SU1062833A1 - Device for stabilizing output voltage frequency of direct-type frequency converter - Google Patents

Abstract

DEVICE FOR VOLTAGE STABILIZATION RATE output direct frequency converter comprising a stabilized clock pulse generator, whose output is connected to the input of the frequency divider and a synchronizer, characterized in that in order to eliminate subharmonic permanent constituents, it is provided with a two, m and D T -triggerami -trigger, and the output of the frequency divider is connected to the clock input of the first T-trigger, the direct output of which is connected to the D-INPUT of the 33-trigger and with the reset input stabilized clock generator, the synchronizer output is connected to the clock input Q of the D-flip-flop, the inverse output of which is § connected to the setup input of the first T-flip-flop and the clock input of the second T-flip-flop, the output of which is the output of the device. oo w

Description

The invention relates to electrical engineering, in particular, to devices for controlling direct frequency converters.

Devices are known for controlling and stabilizing the direct / converter frequency in an autonomous electric power system, in which the valve groups are controlled from the master oscillator by alternately switching them on with the output frequency, and the rectifying mode pulses are also supplied depending on the polarity of the load current monitored by the sensor current zero i,

A disadvantage of the known device is the limited range of variation of the power factor of the load.

The closest to the technical essence of the invention is a device for controlling the frequency of the direct voltage of the direct frequency converter, containing a stabilized clock and pulse generator, the output of which is connected to the input of the frequency divider, and the synchronizer of the clock.

A disadvantage of the known device is that in the autonomous power supply system sub-harmonic components arise, caused by the difference in the number of sync pulses applied to the positive and negative gates of the irpynn. This phenomenon arises due to the fact that the frequency of the clock pulses depends on the frequency of rotation of the diesel, and the frequency of the master oscillator is not synchronized with the frequency of the clock pulses.

The purpose of the invention is the elimination of subharmonic and constant components of the CCs.

The goal is achieved by the fact that the device is equipped with two T-triggers and a 13-flip-flop, and the code of the frequency divider is connected to the clock input of the first T-flip-flop, the output of which is connected to the P-input of the D-flip-flop pulses, the synchronizer output is connected to the clock input of the D-flip-flop, the inverse output of which is connected to the setup input of the first T-flip-flop and to the clock input of the second T-flip-flop, the output of which is the output of the device.

On the phk, i is a schematic diagram of the proposed device; FIG. 2 shows diagrams explaining his work.

The device contains a stabilized gene | eator of 1 clock pulses, a divider 2 frequencies on triggers

the first T-trigger 3, D-trigger 4, synchronizer 5, the second 13-trigger b

The device for stabilizing the frequency of the direct frequency converter works in the following way.

The generator 1 generates high-frequency clock pulses.

The divider reduces the frequency of the clock

nTI

In 2 times, where P. is the number of triggers in the divider, while the period of operation of the divider is 2 T (, i essentially determines the half period T / 2 of the output voltage of the device and the transformation in general.

The value of T / 2 differs from f T {t), and it does not exceed the period of the clock pulses received from the output of the synchronizer 5. The dTsc addition is introduced so that in the half period of T / 2 the integer number of clock pulses fit. Since the clock frequency cannot change abruptly, the next (negative) half-period of the output voltage of the device will contain the same number of clock pulses as in the positive half-period, i.e. the shape of the output voltage will be symmetrical.

The selection of an integer number of clock pulses in each half-period is carried out using triggers 3 and 4. This is done as follows. After the end of the counting period Tjjj, the trigger 3 is set to the state. When the clock pulses come from synchronizer 5, trigger 4 is set to the state

with its inverse

and the signal

the output resets the trigger 3 to the state O and simultaneously flushes the trigger 6. Thus, the output trigger 6 is always shifted only at the moment of arrival of the clock pulse. The flip-flop 4 returns to state () n1X) when the next clock pulse arrives. It will be noted that while trigger 3 remains in state, generator 1 is prevented from entering generator 1 and the clock pulses are not input to the divider input. Run the generator. 1 is carried out when switching

ABOUT

trigger 3 to state

those.

on the front of the clock. This ensures an integer number of sync pulses over a half period of T / 2 and a constant T interval, as well as a higher frequency stability of the control Hc1 converter.

The effectiveness of the proposed device in comparison with the known is that it provides

higher stability of the half-periods of the output voltage, the absence of subharmonic components and a constant component in the output voltage of the converter, since the device guarantees that the number of clock pulses is equal in each half-period of the output voltage.

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Claims (1)

DEVICE FOR STABILIZING I FREQUENCY OF OUTPUT OUTPUT VOLTAGE A JET FREQUENCY CONVERTER, containing a stabilized clock generator, the output of which is connected to the input of the frequency divider, and a synchronizer, characterized in that in order to eliminate subharmonic constant components, it is equipped with two--, mT-triggers and a D-trigger, and the output of the frequency divider is connected with the clock input of the first G-trigger, the direct output of which is connected to the D-input of the D-trigger and with the enable input of the stabilized clock generator, the synchronizer output is connected to the clock Valid mu D-flip-flop inverse output of which is connected to the adjusting input of the first T-flip-flop and a clock input vtorogoT -triggera whose output & is the output of the device. With figure 1