SU1062718A1 - Multichannel relay correlator - Google Patents

Abstract

A MULTICHANNEL RELAY CORRELMETER containing an analog-to-digital converter, whose information input is the first input of the correlator, and the synchronization input is combined with the synchronization input of the first shift register and connected to the output M-cr of the counter containing Iw + rn) bits (where t 1 f M is the number of samples in the i-th block, i 1, N), the output of the highest bit of which is connected to the first BXOJJOM synchronization of the second. P shift shift containing D cells (where F is the number of ordinates of the correlation function), input counter combined with sec the synchronization input of the second shift register and the synchronization input of the adder and connected to the pulse generator output, the bit outputs of the upper cell of the second shift register are connected to the corresponding inputs of the first input group of the first cell, the inputs of the second input group of the first cell are connected to the corresponding bit outputs of the first shift register The information input of which is connected to the output of the comparator, the input of which is the second input of the correlometer, about tl. and so that, in order to improve speed, a calculation block is entered into it (L no interim amounts, the informational inputs of which are connected to the corresponding bit outputs of the English-digital converter, and the inputs of the reading address are connected to the corresponding the bit outputs of the high cell of the second shift register, the synchronization input of the intermediate sums calculator are connected to the output of the pulse generator, and the outputs are connected to the corresponding information inputs of the adder.

Description

2. A correlometer according to claim 1, wherein the intermediate amount calculation unit contains an adder, a memory element of the decoder and a counter containing () bits, the bit outputs of which are connected to the corresponding inputs of the decoder, and the outputs of the lower order The high and low output of the counter is connected to the corresponding input address of the memory element's write address, the synchronization input of which is combined with the synchronization input of the counter and is the synchronization input of the block, the output of the high discharge of the counter is connected to the corresponding Valid address reading memory element, the other inputs of which the read address are respective inputs of the read unit address inputs of the first-group element outputs Paglia tee connected to respective inputs of the first group of information, the adder inputs, the outputs of which are connected to respective data inputs. memory element ,. the outputs of the second group of outputs of which are the corresponding outputs of the block, the input controlling the operation mode of the adder is connected to the output of the decoder, and the inputs of the second group of information inputs are the corresponding information inputs of the block;

one

The invention relates to specialized computer facilities and can be used to construct multi-channel relay correlometers of random stationary ergodic signals.

A correlometer is known, a relativizing relay algorithm. Calculating an estimate of the mutual correlation function, comprising a linear frequency converter, a delay unit, limit amplifiers, ambiguity elements, and accumulators 13.

However, the relatively low speed of this correlometer does not allow to investigate high-frequency signals.

Closest to the proposed technical entity and the proposed result is a device containing an analog-to-digital converter, the information input of which is the first input of the correlometer, the control input of the analog-digital converter connected to the first output of the control unit containing a pulse generator and a counter, and output to the first input of the decoder containing elements AND or ILIG; the second input of which is connected to the output of the comparator, the first - to the input of the fixation block of the mean square deviation, and the second output to the input of the adder, the control input of which is connected to the second output of the counter, the input of which is connected to the output block of the fixation of the standard deviation, and the third output to the first input of the comparator the second input is 12 (12.

A disadvantage of the known device is the relatively low speed due to sequential data processing. The purpose of the invention is to increase the speed of the correlometer, i.e. Expansion of the frequency range of explored Bf .ttjx signals.

This goal is achieved by

The iTO is a multichannel burdock correrelometer, containing an analog-to-digital converter, whose information input is the first input of a correlometer, and the synchronization input is combined with the synchronic input of the first shift register and connected to the output of the M-th digit from the receiver containing) ampere (where M - the number of samples in the i-th block, i 1 ,,

the output of the higher bit, which is connected to the first input of the synchronization of the second shift register, containing D cells (where D is the number of Ordinates of the correlation function),

the counter input is combined with the second synchronization input of the second shift register and the synchronization input of the adder and connected to the output of the pulse generator, the bit outputs of the upper cell of the second shift register are connected to the corresponding inputs of the first group of inputs of the first cell, the inputs of the second group of inputs of the first cell of which are connected to corresponding to the bit outputs of the first shift register, the information input of which is connected to the comparator output, the input of which is the second input of the correlator, the block you entered the intermediate sums, the information inputs of which are connected to the corresponding bit outputs of the analog-digital converter, and the write address inputs are connected to the corresponding bit outputs of the upper cell of the second shift register, the sync of the intermediate sum calculation unit is connected to the output of the pulse generator, and the outputs are connected to corresponding to the information inputs of the adder. Moreover, the intermediate sum calculation block contains an adder, a memory element and a counter containing (+ 1) bits, the bit outputs of which are connected to the corresponding inputs of the decoder, and the low-voltage outputs W and the high digit output of the counter are connected to the corresponding inputs the memory element write address, the synchronization input of which is combined with the synchronization input of the counter and is the synchronization input of the block, the high-order output of the counter is connected to the corresponding input of the memory element reading address, the rest the read address inputs of which are with the corresponding inputs of the block reading address, the outputs of the first group of outputs of the memory element are connected to the corresponding inputs of the first group of information inputs of the adder, the outputs of which are connected to the corresponding information inputs of the memory element / outputs of the second group, one of which are the outputs of the block; the input of the control of the operation mode of the adder is subunit to the output of the decoder, and the inputs of the second group of information inputs are the corresponding ion inputs of the unit. FIG. 1 shows a structural diagram of a multi-channel relay correlometer; Fig. 2 is a block diagram of a block for calculating subtotals. The correlometer contains an analog-to-digital converter (dcp 1, block 2 for calculating intermediate amounts Lummatf 3, comparator 4, first 5 and second 6 shift registers, counter 7, generator 8 pulses, Block 2 for calculating intermediate sums contain adder 9, decoder 10 , memory element 11 and counter 12. The correlometer works as follows ... A random input signal is converted into ADC 1 into binary multi-digit numbers with a frequency f equal to the pulse frequency TI 1 of output G9 of counter 7, containing CL + fpi bit don sequence the samples of the input signal are divided into blocks by M 2 numbers, where i 0,1 0,1,.,., (N-1) is the block number, j О, 1, ..., (M-1) is the number of the block. From the numbers of each block with number i, coming from the bit outputs of the A / D converter 1 to the corresponding inputs of one of the groups of information inputs of the driver 9, during the time M of TI 1 pulses in block 2, 2 sums №-1 are formed. , x ,, where aj is the value of the bits of the binary number of the sum number A (a. , a, .., a g ... "a4d L, A o, 1, ...", h,. . . , and | U i (- 1). , Frequency f f2 / 2, where f2 is the frequency of the output pulses of TI 2 of the generator 8 pulses. The pulses TI 2 arrive at the synchronization input of the memory element 11 of the block 2 calculating intermediate sums and the input of counter 12, in which a (M + P1 + 1) -bit binary code is formed (0 I a, ..., aj consisting of three parts: n the least significant bits are equal, L-number of the sum 8d,;, are discharged, adc +, ..., a; c) j-number of the unit of the block with i the most significant category 3 | L O Pu i even, hell, 1 for 1 odd. For each value of Xjj, the number l in turn takes values from 0 to (1). In the decoder 10 a number is formed aa aa a, j. .. a ,, which is input to the control of the operation mode of the adder 9, operating in the addition mode, with aj 0, and in the subtraction mode with a 1. The number a is equal to the value of the digit with the number of the number A. Memory element 11 contains memory cells whose width corresponds to the maximum value of the sum. The inputs of the memory entry address of the memory element 11 are received from the outputs of the M mssspxh bits and the high bit of the counter 12 (“+ 1-bit code (ao a, ..., aa}), and to the read address of the a (G f 1) bit code || th code, lower M bits KOTjopo-go are equal to the output code of the shift register 6 and the high bit is equal to 9-inverse value of the output value of the high-resolution counter 12. Memory element 11 can be split two halves with 2 cells each, the right of which includes cells with numbers 0,1,. ,, М-1, and the second with cells with numbers Л, (M-fir, .., (2M-i). In the cells with the numbers L of one half of the email of the memory 11, the formed amounts are H4, in the memory cells of the other half the sum Sy is accumulated. For even i (o) the cell of the first (second) memory element 11 is connected to 9 (3) adder / for odd with adder 9 (h; the cells of the second are connected (the first half of the element 11. The intermediate value of the sum S ";.,. from the memory cell with the number A of one of the half of the memory element 11 goes to the corresponding inputs of another group of information inputs of the adder, 9 with high potential on input sync input random signal y (1;) transform tc in Comparats e 4 sig I Go, if y 70, and if y i O, which in the Mth shift register 5, containing M bits, is quantized by TI 1 pulses in time with frequency f and converted to M This is a binary code B (, ..., c, c:) d, where B ,, - j Bt (Mi + j) / gL. i is the block number j 0,1,. ,, ,, (М-1) the number of the number in the block,. , .. ((- 1J J.; The second shift register 6 contains D m – 2 cells of the size M, where D is the number of the e determinants in "t ordinates of the correlation function. Pulses TI 1, output from the output of the generator 8 pulses to the corresponding synchronization input of the shift register 6, shift the information therein by one M-cell. The bit outputs of the higher cell of the shift register 6 are connected to the corresponding inputs of the first group {INPUTS of the first (young cell. TI pulses 3, frequency Copods of f from the output of cxaiMuero bit counter 7 on the Dfugo I input sync tions sdenga register 6, it is recorded in the first cell eree e sootvetstvuits second inputs of first OR input group

reduction of memory element 11 (TI). In cyivwaTope 9, one term is added to the subtotal.

a5Ai-H ,, i.N (-i

the result, with TI, is recorded in the same memory cell with A. After the completion of the formation of the sums SA: + I (at time t, M / Ji) half of the memory element 11 are switched.

An example of the formation of amounts of rear

: at shch 1, m 2, a. (afa) .. cells code Bj. formed in register 5 shifts The bit outputs of the upper cell of shift register 6 are connected to the corresponding inputs (to M younger bits; read addresses of the element 11 of the block memory 2. On the bit outputs of the upper cell of the shift register 6 with the frequency fi, the codes B |: j) i, are alternately generated. j which is chosen from the element 11 of the memory of the sum of LI L, “1C g-, rfc j where to 0,1, ..., (C-1), The sampling time of the sums when changing from o other (g-1) is equal to t2 Bjfl ; -2 ie during the cycle time of the shift register in block 2, the calculation of subtotals results in the formation of the total number of 4. In adder 3, a spool of ML, IL and MN VK Г MN TS .J are formed which are equal to the estimates of the ordinates of the relay correlation function calculated by the device, known by the device, MN readings of the input signals at D M2. In order to obtain the kth ordinal estimate of the higher correlation function of the signals X (t) and Y (t), it is sufficient, as in the known device, to multiply the value of H by a factor of J; 1 from the distribution of input signals. VL (MK / €.-Un. The introduction of a block for calculating subtotals makes it possible to increase the speed of the correlator by M times. Indeed, if in a known device for blocks X | f and the formation of sum S is done in M cycles, in the proposed device for of each block Hu in advance, regardless of the values of the signal Y {t7, sukyy s are prepared for all possible values of B and for a particular B. In the adder 3 of block 2, a corresponding amount is generated by one-cycle operation. If, for example, M 5, D 5-2 160, f. Quantization frequency of input signals, then f2 32f for the proposed correlometer I. f2 l60f for the known, which allows the use of elements with lower speed. With the same TI 2 pulse frequency, the highest frequency of the signals under study is M times higher in the proposed device.

Claims (2)

1 MULTI-CHANNEL RELAY CORRELOMETER containing an analog-to-digital converter, the information input of which is the first input of the correlometer, and the synchronization input is combined with the synchronization input of the first shift register and connected to the output M-discharge of the counter containing ΐΑΛ + m) discharges (where m = = ςος ₂ M, And is the number of samples in the Ϊ-Μ block, i = Ι, Ν), the output of the highest bit of which is connected to the first synchronization input of the second shift register containing 'D cells, (where' .E is the number of ordinates of the correlation function) , counter input combined with the second synchronization input of the second shift register and the synchronization input of the adder and connected to the output of the pulse generator, the bit outputs of the senior cell of the second shift register are connected to the corresponding inputs of the first group of inputs of the first cell, the inputs of the second group of inputs of the first cell of which are connected to the corresponding bit outputs of the first shift register, the information input of which is connected to the output of the comparator, the input of which is the second input of the correlometer, about t. And moreover, in order to increase the speed of SB operation, an intermediate sum calculation unit is introduced into it, the information inputs of which are connected to the corresponding bit outputs of the analog-to-digital converter, and the read address inputs are connected to the corresponding bit outputs the older cells of the second shift register, the clock input unit calculating subtotal connected to the output of the pulse generator and outputs connected to soot- ¹ sponding data inputs' of the adder. SU ,, .. 1062718 Fig 1 2. The correlometer according to π. 1, characterized in that the intermediate sum calculation unit contains an adder, a memory element, a decoder and a counter containing (Λί + ιήνί) bits, the bit outputs of which are connected to the corresponding inputs of the decoder, and the outputs L * of the lower bits and the output of the highest bit the counter is connected to the corresponding inputs of the write address of the memory element, the synchronization input of which is combined with the synchronization input of the counter and is the synchronization input of the block, the output of the highest level of the counter is connected to the corresponding input of the address h a memory element, the remaining read address inputs of which are the corresponding inputs of the block read address, the inputs of the first group of outputs of the memory element are connected to the corresponding inputs of the first group of information, the inputs of the adder, the outputs of which are connected, to the corresponding information inputs of the memory element, the outputs of the second group of outputs of which are the corresponding outputs of the block, the input for controlling the operating mode of the adder is connected to the output of the decoder, and the inputs of the second group of information inputs are corresponding information inputs of the block;