SU1056175A1 - Data input device - Google Patents

Abstract

yCTPOf CTBO FOR INPUT OF INFRAM MAATION, containing a switch, the outputs of which are connected to the counting inputs of the meters, the installation inputs of which are connected to the outputs of the first group of the control unit, the data drivers, the outputs of which are connected to the information input of the data switch, the control inputs of the data drivers are connected to the outputs of the second group control unit, input-: the output of the data switch is the input-output of the device, the output of the data switch is connected to the first input of the control block, a group of inputs, the second and the third inputs of which are addresses of the address, read and write control of the device, respectively, of which. This is because, in order to improve the reliability of the device by eliminating signal races when retrieving information from the counters and ensuring control over their overflow, delay elements, buffer registers, information reception gating blocks, triggers, counter overflow register, and block formers are introduced into it service signals, the first element I, the inputs of the delay elements and the first inputs of the information receiving gating units are the information inputs of the device, the outputs of the delay elements are connected to one input the second inputs of the gates of the reception of information are connected to the outputs of the second group of the control unit, the third inputs of the outputs of flip-flops, the synchronization inputs of which are connected to the first output of the control unit, and the information inputs of the triggers are connected to the outputs of the gates of the reception of information reception connected to the inputs control records of the buffer registers, the information inputs of which are connected to you (L of the moves of the corresponding counters, and the outputs - to the inputs of the corresponding data overflowers, one of the overflow outputs is connected to one of the overflow register inputs, and the overflow outputs of other counters are respectively connected to other overflow register inputs and to the other ports: switch inputs, overflow register outputs are connected to the service signal formers and to the inputs of the first element AND, the output of which is the control output of the device interrupt request O1, the output of the shaping unit. The service information is connected to the information input of the data switch, and the control input is connected to the second output of the control unit, the control input of the data switch is connected to the third output of the control unit, 2. The device according to claim 1, and in that the information reception gating unit comprises a second And element and a one-shot, whose input is the first input of the block; and the one-shot output is connected

Description

with the first input of the second element And, the second and third inputs of which ow -. The second and third block inputs, respectively, and the output block output, respectively.

3. The device according to claim 1, that is, so that the control block contains address and write, read and write decoders, the first and second inverters, the element LI-NE, the first and second elements AND-NOT The group of elements AND and the third element AND, the address inputs of the address, write and read decoders are a group of inputs of the block, the control input of the address decoder is connected to the output of the OR-NOT element, the first input of which is connected by the first input of the first AND-NAND and the output of the first inverter , the second input of the element OR NOT / connected to the first input of the second ele The AND-NOT and the output of the second .inverter, the inputs of the first and second inverters are the second and third inputs of the block, respectively, the output of the address decoder is connected to the second inputs of the first and second elements AND-NOT, the output of the first AND-NOT element is connected to the control input of the decoder write, the output of the second element AND-NOT connected to the control input, read decoder, the outputs of which are connected to the corresponding inputs of the third element AND, respectively, the outputs of the second group and the second output of the block, the output of the third element And I is the third output of the block, the first inputs of the elements of the AND group are connected to the first output of the write decoder, the second inputs are the first input of the block, and the outputs are the outputs of the first group of the block, the second output of the write decoder is the first output of the block.

The invention relates to computing technology and can be used as an input device for cellular computers used in process control systems, in automation systems of scientific experiments. A device for inputting information is known, which contains an accumulation unit, an interface unit with a sensor, a local control unit. The output of the interface unit is connected to the first input of the local control unit, the second input cat is connected to one of the device inputs, and the output is connected to the device output control l. A disadvantage of this device is its complexity. It is also known to have an information input device comprising an accumulation unit, a reception register, an input switch, an adder and registers; by the number of connected sensors pj. The disadvantage of the device is limited reliability. Closest to the invention is an information input device comprising binary counters, a switch having counting and overflow inputs, interfacing circuits of data transmitters, a transceiver unit and a control unit, and the switch outputs are connected to the counting inputs of binary counters , whose reset inputs are connected to the reset outputs of the control unit, the outputs of the data transmitter units are connected to the transceiver unit, the control inputs of the data transmitter units are connected to the control outputs laziness input control unit, the control unit transceivers input is connected to the first output of the control unit, vhodvyhod transceiver unit connected to the data lines of the interface bus transceiver unit output is connected to the data entry unit | control, which is connected to the address lines and the read and write control lines of the ST bus. However, the known device also has limited reliability, since there is no possibility of hardware detecting overflow of counters and eliminating race signals when reading information from them. The purpose of the invention is to increase the reliability of the device by eliminating the races of the signals when retrieving information from the counters and ensuring control over their overflow. : This goal is achieved by the fact that the input device containing the switch, the outputs of which are connected to the counting inputs of the meters, the installation inputs of which are connected to the outputs of the first group of the control unit, the data drivers, the outputs of which are connected to the information input of the data switch, the control inputs of the drivers data is connected to the outputs of the second group of the control unit, the input-output of the data switch is the input-output of the device, the output of the data switch is} to the first input control locus, a group of inputs, the second and third inputs of which are the read and write control address inputs of the device, respectively, introduced delay elements, buffer registers, information reception gating units, triggers, counter overflow register, service signal conditioner block, first I element, inputs the delay elements and the first inputs of the information reception gating units are the information inputs of the device, the outputs of the delay elements are connected to one input of the switch, the second input the information reception gates are connected to the outputs of the second group of the control unit, the third inputs with the trigger outputs, the synchronization inputs of which are connected to the first output of the control unit, and the information inputs of the triggers are connected to the output of the data switch; registers, informational inputs of which are connected to the outputs of the corresponding counters and outputs - to the inputs of the corresponding data drivers, the output is overflow One of the counters is connected to one input of the overflow register of the counters, and the overflow outputs of the other counters are respectively connected to other inputs of the overflow register of the counters and to other inputs of the switch, the outputs of the register of overflow of counters are connected to the input of the block of signal conditioners and the inputs of the first And element whose output is the control output of the interrogation-interrogation device, the output of the overhead information driver block is connected to the information input of the data switch, and control stroke - with the second output of the control unit; the control input of the data switch is connected to the third output of the control unit. i

In addition, the information reception gating unit contains a second element And a one-shot, the input of which is the first input of the block, and the output of the one-shot is connected to the first input of the second element AND, the second and third input of which is the second and third inputs of the block respectively, and the output of the block .

In this case, the control unit contains address and write and read decoders, the first and second inverters, the OR-NOT element, the first and second AND-NOT elements, the AND group and the third AND element, the address inputs of the address, write and read decoders are a group of block inputs , the control input of the address decoder is connected to the output of the OR-NOT element, the first input of which is connected to the first input of the first element AND-NOT li

0 the output of the first inverter, the second input of the element OR NOT connected to the first input of the second element AND-NOT and the output of the second: inverter, the inputs of the first and second Inverters are 5 with the second and third inputs of the block, respectively, the output of the address decoder is connected to the second inputs of the first and the second element is NOT, the output of the first element is NOT connected to

the control input of the descrambler

b, the output of the second element AND-NOT is connected to the control input of the Read decoder, the outputs of which are connected to the corresponding AND inputs of the third element AND and are respectively the outputs of the second group and the second output of the block, the output of the third element AND is the third output of the block, the first inputs Elements And groups are connected to the first output of the write decoder, the second inputs are the first input of the block, and the outputs are the outputs of the first group of the block, the second output of the write decoder is the first output 5 of the block.

The drawing shows a diagram of the proposed device ..

The device contains information inputs 1, junction blocks 2, opto trones 3, amplifiers 4, delay elements 5, switch 6, counters 7, buffer registers 8, counter overflow register 9, service signal conditioner block 10, first 5 And 11 elements, output 12 interrupt request device, interface i-in 13, data generators 14, data switch 15, data bus 16, control unit 17, first 18 and second inverters 19, OR-NOT element 20, first and second elements AND-HE 21 and 22, address decoders 23, records 24 and readings - 25, third element, And 26, group e The elements And 27, the inputs 28 and 29 e of the recording control 28. and the reading 29 of the device, the input 30 of the device address, the triggers 31, the information gating units 32, the one-shot 33 and the second element 34.

0 The device operates as follows.

Pulse signals from the sensor at the inputs 1 through the blocks 2 of the conjugation, elements 5 of the delay and KOMN yTaTOp 6

5 arrive at the input of the counter 7. Each

7 has a fixed number of bits. In the process of counting pulses on the counter 7, a counter overflow signal may occur, which is fed to the input of switch b and the input of the register 9 overflow of counters or only to the input of register 9,

The required width of the counter for receiving information from this or that sensor is provided with a switchboard switch b, representing the type of field, on which jumpers are installed, necessary for the selected operating mode. At that, the counter overflow signal arrives jjH6o only at the input of register 9 overflow of counters, or else during the course of another counter of group 7. In this case, the counting of the input pulses exists by means of successively connected counters 7, which represent a counter of greater magnitude.

In the drawing of the GGOCA, the installation of a multi-channel jumbo junction.

The overflow signals of the counters arrive at the input of the register 9 overflow of counters / logical 1 in the bits of which correspond to the overflow of individual counters.

The information from the output of the overflow register 9 is transmitted to the input of the overhead signal generator unit 10 (overflow information, the inverse outputs of the overflow register 9 of the counters are connected to the AND 11 element, as a result of which the interface bus 13 interrupts at 12 counter 7.

The contents of counter 7 are rewritten into a buffer register 8 and fed to the input of data drivers 14 if there is no inhibitory signal generated by gating units 32 receiving information on the recording control input of the buffer register 8. The signal from control unit 17 permitting data transfer from the driver 14 data, simultaneously enters the input of block 32, which generates a signal prohibiting the recording of information from counter 7 to the buffer register 8 for the entire duration of reading digital computational information. .

The signal from the control block 17 is set to the logical state: the outputs of those flip-flops 31, the information inputs of which are logic 1 from the output of the switch 15. The flip-flops 31 through the block 32 also prohibit the recording of information from the counters 7 to the buffer registers 8. The reset of the flip-flops 31 is effected by a signal from the control unit 17 in the presence of logic O

information inputs. Block 32 is supplied with an input pulse of block 2, which also prohibits the recording of information from counter 7 into the buffer register 8. At the same time, the same pulse through delay element 5 and switch b is fed to the input of counter 7, and the pulse delay time is less than the pulse duration output one-shot 33.

Thus, the recording of information from counter 7 into the buffer register 8 is enabled by block 32 only after the information is entered into counter 7. The contents of one or several counters 7 are reset to logical O when the corresponding reset inputs of counters 7 are fed from the block 17 controls Information from the outputs of the buffer registers 8 and the register 9 of the overflow of the counters is fed to the inputs of the data drivers 14 and the block 10 of the signal drivers. According to the signal from control block 17, information from the output of the corresponding driver 14 or from block 10 is transmitted via switch 15 to data bus 16.

The control unit 17 from the interface bus 13 receives signals on inputs 28-30.

The presence of a signal at input 28 or 29 determines the operating mode of the device: write or read.

; The higher address bits that specify the device address are received at the input

 30 to the address input of the address decoder 23, the control input of which is connected through the element OR-NOT 20 and the inventories 18 and 19 to the control inputs of the record 26 and the read 27.

When accessing the device, the output of address decoder 23 generates a signal that serves to control either write decoder 24 in write mode and read decoder 25 in read mode. The address bits of the address decoder are received at the address inputs of these decoders. The signals that occur at the output of the write decoder 24 serve to control the triggers 31, as well as to form a reset of those counters 7, which are determined using logic 1 in the corresponding information bits passed from the output of the switch 15. Signals that occur at the outputs of the decoder 25, are used to input information or another generator 14 or block 10 to the switch 15, as well as to form a signal at the output of the AND element 34, which serves to control the switch 15 when issuing information 5, not to the data bus 16.

The application of the invention provides the hardware ability to detect the overflow of counters and in this case interrupt the program of the digital computer interacting with the device; the ability of the digital computer to read the instantaneous state of an arbitrary number of consecutively connected counters by interrogating buffer registers in which the instantaneous state of the counters is recorded at a certain digital computer.

Since the counters operate in i-continuous mode, at the time of the sequential polling of the digital computer of the fixed buffer registers, as a result of incrementing, a change in the state of the Leu counter may occur, which eliminates errors when the digital computer reads the instantaneous state of the counters.

Claims (3)

f INFORMATION INPUT DEVICE, comprising a switch, the outputs of which are connected to the counting inputs of the counters, the installation inputs of which are connected to the outputs of the first group of the control unit, data shapers whose outputs are connected to the information input of the data switch, the control inputs of the shapers of data are connected to the outputs of the second group of the block control, the input-output of the data switch is the input-output of the device, the output of the data switch is connected to the first input of the control unit, a group of inputs, the second and The third inputs of which are the inputs of the address that controls the reading and writing of the device, respectively, with the aim that, in order to * increase the reliability of the device by eliminating signal racing when taking information from meters and providing control of their overflow, delay elements, buffer registers, gating blocks for receiving information, triggers, counter overflow register, block of signal conditioning drivers, first element AND, inputs of delay elements and first inputs of gating blocks are entered into it The information is the information inputs of the device, the outputs of the delay elements are connected to one of the inputs of the switch, the second inputs of the gates of the reception of information are connected to the outputs of the second group of the control unit, the third inputs are the outputs of the triggers, the synchronization inputs of which are connected to the first output of the control unit, and the information inputs of the triggers connected to the output data switch gating information receiving unit outputs connected to control inputs separately signed _e za- buffer registers, Informational SB onn whose inputs are connected to the outputs of the respective counters, and the outputs are connected to the inputs of the corresponding data shapers, the overflow output of one of the counters is connected to one of the inputs of the counter overflow register, and the overflow outputs of the other counters are respectively connected to the other inputs of the counter overflow register and to the other ^: inputs of the switch, the outputs of the counter overflow register are connected to [the input of the service signal conditioner unit and to the inputs of the first AND element, the output of which is the control by the output of the interrupt request of the device, the output of the block is formed * The service information line is connected to the information input of the data switch, and the control input is connected to the second output of the control unit, the control input of the data switch is connected to the third output of the control unit. 2. The device according to claim 1, with the proviso that the information reception gating unit comprises a second AND element and a one-shot, the input of which is the first input of the block; and the output of the one-shot is connected .1056175 with the first input of the second element And, the second and third inputs of which is -. are respectively the second and third inputs of the block, and the output is the output of the block. 3. The device according to claim 1, the fact is that the control unit contains address, write and read decoders, the first and second inverters, the OR-HE element, the first and second AND-NOT elements, the group of elements And the third AND element, the address inputs of the address, write and read decoders are a group of block inputs, the address decoder control input is connected to the output of the OR-NOT element, the first input of which is connected to the first input of the first AND-NOT element and the output of the first inverter, the second input element OR-HE. connected to the first input of the second AND-NOT element and the output of the second inverter, the inputs of the first and second inverters are the second and third inputs of the block, respectively, the output of the address decoder is connected to the second inputs of the first and second elements AND, the output of the first element AND connected to the control input of the write decoder, the output of the second AND element is NOT connected to (. the control input, the read decoder, the outputs of which are connected to the corresponding inputs of the third AND element and are respectively the outputs of the second group and the second output of the block, the output of the third element AND is the third output of the block, the first inputs of the elements AND groups are connected to the first output of the recording decoder, the second inputs are the first input of the block, and the outputs are the outputs of the first group of the block, the second output of the recording decoder is the first output of the block ..