SU1043662A1 - Fourier coefficient computing device - Google Patents

Abstract

1. A DEVICE FOR CALCULATING FOURIER COEFFICIENTS, containing an analog-digital converter, an arithmetic unit consisting of two arithmetic units, a coefficient memory unit, a first switchboard, a first and a second shift unit, each of which consists of four nodes shift, and a control unit, the information input of the analog-digital converter being the information input of the device, and the output connected to the first information input of the first switch, the output of the coefficient memory module connected to the input Am coefficients of arithmetic units of an arithmetic unit, the outputs of which are connected to the second and third information inputs of the first switch, the outputs of the first, second and third shift nodes. In each shift block are connected to information inputs of the second, third and fourth shift nodes, respectively, information, inputs of the first and the third shift nodes in each shift block are connected to the corresponding outputs of the first commutator, the address inputs of the coefficient memory block, as well as the control inputs of the analogue center the arrays, the arithmetic nodes in the arithmetic unit, the first switch and the shift nodes in the first and second blocks of the shift are connected to the corresponding control outputs 6LOK4, characterized in that it contains a second switch and a third shift block, consisting of four the shift nodes, with the outputs of the first, second and third shift nodes in the third shift block being connected to the information inputs of the second, third, and fourth shift nodes, respectively, The first inputs of the first and third shift nodes in the third shift block are connected to the corresponding C outputs of the first switch; the outputs of the first, second, third and fourth shift nodes in each shift block are connected to the first, second, third, and fourth groups of inputs of the second switch, respectively. , the first output of the second switch is connected 4 00 to the inputs of the first operands of arithmetic nodes in the arithmetic unit, the second output of the second switch is connected to the inputs of the second operands of arithmetic nodes in the arithmetic Yes, the block, the third and fourth outputs of the second switch are connected to the inputs of the three Tjb operand respectively the first and second arithmetic nodes in the arithmetic block, the control inputs of the second switch and the shift nodes in the third shift block are connected to the corresponding outputs of the control unit, the output of the fourth offset node in the third block, the shift is the output of the device. 2, The device according to claim 1, characterized in that the control unit consists of a tact generator

Description

the output of the pulses, the counter and the fixed memory unit, the output of the clock generator is connected to the input of the counter, the output of the counter is connected to the address input of the fixed memory unit, the outputs of the fixed memory unit are the outputs of the control unit.

The invention relates to computer technology and can be used in digital signal processing systems, diagnostic systems, as well as in an automatic control system. A device for calculating Fourier coefficients, containing two groups of analog shift registers and switches, switching panels, counters and blocks of operational amplifiers tl2, is known. The disadvantages of this device are low accuracy, limited functionality and relatively high complexity and low reliability. The closest in technical solution to the invention is a device for calculating Fourier coefficients, comprising an analog-to-digital converter, a switch, an arithmetic unit consisting of two arithmetic nodes, a coefficient memory block, the first and second shift blocks, each of which consists of four shift nodes , and the control unit f 2 J. A disadvantage of the known device for calculating Fourier coefficients is low speed and, as a result, a narrow frequency range of the input signal, since the analysis The data is fed through an analog-to-digital converter to a block of buffer registers in which the input information is accumulated. After the end of the current implementation of the input signal, the information is written to the first shift block. Such an organization requires a significant investment of time for rewriting information, since with large sample sizes, recording from one shift block can be organized only in a sequential mode. Otherwise, significant hardware costs are required. The purpose of the invention is to increase the speed of the device. The goal is to achieve a device for calculating Fourier coefficients, containing an analogue digital converter, an arithmetic unit consisting of two arithmetic units, a coefficient memory, the first switch, the first and second shift blocks. , each of which consists of four shift nodes, and a control unit, the information input of the analog-digital converter being the information input of the device, and the output connected to the first information To the input of the first switch, the output of the coefficient memory is connected to the inputs of the coefficients of the arithmetic nodes of the arithmetic unit whose outputs are connected to the second and third information inputs of the first switch, the outputs of the first, second and third shift nodes in each shift block are connected to the information inputs of the second, third and the fourth shift nodes, respectively, the information inputs of the first and third shift nodes in each shift block are connected to the corresponding outputs of the first switch, addr The integral inputs of the coefficient memory, as well as the control inputs of the analog-digital converter, arithmetic nodes in the arithmetic unit, the first switch, and the shift nodes in the first and second blocks of the shift are connected to the corresponding outputs of the control unit, contains the second switch and the third shift block consisting of the four shift nodes, with the outputs of the first, second and third shift nodes in the third shift block connected to the information inputs of the second, third and fourth shift nodes, respectively, The inputs of the first and third shift nodes in the third shift block are connected to the corresponding outputs of the first switch; the outputs of the first, second, third, and fourth shift nodes in each shift block are connected to the first, second, third, and fourth groups of inputs of the second switch, the first the output of the second switch is connected to the inputs of the first operands of arithmetic nodes in the arithmetic unit, the second output of the second switch is connected to the inputs of the second operands of arithmetic nodes in the arithmetic block, mp The third and fourth outputs of the second switch are connected to the inputs of the third operand, respectively, of the first and second arithmetic nodes in the arithmetic unit; the control inputs of the second switch and the shift nodes in the third shift block are connected to the corresponding outputs of the control unit; the output of the fourth shift node in the third block, the shift is the output of the device. In addition, the control unit consists of a clock pulse generator, a counter and a constant memory block, the clock pulse output is connected to the counter input, the counter output is connected to the address input of the fixed memory block, and the outputs of the constant memory block are the outputs of the control unit. FIG. 1 is a block diagram of a device for calculating Fourier coefficients; Fig. 2 is a block diagram of the control unit. The device comprises an input bus 1, an analog-digital converter 2, a switch 3, an arithmetic unit 4 consisting of arithmetic nodes 5 and 6, a block 7 of coefficient memory, blocks 8-10 shift, consisting of nodes 11-22 shift, switch 23, output bus 24, block 25 control. The control unit consists of a clock pulse generator 26, a counter 27, and a fixed memory block 28. A device for calculating the Fourier coefficients works as follows. In the initial state, the blocks 8 and the shift do not contain information, as in the shift block 9 in the parallel code there are stored M samples of the previous implementation of the input signal, which was fed to the input 1 of the device, so that zero output is present at the output of the shift node 18 at the output of the node 17 shift - countdown number N1 / 4, at the output of the node 15.sdv ga - counting number 3N / 4. The analog-to-digital converter provides, at the moments when the clock pulse input to its control input, converts the input analog signal fed to input 1 into a digital form at the output. The parallel code of the counts of the current implementation is sequentially loaded through the switch 3 into the shift block so that the first of N implementation counts after N synchronization cycles takes the output position of the shift node 14, the count with the number N / 4 takes the output position at the shift node 13, the count from Rum N / 2 occupies the output position at shift node 12, and counting with number 3N / 4 at the shift node 11. Simultaneously with the loading of the current implementation, the Fourier coefficients are calculated for the implementation stored in the initial state in the shift block 9. The calculation is performed using the Fast Fourier Transform algorithm for real input signals. According to this algorithm, in the first cycle of calculations, the inputs of the arithmetic unit 4 through the switch 23 receive in the parallel code the samples with the numbers O, N / 4, N / 2 and 3N / 4, which serve for the arithmetic unit 4 operands X о, X, Xj and Хз Arithmetic the block performs the following actions on the received operands: Xjj + X2r X + X j; XQ-C21 -i X. The results of these actions are the constituents of the first array of partial sums when calculating the Fourier coefficients. At the same time, at the outputs of the arithmetic unit, the numbers Xp + X2 and are first formed simultaneously. X 5 and then the numbers Xo-X2 and. The values thus calculated are fed through the switch 3 to the inputs of the shift unit 10. The numbers Xd + X and X + Xj are loaded one by one into the shift node 19, and the numbers Xfl-Xj and X -, Xs - into the shift node 21. Information is then shifted, and output positions at shift nodes 1518 are occupied by samples of the processing implementation with numbers 1, N / 4 + 1, N / 2 + 1 and 3N / 4 + 1, which in their turn are operands to calculate the following values of the first an array of partial sums, the values of which through switch 3 are recorded in the shift unit 10, Further, due to performing N / 4 similar operations, the shift unit 9 is cleared, and the shift unit 10 is filled with partial sums of the first array. After that, the outputs of the shift unit 1.0 through the switch 9 are connected to the inputs of the arithmetic unit 4, and the results of the calculations are recorded through the switch 3 in the shift unit 9 as a second array of partial sums. Then the second array is processed in a similar way, and the result of the processing — the third array — is placed in the free shift unit 10. After the operations in the shift block 9, if tog2N is an even number, or in the shift block 10, if 6og2N is odd, the Fourier coefficients are written. At the same time, at the corresponding stages of the calculation, the arithmetic unit can perform, in addition to the indicated actions, operations like Xd + X "-

  Xp-J-x -F. , -x, g |

, F.X2 / ,,

x + FpXj;

where F is the values of the rotation vectors stored in the coefficient memory unit 7 and received at the first input of the arithmetic unit 4,.

the speed of the element base and the clock frequency of operation of the arithmetic unit is chosen so that all iterations on the calculation of the Fourier coefficients are performed for a time less than the load time of the current implementation in block 8 of the shift. Therefore, after the end of the last inertia, the results of the Fourier transform over the previous implementation are output from the device at output 24 in series, number by number in a parallel code. Thus, shear blocks 9 and 10 are cleaned before the loading of the current implementation ends. Upon completion; the current implementation of the next implementation begins to load into the second block of the shift, and the current implementation is processed in the same way, except that the exchange of the operands and the result of the calculations is performed between the first and third blocks of the shift.

The control unit operates as follows.

Suppose that, in the idle state, blocks 8 and 10 of the shift do not contain information, whereas in block 9 of the shift. In parallel code, there are N samples of the previous implementation of the input signal. The first and second switches 3 and 23 are programmed with codes generated at the outputs of control unit 25 so that the first of them connects the outputs of arithmetic nodes 6 and 5 to the inputs of shift nodes 19 and 21, and the second connects the outputs of shift nodes 15-18 to the inputs of the arithmetic unit 4. During the first iteration, the control unit generates the shift pulses for block 8 at the A / D conversion frequency at its outputs. These pulses go to the control inputs of the shift nodes 11-14 and initiate recording of the input realization from the output of the analog-digital converter 2 through the first cockshutter 3 to the shift block 8 at the input of the slip node 11. At the same time, shift pulses are applied to blocks 9 and 10 of shift, and the synchronization frequency of block 9, from which four operands are counted for each clock cycle at the outputs of shift nodes 15-18 through the second switch 23 to the arithmetic unit 4, is half the frequency of shift in the block 10, in which; the results of intermediate calculations are written in pairs from arithmetic nodes 5 and 6 through the first switch 3, Arithmetic nodes 5 and 6 are tuned by the codes supplied to their control inputs to the operations that must be performed during the first iteration. The contacts for performing the operation multiplying by the coefficient is fed to the arithmetic unit 4 from the coefficient memory unit 7, addressed by the group, the outputs of the control unit 6.

This order of operation is maintained until the shift block 9 is empty. And the block 10 is not filled. Thereafter, the codes controlling the switches and tuning the arithmetic unit are changed so that the outputs of the shift nodes 19-22 are connected to the inputs of the arithmetic unit 4, and the outputs of the arithmetic unit are connected to the inputs of the shift unit 9. The synchronizing pulses of the doubled frequency begin to arrive at the input 9 of the block, and at the synchronizing input of the block 10 the pulses are applied twice as rarely. At the end of the second iteration, the state of the outputs of the control unit changes again in accordance with the selected algorithm. The signals generated at the control inputs of the analog-to-digital converter 2 are asynchronous with respect to the rest of the control signals. The sequence of these pulses stops after filling in the shift block 8, by this time all the iterations have been completed and the result of the conversion is output to the external device via output 24.

The proposed design and order of operation of the device for calculating Fourier coefficients allows the calculation of the Fourier transform for relatively wideband signals in real time, which is not achievable in the known device.

Claims (2)

1. A DEVICE FOR CALCULATING FOURIER COEFFICIENTS, containing an analog-to-digital converter, an arithmetic unit consisting of two arithmetic units, a coefficient memory unit, a first switch, a first 'and a second shift unit, each of which consists of four' shift units, and a control unit, wherein the information input of an analog-to-digital converter is the information input of the device, A. the output is connected to the first information input of the first switch, the output of the coefficient memory block is connected to the inputs of the coefficients of arithmetic nodes of arithmetic ^ noKa, the outputs of which are connected to the second and third information. the inputs of the first switch, the outputs of the first, second and third shear nodes in each shear block are connected to the information inputs of the second, third and fourth shear nodes, respectively, the information inputs of the first and third shear nodes in each shear block are connected to the corresponding outputs of the first commutator, address inputs of the coefficient memory block, as well as control inputs of the analog-to-digital converter, arithmetic nodes in the arithmetic block, the first switch and shift nodes in the first and second blocks the shear are connected to the corresponding outputs of the control unit, characterized in that, in order to increase the speed of the device, it contains a second switch and a third shear unit, consisting of four shear nodes, and the outputs of the first, second and third shear nodes in the third shear unit are connected to the information inputs of the second, third. and fourth shift nodes, respectively, the information inputs of the first and third shift nodes in the third shift block are connected to the corresponding outputs of the first switch, the outputs of the first of the second, third, fourth and fourth shear nodes in each shear block are connected respectively to the first, second, third and fourth groups of inputs of the second switch, the first output of the second switch is connected to the inputs of the first operands of arithmetic nodes in the arithmetic block, the second output of the second switch is connected to the inputs of the second operands of arithmetic nodes in the arithmetic unit, the third and fourth outputs of the second switch are connected to the inputs of the third operand, respectively *; of the first and second arithmetic * nodes in the arithmetic block, the control inputs of the second switch and the shift nodes in the third 'shift block are connected to the corresponding outputs of the control unit, the output of the fourth shift node in the third shift block is the output of the device. 2. The device according to π.1, characterized in that the control unit consists of a generator of ¹⁰ ns output pulses, a counter and a read-only memory, the output of the clock generator is connected to the input of the counter, the output of the counter is connected to the address input of the read-only memory, outputs read-only memory blocks are the outputs of the control unit. the coefficient-co-commutator is a 2 block consisting of two arithmetic nodes, a coefficient memory block, a first switch, a first and second shift blocks, each of which consists of four shift nodes, and a control unit, the information input of the analog-to-digital converter being the information input of the device, and the output connected to the first information input of the first switch, the output of the coefficient memory block is connected to the inputs of the coefficients of arithmetic nodes of the arithmetic block, the outputs of which are connected s to the second and third information inputs of the first switch, the outputs of the first, second, and third shear nodes in each shear block are connected to the information inputs of the second, third, and fourth shear nodes, respectively, the information inputs of the first and third shear nodes in each shear block are connected to the corresponding outputs the first switch, the address inputs of the coefficient memory block, as well as the control inputs of the analog-digital converter, arithmetic nodes in the arithmetic block, the first switch and the node in a shear in the first and second shear blocks are connected to the corresponding outputs of the control unit, contains a second switch and a third shear block consisting of four shear nodes, the outputs of the first, second and third shear nodes in the third shear unit are connected to the information inputs of the second, third and fourth shift nodes, respectively, the information inputs of the first and third shift nodes in the third-shift block are connected to the corresponding outputs of the first switch, the outputs of the first, second, third and fourth, shift nodes and in each shift block they are connected respectively to the first, second, third and fourth groups of inputs of the second switch, the first output of the second switch is connected 5Q to the inputs of the first operands of arithmetic nodes, in the arithmetic block, the second output of the second switch ('connected to the inputs of the second operands -' arithmetic nodes in arithmetic 10