SU1043621A1 - Device for interfacing subscribers to digital computer - Google Patents

Description

(21) 3437492 / 18-24.

(22) 05.13.82

(46) 09/23/83. Bul No. 35

(72) B, C. Shevkopl with

(53) 681.3.25 (088.8)

(56) 1. Patent. US No. 4,149,241,

cl. 364-200, 1979.

2. US patent No. 4024505, cl. 340-172.5, 1977 (prototype).

(54) (57) A DEVICE FOR CONNECTING SUBSCRIBERS TO A DIGITAL COMPUTING MACHINE, containing two matching blocks, each of which is executed as a group of voltage dividers, and a group of communication blocks with a subscriber, each of which is made in the form of a comparison circuit, register a shift, a decoder, two delay elements and two NOT elements, each input-output of the address, information and control input-output groups of the device is connected to the output of the corresponding voltage divider of each matching unit, the first and second outputs The delay elements of the communication unit with the subscriber are connected respectively to the inputs of rtepBoro and the second. Elements of the communication unit with the subscriber, the inputs of the first and the outputs of the second elements of the NOT communication blocks with the subscriber are connected to the group of control inputs and outputs of the device comparing communication units with the subscriber is connected by a communication address set unit with the subscriber, the inverse output of the comparison circuit of the communication unit from the subscribers is connected to the first input of the OR element of the communication unit with the subscriber, the outputs of the decoder of the communication unit with the subscriber The volume is a corresponding group of device command outputs / characterized in that, in order to increase reliability, it contains an emergency control unit, an address group, an information group, and a group of control inputs / outputs of which are connected respectively to a group of address, information and control device inputs and outputs, and in each communication unit with the subscriber entered four majoritarian

element, element AND, element OR, trigger, pulse generator and threshold node, with the first, second reset inputs of the shift register and the first input of the element and communication units with the subscriber connected to the corresponding input-output of the device control-input-output groups, inputs the threshold node and the majority elements of the communication unit with aboSS nent are connected to the group of address inputs-outputs of the device, the outputs

(L of the threshold node and the first major element of the communication unit with the subscriber are connected respectively with

the second and third input.

ILIT-NOT communication unit with the subscriber, the output of the element OR-NOT communication unit with the subscriber is connected to the information input of the register of the block shift

4 communications with the subscriber, the input of the first element of the delay of the communication unit with the subscriber through the pulse shaper

Ot) the communication unit with the subscriber is connected to the ND by the input of the element I of the communication unit, with the subscriber, the output of the element And the communication unit with the subscriber is connected to the trigger reset input and to the third input of the shift register of the communication unit with the subscriber, output of the first the delay element of the communication unit with

The customer is connected to the sync input of the shift register of the communication unit with the subscriber; the first output of the shift register of the communication unit with the subscriber is connected to the trigger input of the communication unit with the subscriber; the second output of the shift register of the communication unit with the subscriber is connected the input of the decoder flare communication with the subscriber, the output of the trigger of the communication unit with the subscriber is connected. the second input element OR, the output of which is connected to the input of the second delay element of the communication unit with the subscriber, the output of the majority element of the communication unit with the subscriber m, besides the output of the first major element, is connected to the corresponding information input of the decoder and with the corresponding input of the second group of inputs of the unit comparison. with the subscriber, the D input of the trigger of the communication unit with the subscriber is connected to the positive potential level, and the emergency control unit contains fixed memory, three groups of elements NOT, three elements NLN-NOT, trigger, threshold node, four major elements two elements AND, two elements NOT, two delay elements, display node, element NAND, and, outputs The first group of elements is NOT and the inputs of the threshold node; the inputs of the majority elements are connected to the group. the addressable inputs / outputs of the block, the outputs of the majority elements, the output of the threshold node, the output of the first delay element OR are NOT connected to the C input of the trigger, the forward output of which is connected to the input of the display node and the information input of the first group of elements NOT, inverse output .trigger connected with. the first input of the second element OR NOT, the output of the AND element - NOT, the second input of the second element CLI-NO, the information input the first and the control input of the second, the w. delay elements, the reset inputs of the nominal pag and the trigger are connected to the group, control inputs / outputs of the block, the output of the second major element through the first element is NOT connected to the first input of the first element AND, the second input of which is connected to the first indicative output of the permanent memory, to the first input of the third element OR - NOT, to the information input second group ale NOTES, the output of the first element AND is connected to the input of the permission of reception of a constant memory, the third input of the second element OR is NOT connected to the output of the first delay element, the output of the second element OR NOT CONNECT. dinene with the information input of the second delay element and with sync-. dog memory, the first, second and third outputs of the second element, the delays are connected respectively. but with the input of permitting the issuance of a fixed memory, with the control input of the second group of elements with the first input of the NAND element, the second indicative output of the permanent memory is connected to the second input of the third, the OR OR NOT element and through the second element NOT the second input of the NAND element, the output of the third element OR-.NE and the second output of the second element of the delay through the second element AND are connected to the control input of the third group of elements, the OUT of which and the outputs of the second group of elements are NOT connected to the Ying group .formatsirnnyh in moves-outs of bl An informational output that is connected to the informational input of the third group of elements NOT and to the address input of the permanent memory,. the control input of the first group of elements is NOT and. D-input trigger connected to the level of positive potential. . .

The invention relates to computing technology and can be used in computing devices built on the principle of a common highway to ensure proper control of subscribers in the case. a failure of the address bus lines A device for interfacing subscribers with a digital computer is known, containing active and passive units combined by a common highway, as well as a control unit whose output is connected to the off input of the power supply 1. . - During operation of the device, the trunk is periodically released, i.e. in which the processor operates according to internal firmware and is not yet ready to turn the trunk to the outside world to read the next instruction or operand, to record the result in the like. At these intervals, certain potentials should be established on all address and information lines of the trunk: using the main elements, with an open collector — high, with an open emitter — low. If at least on one of the lines the specified condition is not fulfilled, then this means that further work of the digital computer is impossible due to information distortions.

transmitted by highway. Therefore, the control unit turns off the power of the failed PBM and the controlled object either ceases to receive control actions from the digital computer, l-for it is connected to another backup PVM. Loss of control is unacceptable for a certain class of objects; on the other hand, maintaining the second JIBM in the hot standby mode is not always economically sound.

The closest to the invention according to the technical essence and the achieved result is a device for interconnecting cPVM subscribers, containing a group of subscriber units and two matching units, address inputs-outputs, matching units are combined with the address inputs of subscriber units and are address input-outputs devices, informational inputs-outputs of matching blocks are informational inputs-outputs of a device, control inputs-outputs of matching blocks combined with control inputs-outputs of a subscriber Entrance units are the device control inputs-outputs, the matching blocks contain resistor dividers according to the number of inputs-outputs of the device, the device’s input-output is connected to the middle points of the respective resistor parts of the first and second matching blocks, the subscriber unit contains the block, compare, decoder, OR-NOT, shift register, first and second delay elements, whose inputs are connected respectively to the inputs of the first and second inverters, the output of the comparison unit is connected to the first input nta OR-NOT, the input of the first delay element is the first control input of the subscriber unit, the output of the second inverter is the control output of the subscriber unit, the outputs of the decoder a, the command outputs of the subscriber unit a.

The device allows you to connect to the digital computers different. the functional purpose of the objects: printing devices, magnetic tape drives, etc. 2. ;

The drawback of the device is that the existing hardware and software controls for correcting information do not allow for the correct management of objects (subscribers) if one of the address bus lines fails. ... Therefore, the object, in whatever state it may be, loses control from PVM. Since the failure of the address line leads to the selection of commands and operands from random memory areas, the digital computer begins to randomly wander around Hpo rpai-iMB and the possibility of issuing incorrect effects to the object is not excluded, which may be good for its accident.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that the device for interfacing subscribers with a digital computer containing two matching blocks, each of which is made as a group of voltage dividers, and a group of communication blocks with a subscriber, each of which is made as a comparison circuit, register shift, decoder, two delay elements and two elements NOT, with each input-output groups of address, information and control inputs. the device outputs are connected to the output of the corresponding voltage divider. each matching unit, the outputs of the first and second delay elements of the communication unit with the subscriber are connected respectively to the inputs of the first and second elements of the HE unit —the connection with the subscriber, the inputs of the first and the outputs of the second elements of the HE blocks the communication with the subscriber is connected to the group of control inputs-outputs of the device, the first group of inputs of the comparison circuit of the communication block with the subscriber is connected to the angle of the address of the communication block with the subscriber, the inverse output of the circuit is compared and the communication unit with the subscriber is connected to the first input of the NLI-NOT element of the communication unit with the subscriber, the outputs of the decoder of the communication unit with the subscriber are | Utc corresponding to the group of command outputs of the device, the emergency control unit, address group, information group {ionic and the group of control inputs-outputs of which are connected respectively to the group of address, information, and control inputs-outputs of the device, and four major, element,., element AND, element OR, trigger, are inserted into each communication unit with the subscriber The pulse pulse and the threshold node, the first, second fault inputs of the shift register and the first input of the element AND of the communication units with the subscriber are connected to the corresponding input-output of the group of control inputs-outputs of the device, the inputs of the threshold node and the majority elements of the communication unit are connected to the subscriber with a group of address inputs and outputs of the device, the outputs of the threshold node and the output of the first major element of the communication unit with the subscriber are connected respectively to the second and third inputs of the element OR NOT the communication unit with the subscriber, output the element OR of the communication unit with the subscriber is connected to the information input of the shift register of the communication unit with the subscriber; the input of the first delay element of the communication unit with absent is connected to the subscriber via the pulse generator of the communication unit with the subscriber. - the input element AND the communication unit with the subscriber, the output element. And the communication unit with the subscriber is connected to the trigger reset input and the third reset input of the shift register of the communication unit with the subscriber, the output of the first 3-element support of the communication unit with the subscriber with the synchronous input of the shift register of the communication unit with the subscriber, the first output of the shift register of the communication unit with the subscriber is connected to the C input of the trigger of the communication unit with the subscriber, the second output of the shift register of the communication unit with the subscriber is connected to the first input of the OR element and to the control the input of the blister decoder an eye communication with the subscriber, the output of the trigger of the communication unit with the subscriber is connected to the second input of the OR element,. the output of which is connected to the input of the second delay element of the communication unit with the subscriber, the output of the majority element / a of the communication unit with the subscriber, besides the output of the first major element, is connected to the corresponding information1-1-1 input of the decoder and the corresponding input of the second group of circuit inputs Comparison of blockages. by the object, the D-input trigger of the communication unit with the subscriber is connected to the level of the positive antenna, the emergency control unit 1) contains a permanent memory. three groups of elements NOT, three elements OR-NOT, trigger, threshold node, four major elements, two elements H, two elements NOT, two delay elements, display node, element NAND, with outputs of the first group of elements NOT. and inputs the threshold node, the entrances of the majority elements are connected to the hell group, the national inputs-outputs of the block, the outputs of the majority elements, the output of the threshold node, the output of the first delay element through the first OR-H element are connected to the C input of the trigger, the direct output of which is connected to the node input indications and informs the first input of the first group of elements NOT the inverted output of the trigger is connected to the first input of the second element, the output of the NAND element, the second input of the second element OR NOT the information input of the first and control input of the second delay element, reset inputs of the permanent memory and trigger connected to a group of control inputs / outputs of the block f, the output of the second major element is NOT connected to the first input of the first element AND, the second input of which is connected to the first indicative output of the permanent memory, to the first the input of the third element OR NOT, with the information input of the second group of elements NOT, the output of the first element is connected to the input enable input of the permanent memory, the third input of the second element OR NOT is connected to the output of the first delay element, the output of the second element OR NOT is connected to the information input of the second delay element and with the synchronous input of the permanent memory, the first, second and third outputs of the second delay element are connected respectively to the permission input of the issuing memory, with the control input of the second and with the first The second input of the element is NOT the group of elements NOT, the second is indicative, the output of the permanent memory is connected to the second input of the third element OR NOT through the second element NOT to the second input of the element AND NONE, the output of the third element OR NOT and the second YOU The input of the second delay element through the second element I is connected to the control input of the third group of elements NOT, the outputs of which and the outputs of the second GR17PY elements are NOT connected to the group of information inputs-outputs of the block, the information output of the permanent memory is connected to the information input of the third g The groups of elements NOT and with the address input of the constant to the control input of the first group of elements NOT and the 0 input of the trigger are connected to the level of positive potential.

FIG. 1 shows the proposed device; in fig. 2 - matching unit; FIGS. 3 shows a communication unit With a subscriber; in fig. 4 - emergency control unit; in fig. 5 pulse shaper; in FIG. b second delay element; in fig. 7th threshold node ...

The device contains matching 6LO.KI 1, a group of communication units 2 with a subscriber, emergency control unit 3, trunk 4 containing a group of connections connected by address input output 5, information input output 6, control input output 7, command outputs 8, group -.9 outputs for interaction with subscribers.

The matching block contains resistors .10 ц 11, forming resistor dividers. Items 12 and 13 denote the positive pole of the voltage source and the potential of the earth, respectively.

The communication unit with the subscriber contains a circuit of 14 comparisons, a decoder 15, an element OR NOT 16 ,. shift register 17, delay elements 18 and 19, elements NOT 20 and 21, first control input 22, control output 23, trigger 24, element OR 25, element AND 26, pulse shaper 27, threshold node 28, majority elements 29 -32, the inputs 33 of the threshold node, bits 34-36 of the shift register, the second control input 37, the address dialing node 38. The emergency control unit 3 contains a permanent memory 39, including the address register 40, the drive 41 and the data register .42, three groups of 43-45 NOT elements, trigger 46, threshold node 47, four major elements 48-51, three element-. 52-54, AND elements 55 and 56, AND-HE element 57, HE elements 58 and 59, delay elements 60 and 61, and display element 62, including a series-connected HE element 63, a LED 64 and a limiting resistor 6 connected to positive field su 66 source of food. In addition, the emergency control unit contains an input 67, a read tag, information input 68 and outputs.-69-7 of the second delay element, bits 72 and 73, and a group of 74 fixed memory bits. The pulse shaper can be executed in the form of a trigger, formed by AND-HE elements 75 and 76 and H-NE 77 element. The second delay element can be made in the form of the set of elements AND 78 and the element HE 79. The threshold node can be made in the form the elements of the OR 80 and the element AND 81. The matching blocks 1 perform two functions: provide no reflections from the physical ends of the cable lines of the trunk 4, for which the ohmic resistance of a parallel pair of resistors 10 and 11 is chosen equal to the wave, the new resistance of the cable and the echivayut maintaining relatively high positive potentials {napr.imer, 3, 5B) on the line 4 to the passive state. The active signals on the trunk lines are low potentials (e.g., 0.5 V) generated by transmission elements with open collector type outputs. If none of the transmitters connected to a certain line of highway 4 is switched on, then a high potential is maintained on this line {3, 5 V, if one transmitter is turned on, then a low potential is maintained on the line (0.5 V). Thus, each line of highway 4 performs the function of a wired OR with respect to the signal presented, low potentials B of 1 and 1 devices, built on the principle of a common highway, one of the narrowest points from the point of view of reliability is the highway itself. Indeed, the failure of any element (cable receiver, transmitter, detachable connection, etc.), leading, for example, to the appearance of a constant potential on just one line of the address bus, leads to a loss of device performance. In this case, the command and word information selected from the memory does not correspond to that prescribed by the program, the operation of the digital computer has the character of random walk. Objects connected to a digital computer lose control, or receive incorrect control, which can lead to a crash. Therefore, to avoid accidental situations in the event of a line failure, at least rude but proper control should be provided, which guarantees the safe completion of the controlled process. This problem is solved only with respect to failures of one or, under certain conditions, several lines of the address bus. The principle of the device is as follows. If the address bus is healthy, the digital computer, executed the work program, exchanges information with subscribers. The exchange is that one of the registers is defined. the subscriber either provides .information to the digital computer via the data bus, or receives information from this bus. The register is accessed in two stages: at the first stage, the digital computer accesses a certain address to which the required subscriber is located, at the second stage, the digital computer sets the address defining one of the subscriber registers. Address selection is made in such a way that the code distance between any subscriber address and any other address used in the system is equal to or greater than three. When this condition is fulfilled, as is known, it is possible to correct errors, at least single. In other words, addresses related to peripheral devices must be so distinguishable from each other and other addresses that distortion of any bit will nevertheless make it uniquely identical. to appropriate the corresponding object. When a failure of the address bus is detected, the DVR turns to a specific address protected from error (as described), as a result of which a new source of commands and data (emergency control) is connected to the data bus instead of work if there is a constant error in the address bus. The emergency control unit transmits the digging of the digital computer to the zero cell and at the same time fixes in one state the higher bits of the address bus. This leads to the fact that, from the point of view of a digital computer, selection of command and numerical information leads from regular memory cells (connected to a failed trunk, whose addresses do not exceed a relatively small amount. In fact, due to deliberate distortion address information, the CVM nporpaf-tMHyio digital computer and the numeric one is not from the initial memory area, but from the emergency control unit that is not sensitive to address errors. The emergency control unit ensures that the digital computer does not go beyond the limits of the specified zone, generating, if necessary, an unconditional control transfer command to the zero cell. During the execution of the program, xpaHHN.jH in the emergency control unit, branching may occur according to the results of the polling of subscriber registers. For alternative errors, alternative conditional jump addresses are selected such that the code distance between them is at least three, In this case, an accurate determination of the result of the operation of the conditional transition operation in the presence of a failure in the address bus is guaranteed. Thus, despite the rejection of the address bus line, the digital computer receives the correct command and numeric information. The use of secure addresses ensures proper processing of subscriber registers and the correct execution of conditional control transfer operations. These properties are sufficient for the implementation of arbitrary algorithms for software-controlled interaction with objects with an appropriate amount of memory of the emergency control unit. The device works as follows. The device is brought to its initial state when a low potential is applied to the input 37 (, Figs. 3 and 4). This potential is formed, for example, when a button is pressed on the digital computer control panel, either automatically after power is turned on, or under program control, etc. The zero signal passes through the element AND 26 and resets the trigger 24 and the bit 3 of the shift register 17. The bits 34 and 35 of the register 17 are also reset by a signal from the input .37. The decoder 15 is locked with zero signal / output signal of bit 36. register 17, a passive unit is formed at output 23 by connecting corresponding resistor dividers 10-11 located in blocks 1. Passive units are also supported on address bus 5, which corresponds to the LLC OOD code . The tracking address signal at input 22. is absent, i.e. corresponds to the passive unit. The reset signal from the input 37 brings the register 40 and the data memory register 42 to 39 to zero, as well as the trigger 46. The LED 64 of the display element 62 is turned off, the block 3 is logically disconnected from the trunk 4. After a time sufficient for translating the indicated elements the memory is reset, the reset signal is removed, i.e. at the input 37 is set-. a passive unit is cast. The subscriber register is addressed in two stages. At the first stage, the digital computer generates on the address bus 5 the address of one of the seven communication units with the subscriber: A 177NNN. The component NNN of this code determines the number of the communication unit with the subscriber according to the table. 000 007 070 077 700 707 770 If, for example, at the outputs of node 38 of the address set of some block 2 of communication with the subscriber the code is 4d 1002, access to this block of digital computer must place a code on the address bus. A 177077, and at input 22 - low potential signal tracking address. The leading edge of this signal (transition from high potential to low) confirms that the address code installed on bus 5. The code 177077 is transmitted to the inputs of the threshold node 28 and the major elementary potentials — active zeros, and to the inputs of the majority element 30 - in the form of high potentials of the passive units. Logic zeros are formed at the outputs of node 28 and majority elements 28, 29-31, and 32, and logical one at the output of majority element 30.

The codes on both soils of the inputs of the comparison circuit 14 are the same, so a logical zero is formed at its output, and a logical unit is formed at the output of the ILINE 16 element. By the end of the transient processes at the output of the ILPNE 16 element, the tracking address signal from the input 22 passes to the output of the delay element 18, passes through the NOT 20 element, and putting the front edge shifts the information in the shift register 17. A single signal from the output of the element OR NOT 16 is recorded in bit 34, pr1 of rank 35 and 36 remains in the zero state. The positive edge of the signal from the output of bit 34 causes the trigger 24 to be set to one, with the result that at the output of the element

OR 25, a logical unit is formed, which, after the time determined by the delay of delay element 19, sends an open collector to the input element HE 21. The operation of the HE element 21 causes the response signal to be output to the digital computer (Register-Memory command) out: 23 in the form of low potential.

Having received this signal, the digital computer removes the low potential from the input 22 of the address tracking, and from the bus 5 - the address code. At the same time, at the falling edge of the signal at input 22 (transition from low potential to high) at the output of pulse generator 27, a short-term logical zero signal is produced, which, passing through element 26, resets trigger 24, in which the element 21 is closed and the response signal from BELCOAD 23 is also removed, trunk 4 is freed and ready for the next exchange.

After executing this command, the digital computer turns into the memory for the next one. In this case, the address of the command does not cause the operation of the control circuit 14, since the addresses of the peripheral devices. The functions, as noted, differ from the command addresses in at least three bits. As a result, by the time of arrival of a positive signal front at the synchronization input of register 17 ,. on the output of the element OR NOT 16, a logical zero signal is generated. Therefore, as a result of the information shift, in register 17 the code 010 is set, the response

the signal is not generated by block 2, just as the command vibra is produced, but not its execution.

The selected command instructs the machine to read by or write to one of the addresses.

And 170MMMQ,

where the component MMM determines the address of one of the eight registers of the subscriber.

By the time this address is set on bus 5 and the transients in decoder 15 terminate, the signal from the output of the NOT element 20 causes the logical unit to advance from bit 35 to bit 36 of the register 17. This signal opens the decoder 15 output stage and outputs to one of the outputs 8 signal to access one of eight subscriber registers (not shown).

The information is either received from the bus 6 into this register, or is outputted from it to this bus depending on the value of the control signal at input 67 (line Read / write of the control bus 7. The response signal about the end of the operation goes to the digital computer at output 23 output bit 36 register 17 shift.

When receiving this response

 Signal DVR removes signals from the bus

5 and from input 22 of block 2. Next, the pulse shaper 27 is triggered, the reset pulse passes through AND 26 and resets bit 36 (bits 34 and 35 have already been reset). The decoder, 15 is closed, the response signal from output 23 is removed. At this elementary exchange procedure

information with the subscriber ends.

Threshold node 28 has a threshold of two. Therefore, at its output, a logical zero is supported only in the case when inputs 33 (the upper bits of the addressj hold the code including three or four single bits (recall that in the address bus 5, the single bits are represented by low potentials). This is a property of the threshold node 28 allows you to correct false type errors (false high potential) in the group of inputs 33 when referring to block 2. Similarly, a single error of any type can be present at the inputs of any major element 29-32. For example, aza address bus 5 177 077 instead of the code on the input unit 2 can do code 073 456 (one error at the inputs of the threshold unit 28 and the majority of each element 29-32, only 5 mismatch error) / that does not lead to the wrong choice nuzh -5ogo subscriber.

The emergency control unit 3 for utility line 4 and further causes the machine to perform orpaHHieti.Hfcie (but perhaps quite complex) object control functions only, in that case, if at some point in time for 1iin 5 addresses from the side of the digital computer code 177777 with a corresponding signal tracking address at input 22. This code is generated by the machine when it is resetting the address bus 5. The failure of address bus 5 may be obstructed by one of the well-known methods, pag; p} lp mentioned by the periodic method main line inspections Uza :: between. exchange ...

 pals: iiiHHe 5 addresses 177777 (or more than one position in the odes of the threshold node 47 and each of the major elements) at the outputs of the threshold node 47 and the majority; the first 48-51 elements form logical zeros that are prepared for or-NOT 52. When receiving this element a delayed element at the input (VOL 60 delays of the signal: ee1; and address, the output of the element I.I1-NOT 52 is formed and a positive signal is generated that is reverted to 46. how to enter information

About trigger POSTED

Iiji logistic unit. Sigya: l from a single arm trigger. 46 includes the display element 62 Current from the positive pole 66 The power source flows through the limiting resistor 65 and the LED 64 into the open collector of the HE element 63. The LED 64 signals that the system includes a digital computer and controlled objects, went into emergency control mode, in which the intelligence of the machine (defined by software o6ecne.4eHHeivi, xpaHHivK iM in a regular mode, m so-called) is largely lost in the amount of fixed memory. 39 emergency control unit 3.

A single signal from the output of the trigger 46 is also fed to the inputs of a group of elements HE 43, to the control input of which a work enable signal from the positive pole of the power supply is constantly supplied. As a result, low potentials (code llll-) are set on the four lines of the higher-order address bits, which are further delayed until the trigger is reset. 46 signal input 37. General reset. This signal as noted

previously, for example, may be initiated by the operator from the console after making the appropriate decision.

The zero signal from the output of the zero arm of the trigger 46 continuously permits the operation of the element OR NOT 53, the operation of this element, i.e. the formation of a positive front of the signal at its output occurs when there is a delayed signal of the address tracking and control signal Read / write {low potential when reading at input 67.

The positive edge of the signal at the output of the OR-NOT 53 element arrives at the exit 68 of the delay element 61 and at the synchronization input 40 register register memory address 39. This front, B, depending on the signal at the output of the element 55, causes either an increase per unit of the lower bit of the old contents of the register 40 of the address, or the entry in the register 40 of the address of the new information from the outputs of the register 42 of the data of the permanent memory 39. The first condition is satisfied when the signal at the output of the element K 55 is zero, the second at the single signal at this output In any of the two indicated cases, from the accumulator 41 constant naf-M.Tn 39 a certain word is extracted with a width exceeding by two bits the width of the data bus 4 of the bus 4.

K-moment of the establishment of new information on the inputs of the register of 42 data on its sync input. a positive edge of the signal is output from the output 69 of the delay element 61, as a result of which the new information is remembered.

With zero information in bits 73 and 72, a group of bits 74 is produced through a group of 44 elements NOT in data storage. The output is carried out when a positive signal appears at the output 70 of the delay element 61, which triggers the And 56 element and trips the formation of the enable signal on the control input of the group 44 of the NOT elements. The work enable signal (logical unit) also enters from the output 70 of the element 61 of the delay 11 to the control input of the group 75 of the elements NOT. However, since logical inputs from the output of bit 73 are present at the inputs of this group, open collector outputs of group 45 do not affect the state of data bus 6. The information issued in this mode to the data bus 6 is intended for the digital computer and is regarded by it as a command, address or constant for calculations depending on the context of the program.

With all the information, a follow-up signal is generated confirming its truth, from output 71 the delay elements 61 are not output, 23 in the form of a low potential. In response to receiving this signal, the DVR removes the address from the busses 5 and the tracking signal from the address 22. The appearance of a high potential at the input 22 causes the delay element 61 to be reset and the OR-NOT 53 element to be locked. As a result, information is removed from the bus 6 data, the response signal from the emergency control unit 3 at output 22 corresponds to the absence of data (passive unit).

If during the execution of the emergency program, the machine performs a write operation, the element ILINE 53 does not work and the emergency control unit 3 does not interfere with the transfer of data from the digital computer to the corresponding subscriber.

If the DVR executes the command to read information from the subscriber's register, then the selection of a new word from the accumulator 41 is performed, however this word contains a unit in the control section of the prohibition ban. The signal from the output of bit 72 of register -42 passes through the OR-NOT 54 element, locks the element. And 56 and, after passing through the HE.59 element, locks the AND-NOT 57 element. As a result, the outputs of the emergency control unit 3 are logically isolated from Highways 4 and this block; This is done by executing a read command previously extracted from the read-only memory 39.

The branch according to the program, recorded in the permanent memory 39, occurs as follows.

In response to the request of the digital computer for the next command, the command code of the conditional branch along the previously considered chain of elements 22, 60, 53, 68, 40, 41, 74, 44 and 6 is retrieved from the permanent memory 39. The next call 1 {line 4 is performed with the Purpose of retrieving from the neighboring memory cell the address to which the control was transferred in case of fulfillment (or if j did not fulfill the condition specified in the previously extracted command.

The address of the conditional transition is extracted from the constant memory 39 by a fuzzy path, but it is accompanied by a unit in bit 73 of register 42. This unit locks the element il 56 through the element OR-NOT 54, the input element AND 55 and the inputs of the group 45 elements are NOT . As a result, the conditional jump address is not provided to the data bus 6, since the element group 44 is closed, and is transmitted only to the inputs of address register 40 for later use if the condition is met. At the same time, for

 an account of the operation of a group of 45 elements NOT, a code was issued to the data bus 6, containing three units out of sixteen, namely, code 000700d. In other words, when executing the emergency services maintenance of DVM objects, having encountered a conditional branch command anywhere, either progresses through the program in a natural order, or always proceeds to selecting a command from the 000700 cell, depending on whether the condition is satisfied. In reality, however, the addresses formed by the machine do not coincide with the addresses on the highway and, especially, with the addresses (esy, the command and numerical information from the memory 41 of the permanent memory 39 is retrieved.

As already noted, when working on the emergency control program, the digital computer executes commands selected from its point of view from the initial memory area, in this example, from the 00 + 77e area. Therefore, after issuing the address 000700 to the bus 6, the emergency control unit 3 awaits a response from I.IBM. If the address issued from the digital computer contains three or two (in case of an address line failure) units, i.e. three or two

If the potential at the inputs of the majority element 49 is low, then the condition being checked is fulfilled and the natural order of following the commands must be violated. Otherwise, the digital computer still operates in the initial area of the memory, and therefore the corresponding sequential order of selecting the commands of the fixed memory 39 must be ensured. Thus, depending on the response of the digital computer, the element 55 and in The address register 40 is either entered in the new content, or one is added to the old content.

Stored in the permanent memory 39 the subscriber management program is initiated when a failure is detected

the address bus line 5 and its structure can be built, for example, as follows: the first subscriber’s status register is checked (for this, a read is performed at the corresponding address protected from an error,

the state register contains information sufficient to make a decision about the need for certain actions on the controlled object, the read information is analyzed, on the basis of which a decision is made on whether it is necessary to influence the object; if necessary, the digital computer produces a controlling influence on the object, checks the state of the second subscriber, decides whether the impact is necessary on the object, if necessary, influences it, etc. After serving the last subscriber, the program reverts. to service first, etc. Thus, in the emergency control mode, the digital computer is capable of semi 7

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11 signals from the outside world, process them and exert the necessary effects on the controlled objects. The use of inventions makes it possible to increase the reliability of a known device by introducing means for implementing an emergency control mode, as if compensating for the effect of problems that occur in the address bus.

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