SU1037417A1 - Non-recursive low-frequency digital filter - Google Patents

Abstract

A NON-FLEXIBLE DIGITAL FREQUENCY FILTER containing an analog-to-digital converter, whose input is the filter input, a smart phone whose output is connected to the first input of the adder, a register, a coefficient memory block containing N cells, a synchronization unit, the first output of the KOTOi switch is connected to The control input of the digital-analog converter, the code of which is the output of the filter, is characterized by the fact that, in order to increase the action, the first, second and third switches, t − 1 (rt) N | H, are inserted into it. TOeyirfrp / 5rpj ,, Грбх Гвых - respectively, the limit input and output frequencies) of the registers, and the coefficient memory block contains In memory nodes in and across the cells each, with the output of the analog-digital converter connected to the first multiplier , the output of the adder is connected to the input of the first switch, i -th

Description

The invention relates to computing technology, in particular to digital filters, and is intended for digital processing of electrical signals in various areas of the national economy (geological development of minerals by electromagnetic or seismic methods, radiolocation, hydrodynamics, etc.).

Known non-recursive digital

low-pass filters with a linear phase characteristic, where the filtering effect is achieved by multiplying the members of the current sample of discrete samples of the input signal by weights fixed for each member of the sample and summing the products obtained. The length of the sample (Hf1g1vnov) determines the quality of the filtering (the slope of the cutoff, the level of the frequency response pulsations) and the cutoff frequency 1.

The closest in technical essence to the present invention is a non-recursive digital filter that contains a multiplier, the adder output is connected to the input of the accumulating register, and the input is connected in series with the BTOpbiM adder input and digital-analog converter, two memory blocks for storing samples of the input signal (digital delay lines) and weight coefficients with a total volume of 2 VI cells, synchronization unit G.

The purpose of the invention is to simplify the filter and increase the speed.

The goal is achieved by the fact that a non-recursive digital low-pass filter containing an analog-to-digital converter, whose input is a filter input, a multiplier whose output is connected to the first input of the adder is a register, a coefficient memory block containing N cells, a synchronization unit, the first the output of which is connected to the control input of the digital-to-analog converter, the output of which is the output of the filter, is used to enter the first, second, and third switches, 00 -1 (UP - N II. where y p g ,, I f, p g ,,, ,

tfpB irpBblX - respectively, the boundary input and output frequencies) of registers, and the coefficient memory block contains a pack of memory nodes across AND cells in each, the output of the analog-digital converter connected to the first input of the multiplier, the output sum Txjpa is connected to the input of the first switch, the i-th () whose output

connected to the input. th register, the output of which is connected to the i input of the second switch, the output of which is connected to the input of a digital-analog converter and the second input of the adder, the output of the i-th () memory node is connected to the input (i +1) of the f-th memory node The ti and i th inputs of the third switch, the output of which is connected to the second input of the multiplier, are the control inputs of the first, second, and third switches, respectively, connected to the second, third, and fourth outputs of the synchronization unit, the fifth output of which is connected to the control inputs ( tons of memory nodes.

The width of the output spectrum of the low-pass filter is always less than the width of the input signal. This makes it possible to obtain a gain proportional to the ratio of the upper boundary frequencies of the spectra of the input and output signals. TrPBX

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) t.

FIG. 1 shows the functionality of the proposed filter scheme; in fig. 2 - time diagrams of the filter.

The filter contains analog-to-digital converter 1, multiplier 2, adder 3, register registers 4, first switch 5, second switch 6, coefficient memory block, divided into I1 of memory nodes 7 and each in cells, digital-to-analog converter 8, third 9 switch unit 1O synchronization.

The filter works as follows.

Each sample of the input signal, the inputs from the output of the analogue digital converter 1, is multiplied in the multiplier 2 times by weights, fed alternately through the switch 9 from the outputs of the memory node 7. The switch with switch 9 switches switch 5 and switch 6, adding the products to the contents of the corresponding registers 4 in adder 3. The cycle ends with a cyclic shift of the weights to the right by one cell. In this case, the coefficients from the last cell of each node 7 go to the first cell of the neighboring node to the right, and from the last node to the first. Receiving information into a digital-to-analog converter 8 is performed only when the output of any node 7 is the coefficient CN

whereby the transfer of production information from the register 4 corresponding to this node, after which this register is reset.

The operation of the digital filter is explained in a time diagram, illustrated in FIG. 2. As an example, take a filter with the number of N 10O coefficients in the coefficient memory block divided into memory nodes of 5O coefficients per man (i.e.).

The a axis shows the readings. Y: on the per BOM input multiplier; b axis - weight

the coefficients of the first node on the second inlet multiplier; the b axis is the weight coefficients of the second node at the second input of the multiplier; d axis - receiving result

I add to first register 4; axis d is the result of the addition in the second

register 4; e axis - receiving information into a digital-to-analog converter. The technical and economic effect from the use of the proposed device is expressed in the fact that in the filter during each time interval T there must be performed tj-multiplication operations, addition and access to the memory block and one shift. Consequently

 T7TG - -1 s.

which ensures a performance gain of at least M times. For large values of N, the total volume of the memory block also appears, the number of cells with registers taken into account (.) I instead of 2N in a known filter. In addition, the amount of equipment used and power consumption are reduced.

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Claims (1)

(5,4) NON-RESOURCED DIGITAL DIGITAL FILTER, containing an analog-to-digital converter, the input of which is a filter input, a multiplier, the output of which is connected to the first input of the adder, a register, a coefficient memory block containing N cells, a synchronization block, the first output of which is connected to the control input of the digital-to-analog converter, the output of which is the output of the filter, characterized in that, in order to improve performance, the first, second and third switches are introduced into it, ™ -1 <fri = N | H. where ^ f _rpbx / £ _{rpt) WX} , ^ grvkhArvyh “respectively are the registers, egg input and output frequencies) of the registers, and the coefficient memory block contains Un nodes of memory in each of the cells, and the output of the analog-to-digital converter is connected to the first input of the multiplier, the adder output is connected to the input of the first switch, the ΐ —th (1 = 1, n>) output of which is connected to the input of the ϊ-th register, the output of which is connected to the 1st input of the second switch, the output of which is connected to the input ^{1 of the} digital-to-analog converter and about the second input of the adder, the 4th output. (1 = 3 ^ 1) the memory node is connected to the input of the (i + l) ^^ th memory node and the ϊ-th input of the third switch, the output of which is connected to the second input of the multiplier, the control inputs of the first, • second and third switches are connected respectively to the second, third, and fourth • outputs of the synchronization unit, the fifth output of which is connected to the control inputs of m memory nodes.