SU1034113A1 - Device for overcurrent protection - Google Patents

Description

The invention relates to a technique for the relay protection of electrical objects against overloads and short circuits. High-speed relays are known that compare the time from the moment a current passes through zero to the time it reaches the setpoint with the reference time in which logic elements are used. However, the devices are intrinsic due to the need to measure the time to reach the setpoint, as well as the inoperability when changing the frequency of the alternating current. The closest in technical essence to the present invention is a device for overcurrent protection comprising a current sensor, the output of which includes an overload relay with a potential-pulse input, made in the form of a parator, a magnetic storage pulse counter and a time relay with two outputs the pulse output of the overload relay is connected to the base of the magnetic pulse counter recording triode, the collector of which is connected to one collector with the output winding of this counter, the second output of which is connected to one The second output of this relay is connected through a diode and a resistor by a triode emitter of the type of the mentioned overload relay. The disadvantage of the device is insufficient performance. The purpose of the invention is to increase the response speed of protection. The goal is achieved by the fact that a device for overcurrent protection, containing a current sensor connected via a rectifier to the first input of a comparison element, a binary counter and an actuator, additionally contains a sinusoidal setpoint network frequency control unit consisting of an input pictransformer connected to the zero input of a binary counter, the outputs of the trigger through a non-linear converter, including therefore connected decoder, a memory element, the code converter-analogous connected to the second input of the comparing element, wherein the output of the most significant bit binary counter via an integrator and emy controlled frequency generator is connected to the input of the counter. counter 3, integrator 4, controlled frequency generator 5, decoder b, persistent memory 7, converter 8 code code, rectifier 9 comparing element 10, executive body 11 frequency multiplier 12, nonlinear converter 13. The device operates as follows. After every half-period of sinusoidal voltage, when it passes through zero, peak-transformer 2 generates a pulse that resets the value of counter 3 to zero. The input of the counter 3 receives the pulses of the controlled oscillator 5 frequency. If during half the period the number of pulses received at the input is less than the capacity of counter 3, then the output of the counter (its last trigger / is in the zero state and integrator 4 connected to the output of counter 3 gives a controlled voltage to the controlled generator 5 increases the pulse frequency; if the number of pulses fed to counter 3 is greater than its capacity, the last trigger of counter 3 is triggered and a voltage drop from integrator 4 is applied to the input of generator 5, reducing the frequency of the gene Ratio 5. Consequently, the frequency of the controlled oscillator 5 varies in such a way that the same number of pulses is placed in a half-period, regardless of the phase voltage frequency, and the pulse repetition period of the oscillator 5 is proportional to the period of the controlled sinusoidal voltage. 5 is equal to the product of the capacitance of the meter and the frequency of the monitored voltage. Thus, the peak transformer 2, the frequency counter 3, the integrator 4 to the controlled frequency generator 5 multiplies Spruce 12 frequency. The outputs of the triggers of the counter 3 are fed to the decoder 6, which is associated with a permanent storage device 7, where the values of the sinusoidal function are recorded in the order of increasing argument. The outputs of the persistent storage device 7 are connected via a code-analog converter 8 to the second input of the comparison element 10. The decoder b, the persistent memory 7 and the code analog converter 8 form a non-linear converter 13.

controlled by the frequency of the network, the short-circuit current setting, which during the period varies sinusoidally.

The controlled phase current through the rectifier 9 is fed to the second input of the comparison element 10, where it is compared with the reference current of the sinusoidal setpoint.

In the event of a short circuit, the phase current exceeds the sinusoidal current of the setpoint, which leads to

the appearance of the signal at the output of the comparison element 10 and the actuation of the executive body 11.

Improving the reliability of the relay function greatly depends on the rapid detection of deviations from the normal mode. The speed of the proposed device is limited from below only by the arrival time of the signal at its input.