SU1008733A1 - Binary number division device - Google Patents

Abstract

A DEVICE FOR DIVIDING BINARY NUMBERS, containing the dividend register, the divider register, the triple divider register, the private shift register and the first totalizer, and (i - I) is the input of the first group of inputs of the first totalizer connected to the i-th split of the divisible register (- / I). 1, ..., C; n, the width of the operands), the inputs of the second group of the adder-subtractor are connected respectively to the outputs of the register of the divider, the output of the sign of the register of the dividend is connected to the control with the input of the primary subtractor, inverse The sign breakdown of the first adder-subtractor is connected to the first input of a private shift register, characterized in that, in order to increase speed, it contains the second and third summers and reads, the switch and the analysis unit containing three OR elements and eight AND elements, and the inverse output of the sign bit of the register of the dividend is connected to the first inputs of the first, second, third and fourth lemma And, the direct output of the sign bit of the register of the dividend is connected to the first inputs of the fifth, sixth, seventh and of the seventh And elements, the direct output of the sign bit of the first adder-subtractor is connected to the second inputs of the second; four, the fifth and seventh elements of And; the inverse output of the sign bit of the first adder-subtractor is connected to the second inputs of the first, third, sixth and of the eighth And elements, the inverse output of the sign bit of the second adder-subtractor is connected to the third code of the first and nsnroro elements And, the inverse output of the sign bit of the third adder-subtractor is connected to the third inputs of the second and sixth elec cops And,. W, the output of the first and second, fifth, and sixth elements of And are connected respectively to the inputs from the first to the fourth first OR element, the output of which is connected to the second input of the private shift register, the outputs of the third and seventh And elements are connected respectively to the first and the second inputs of the second OR element, the output of which is connected to the first control input 00 of the switch, the outputs of the fourth and eighth 1 elements AND are connected respectively to the first and second inputs of the third OR element, the output of which is n with a second control input of the switch, {-th register output Delhi: direct coupled to (+2) -th inputs per- .; the output groups of the inputs of the second and third adders are chymtychtey, the control inputs of which are connected to the output of the sign bit of the register of the dividend, and the inputs of the second groups of the second and third adders in 1 readers are connected respectively to the outputs of the register tripled

Description

divider and register divider, the outputs of the second adder-viitatel connected respectively with the inputs of the first group of the switch, the outputs of the third

adder-subtractor is connected respectively to the inputs of the second group of switch, the switch outputs are connected respectively to the inputs of the register of the dividend.

The invention relates to a computing technique and can be used in arithmetic devices of digital calculators.

A device for dividing is known.

binary numbers containing the adder, the registers of the dividend, the divisor and the private and the control block iT.

A disadvantage of the known device is the low speed action due to the formation in each cycle of one digit private.

It is also known a device for dividing numbers, forming in each cycle K a digital private and containing registers of the dividend, divisor and private, multiplication unit, subtractor, encoder To private numbers, address register, memory block, groups of elements I Shch}. A disadvantage of this device is the low beat action due to the multi-cycle: the formation of a K-digit quotient bone. Closest to the proposed by the technical nature of the 5th device for dividing, containing registers

divisible, divisor and private, adder, find fator, elements OR, three groups of elements And the first group of inputs of the adder is connected soitvet-gvenno

with the outputs of the register divisible, the inputs of which are connected respectively to the outputs of the adder and the inputs of the register of the private, the outputs of which are connected to the first inputs of the decoder, the second. the inputs of which are connected to the inputs i of the device divider, the second group of input; Adders of the adder are connected respectively to the outputs of the register of the divider, the inputs of which are connected respectively to the signals of the elements OR, the inputs of which are connected to the outputs of the corresponding elements AND of the i and group, the first inputs of which are connected to the output of the decoder, the second inputs of the elements of AND and the group are connected respectively with inputs i (-fo multiple device divider (l).

In this device, the division operation without restoring the remainder is performed by a series of iterations and determining, at each iteration, the two next racks of the partial values of the residuals calculated by subtracting the multiple divisor from the multiple previous residue. The residue thus obtained is preserved until the next and-darion and, in this iteration, becomes a multiple of the pre-modifying residue — 4 by a shift of two digits to the left L3.

The disadvantage of this device is the low speed, due to the sequential determination of the residuals and the correction of the two bits of the private predicted in the iteration using a table descriptor.

The purpose of the invention is to increase the speed of the device.

The goal is achieved by the fact that the device for dividing binary numbers, containing the register of the dividend, the divider register, the triple divider register, the private shift register, and the first adder calculator, and ((1 1 st input of the first group of inputs of the first adder-subtractor connected to -t -th output of the register of the dividend (i 1, ..., P; h is the width of the operands), the inputs of the second group of the adder are connected respectively to the outputs of the register of the divider, the output of the sign bit of the register of the dividend is connected to the control input of the first sum Torah subtractor, the inverse output of the sign bit of the first totalizer is connected to the first input of the shift register) private, contains the second and third I summatka 5RYB (switch and analysis unit containing three elements OR and eight elements And the inverse output of the sign bit of the register divisible connected to the first input of the first, second, third and fourth elements AND ;, the direct output of the sign bit of the register of the dividend is connected to the first inputs of the fifth, sixth, seventh and eighth elements of AND, the direct output of the sign p The height of the first adder-subtractor is connected to the second inputs of the second, fourth, fifth and seventh elements AND, the inverse output of the sign bit of the first adder-subtractor is connected to the second inputs of the first, third, sixth and eighth elements of AND, the inverse output of the sign bit of the second adder - the subtractor is connected to the third outputs of the first and fifth elements And, the inverse output of the sign bit of the third adder is connected to the third inputs of the second and sixth elements And, the outputs of the first, second, f and w The AND elements are connected respectively to the first to fourth inputs of the first OR element, the output of which is connected to the second input of the private shift register; the outputs of the third and seventh AND elements are connected respectively to the first and second inputs of the second OR element, whose output is connected to the first OR element. the input of the switch, the outputs of the fourth and eighth elements AND are connected respectively to the first and second inputs of the third OR element, the output of which is connected to the second control input of the switch, 4th output the register is divisible and connected to () the inputs of the first groups of inputs of the second and third subtractive rummators, the control inputs of which are connected to the sign bit of the register being divisible, and the inputs of the second groups of the second and third adders connected respectively to the outputs of the triple divisor register and register divider, the outputs of the second adder-subtractor are connected respectively to the inputs of the first group of switch, the outputs of the third end of the adder-reader are connected respectively to the inputs of the second group of switch, The switch moves are connected respectively to the inputs of the register of the dividend. 4 g. 1 shows a diagram of the device for dividing binary numbers; FIG. 2 is a block diagram analysis. The device for dividing the binary numbers contains the first, second and third adders-detectors 1-3, analysis block 4, switch 5, divisible register 6, divider register 7, private shift register 8 and tripled divider register 9. Block 4 analogy contains elements AND 1O-17, elements OR 18-2O. 1,334 A device for dividing binary bits works as follows. We denote the binary P-disjoint divisible..A, the binary P-decomposable normalized divisor & , i is the bit of atst, determined by the sign (ci -t-l) of the th residue Rj. , WITH . The rank of the quotient C, f and the remainder sign (5n () are related by the following logical dependency: C - (3HR- ,,). (О The positive sign of the remainder is coded with zero, and negative - by one When dividing without restoring the remainder; the next the remainder R is calculated from the previous residue k on form 1 iulam Ri, with (2) iR at. О) For one iteration, one determines the os-gato R and two variants of the next (1 / + 2) residue. if then M2R ,, - 6-4R, 3B, if. 0 then; -2R. 8. ГЯ + - - In case (3), if it is 4R, fB, if R- |, then XT) Apply (1) to the sign size of residuals and taking into account the conditions for choosing one of the nI of the remainder (i + 2) -. - from formulas (2) - (7). ,), Ct (3HR4) A (3HR.V; j3h (R-.iv v (SHR4) A (3HR, A (, “(3HR) AA,) l ISHR- - V (3 and R |) l ( HR) A ./: To determine the next pair of times a series of quotients for the original residue R, take one of the warped (l t-2) -ro residues, namely: when the significant bits of RN and Za are known, the remainder is 5, 1003 in the remaining cases x, - R, 42 Denote the first condition Γ and the second П, (ZnK) A (ZnK ,, M) l (z1Tk7;), n (5HR) A (iTR-; yy (3TR; ) A (3HR,). First, prepare the division operation: check whether the overflow of the discharge grid is not (R A - 3 7 O) and calculate the value of the three-time divisor (), which is entered into the register 9. These preliminary results can be carried out on adders 1 and 3. Then the next steps are performed to the division steps, ij In each step (iteration) two next bits of the particular C and C are determined. All adders in case (2) with a positive balance R They turn into subtraction mode, and in case of (3) 20 with R; O, they add to addition mode. At the outputs of adders 1. - 3, codes of the signs of residuals are formed (ii and. respectively. Inversion of the character 5 336 th bit of the current balance Zn enters the output register 8 as the first of two bits of the private C,. The second bit of the quotient is determined by an analysis unit 4 constructed in accordance with formula (9). During the transition to the next step, the accumulated quotient bits in the register are shifted and the true value of the remainder from the outputs of adders-subtractors 2 and 3 is transmitted through the switch 5 in the analysis block 4, in accordance with formulas (10) and (eleven). The division operation ends when in register 8 privately accumulates. Private bits. The result of the operation is formed in tt / 2 steps. Thus, the proposed device for dividing binary numbers has a speed of approximately two times greater than the device prototype.

i / .2

Claims (1)

A device for dividing binary numbers, containing a dividend register, a divisor register, a triple divisor register, a shift register of a private and a first adder, and the (ί +1) -th input of the first group of inputs of the first adder is connected to the <-th output of the dividend register (Л = 1 , ..., η; fl operand bits), the inputs of the second group of the adder-subtractor are connected respectively to the outputs of the register of the divider, the output of the sign discharge of the register of the dividend is connected to the control input of the first adder-subtractor, the inverse output of characters of the first discharge of the first adder-subtractor is connected to the first input of the shift register of the private one, characterized in that, in order to increase the speed, one hundred contains the second and third adders, the subtractor, the switch and the analysis unit containing three elements OR eight elements AND, and the inverse output of the sign discharge · The dividend register is connected to the first inputs of the first, second, third and fourth elements AND, the direct output of the sign bit of the dividend register is connected to the first inputs of the fifth, sixth, seventh and eighth element s, the direct output of the sign discharge of the first adder-subtractor is connected to the second inputs of the second, fourth, fifth and seventh elements And, the inverse output of the sign discharge of the first adder-subtractor is connected to the second inputs of the first, third, sixth and eighth elements And, the inverse output of the sign the discharge of the second adder-subtractor is connected to the third outputs of the first and fifth elements And, the inverse output of the sign discharge of the third adder-subtractor is connected to the third inputs of the second and sixth elements And,. The outputs of the first and second, fifth and sixth AND elements are connected respectively to the inputs from the first to the fourth first OR element, the output of which is connected to the second input of the shift register of the private, the outputs of the third and seventh elements AND are connected respectively to the first and second inputs of the second OR element, the output of which is connected to the first control input of the switch, the outputs of the fourth and eighth elements AND are connected respectively to the first and second inputs of the third OR element, the output of which is soy! Din with the second control input of the switch, (the 1st output of the dividend register is connected to the (1 + 2) -th inputs of the first: output groups of the inputs of the second and third adders-subtracters, the control inputs of which are connected to the output of the sign discharge of the dividend register, and the inputs of the second the groups of the second and third ί adders-in ^ readers are connected respectively to the outputs of the triple divider register and the divider register, the outputs of the second adder-subtractor are connected respectively to the inputs of the first switch group, the outputs of the third adder-subtractor connected respectively to the inputs of the second group of the switch, the outputs of the switch are connected respectively to the inputs of the register divisible.