SU1001160A1 - Device for forming symbols on crt screen - Google Patents

Description

The invention relates to computer technology and can be used in the design of devices for forming signs on the screen of a cathode ray tube (CRT).

A device for resizing characters on a CRT screen is known, comprising a memory unit, a register, a character generator, and sweep generators [1].

Closest to the proposed technical essence is a device for displaying information containing a memory unit, a register, a functional voltage generator, a code-time converter, a pulse generator, a backlight unit, a counter, etc. [2].

The main disadvantage of the known devices is their narrow scope due to the lack of the ability to change the size of the character in the case of using the functional method of forming characters /

The purpose of the invention is the expansion of the scope of the device due to the possibility of forming characters of various sizes.

This goal is achieved by the fact that the device for forming symbols on the screen of a CRT containing the block of 2 AND-OR elements, the first input of which is the input of the symbol code of the device, the second input is connected to the output of the memory unit, the third input is with the first output of the synchronizer, output - with the first input of the counter, the second input of which; connected to the second output of the synchronizer, the output to one of the inputs of the memory block, the third, fourth and fifth outputs of the synchronizer are connected to the other input of the memory block, one of the inputs of the code-time converter and the scan generator, respectively, and the sixth output is connected to one of the generator inputs pulses ·, the second input of the code-time converter is the first output of the device, the first input of the synchronizer is connected to the output of the pulse generator, the second to the third input of the counter, the output of the code-time converter ^ and one of the input rows of the first register and another input coupled to a third input of the synchronizer and the output of the storage unit, the first and second outputs of the first register are connected to the other input of the sweep generator and the input illumination unit, the other input of

1.001.1 60 the pulse generator is the synchronization input of the device, a second register and an adder are introduced, the first input of which is connected to the output of the second register, the second input is with the output of the memory block, the output of the total is 5 times connected to the third input of the code-time converter, one from the inputs of the second register is connected to the first output of the synchronizer, the other input of which is the information input of the device.

In FIG. 1 shows a structural diagram of the proposed device; in FIG. 2 is a block diagram of a block of AND-OR elements 2; in FIG. 3 - structure. synchronizer circuit. The device contains a pulse generator 1, synchronizer 2, block 3 elements 2 AND-OR, counter 4, memory block 5, converter 6 code-time, 20 first register 7, generator 8 sweep, block 9 backlight, second register 10 , adder 11, inputs and outputs 1218, logical elements 2 AND-OR 19.1-19 p, distributor 2 0 pulses, 25 driver 21 of the signal end of the character, driver 22 push-pull pulses, driver 23 of the access signal and trigger 24.

The pulse generator 1 is designed to form a burst of clock pulses, which is necessary for the synchronizer 2. The generator operates in start-stop mode from the beginning of the start pulse to the appearance of the 35 signal of the end of the symbol.

Synchronizer 2 is designed to generate synchronization and control signals between the device blocks. Its technical standardization can be carried out according to the structural scheme (Fig. 3).

Block 3 of elements 2 AND-OR is a circuit of information switch from two directions and is intended for switching the symbol code from the input 12 of the device or the code of the starting address of the symbol firmware from the output of the memory unit 5. The number of AND-OR elements 2 in block 3 corresponds to the capacity of the counter 4. Technically-50 block 3 can be implemented according to the block diagram (Fig. 2).

Address counter 4 is used to record the character code or the code of the starting address, as well as for sequentially changing the code of the starting address during the formation of · symbol contour vectors (the output number of counter 4 is the address for selecting information from memory unit 5) and It is leaked on 1330E7 microcircuits.

The memory unit 5 is intended for recording and storing the codes of the initial addresses of the symbol firmware 'and the codes of the symbol vector. Information in block 5 $$ memory is recorded in two arrays. Codes of the starting addresses of characters are written in the first array, and codes of their vectors and codes of the end of the character in the second array. Each input symbol code has its own starting address code, which is the address of the code of the first symbol vector.

Code-time converter 6 is intended for generating end-of-vector signals with time intervals proportional to the vector length code at the information input and the clock frequency of the pulses at the control input. Register 7 is intended 1 for recording and storing codes of symbol vectors at the time of their writing. The symbol sweep generator 8 serves to generate the symbol sweep voltages along the X and Y coordinates. The backlight unit 9 is used to generate the backlight signals of the symbol contour vectors necessary for its correct image on the CRT screen. The adder 11 performs the function of summing the codes of the lengths of the symbol vectors and the memory unit 5 with an external symbol size code.

Register 10 is designed to store a character size code at the time of writing.

The device operates as follows.

The symbol code from the input 12 of the device is supplied to the first information input of the block of 3 elements 2 AND-OR, and at the input 13, a start-stop generator 1 pulses is started by a synchronization pulse. From the output of the generator 1, a packet of pulses arrives at the first input of the synchronizer 2, which at the first output generates a signal for writing the input symbol code through the block 3 of the 2 AND-OR elements to the address counter 4, and at the second output, a signal for accessing the memory block 5. The number recorded in counter 4 is the address for selecting the code of the starting address of the symbol firmware in the memory unit 5. The selected start address code from memory unit 5 is stored in its output register (not shown).

After the start address code is sampled from the memory unit 5, the address counter 4 is reset to zero by a reset signal from the third output of the synchronizer 2, which at the first output generates a write enable signal for the initial code, the address through the block 3 of the 2 AND-OR elements to the counter 4, and on the second output - the second signal access to the block 5 of the memory.

The new code in counter 4 is the code address of the first symbol vector in memory unit 5. According to the starting address code and the second reference, the output of block 5 of memory generates a cfd of the first symbol vector having the following structure: 6 bits to control the sweep of the symbol vector along X and Y coordinates, 3 bits to set the vector length and 1 $ bit to generate backlight signals.

After the code of the first symbol vector is sampled from the memory unit 5 from the fourth output of the synchronizer 2, clock pulses begin to arrive at the sync input of the converter code-time, and the vector length code from the output of the adder 11 to its information input. If the symbol size code is input - 15 de 14 of the device is zero / then the output number of the adder 11 is equal to a three-digit vector length code recorded in the memory unit 5. If the code 'of symbol size is not equal to zero, then the output number of adder 11 is equal to the sum of two terms, i.e. the sum of codes from the output of memory unit 5 and from input 14 of the device.

At the initial moment of time, at the output of converter 6 code-time, a signal of the end of the vector (SLE) is generated, which corresponds to a zero-length vector. Based on this signal, a code of length and a character vector is entered into code-time converter b, and a scan and highlight code is entered into register 7.

At the same time, the code of the starting address at the output of the counter 4 is increased by one by one, the next signal to access the ³ memory block 5 and the enable signal of the generator 8 for scanning the symbol are generated,

From this point in time, the symbol sweep generator 8 generates a sweep voltage along the X and Y coordinates, 40 the code-time converter 6 sets the vector length, and the backlight unit 9 determines the backlight of the CRT beam.

After the formation of the first 45th symbol vector at the output of the converter ^: code-time 6, an SCR signal is generated with a time interval proportional to the frequency of clock pulses at the clock input and jq code for the length of the vector at the information input. This signal code the second symbol vector from the output of the memory unit 5, register 7 is entered, and from the output of the adder 11 into the converter 6 code is $$ time. In the future, the process of forming the second vector and all subsequent ones is similar to the first.

When forming the last vector of the symbol at the output of block 5 of the memory 60, an output number is formed containing zeros in all bits. Three digits of this number are fed to synchronizer 2, which, according to this code and the last hard currency, generates a signal of the end of the $ 5 symbol (SCS). Use this signal! The property is initialized. In addition, the end-of-character signal is sent to the device output 18 to call the next character code from an external control device * (not shown).

The required character size is provided by applying a size code to the input 14 of the device. At the same time, the code vector time converter receives codes of the lengths of the symbol vectors in increments specified by the External code. This leads to an increase in the amplitudes of the input voltages, the sweep of the symbol along the X and Y coordinates of the generator 8, and, consequently, to the size of the symbols on the CRT screen.

In the proposed device, the scan generator 8 is configured so that, in the absence of a code at input 14, the symbols on the CRT screen are of minimum size. By submitting a symbol size code, its required size is set within the maximum allowed for the selected CRT screen diameter and the density of information displayed on it ..

In practice, the size of the symbol is set by a three-digit code, which provides 8 gradations of its size and meets the requirements in most cases when displaying symbol information in various control objects.

Claims (2)

1. USSR author's certificate number 546914, cl. G 06 K 15/20, 1978. 2. USSR author's certificate No. 634322, cl. G 06 K 15/20, 1979 (prototype).