SG93856A1 - A selective & damage free cu cleaning process for pre-dep, post etch/cmp - Google Patents
A selective & damage free cu cleaning process for pre-dep, post etch/cmpInfo
- Publication number
- SG93856A1 SG93856A1 SG9906679A SG1999006679A SG93856A1 SG 93856 A1 SG93856 A1 SG 93856A1 SG 9906679 A SG9906679 A SG 9906679A SG 1999006679 A SG1999006679 A SG 1999006679A SG 93856 A1 SG93856 A1 SG 93856A1
- Authority
- SG
- Singapore
- Prior art keywords
- dep
- cmp
- selective
- cleaning process
- post etch
- Prior art date
Links
- 238000004140 cleaning Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Photovoltaic Devices (AREA)
- Micromachines (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US35687299A | 1999-07-19 | 1999-07-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG93856A1 true SG93856A1 (en) | 2003-01-21 |
Family
ID=23403325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG9906679A SG93856A1 (en) | 1999-07-19 | 1999-12-29 | A selective & damage free cu cleaning process for pre-dep, post etch/cmp |
Country Status (3)
Country | Link |
---|---|
US (1) | US20030196989A1 (en) |
JP (1) | JP2001038700A (en) |
SG (1) | SG93856A1 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6180524B1 (en) * | 1999-08-09 | 2001-01-30 | Gary W. Ferrell | Metal deposit process |
US7009281B2 (en) * | 2003-03-14 | 2006-03-07 | Lam Corporation | Small volume process chamber with hot inner surfaces |
US7217649B2 (en) * | 2003-03-14 | 2007-05-15 | Lam Research Corporation | System and method for stress free conductor removal |
US7232766B2 (en) * | 2003-03-14 | 2007-06-19 | Lam Research Corporation | System and method for surface reduction, passivation, corrosion prevention and activation of copper surface |
US7078344B2 (en) * | 2003-03-14 | 2006-07-18 | Lam Research Corporation | Stress free etch processing in combination with a dynamic liquid meniscus |
AT500259B1 (en) * | 2003-09-09 | 2007-08-15 | Austria Tech & System Tech | THIN-LAYER ASSEMBLY AND METHOD FOR PRODUCING SUCH A THIN-LAYER ASSEMBLY |
US8614151B2 (en) * | 2008-01-04 | 2013-12-24 | Micron Technology, Inc. | Method of etching a high aspect ratio contact |
KR102506217B1 (en) * | 2016-10-24 | 2023-03-06 | 동우 화인켐 주식회사 | Composition for removing acrylic resin |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4952275A (en) * | 1989-12-15 | 1990-08-28 | Microelectronics And Computer Technology Corporation | Copper etching solution and method |
US5780358A (en) * | 1996-04-08 | 1998-07-14 | Chartered Semiconductor Manufacturing Ltd. | Method for chemical-mechanical polish (CMP) planarizing of cooper containing conductor layers |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5891513A (en) * | 1996-01-16 | 1999-04-06 | Cornell Research Foundation | Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications |
US5970373A (en) * | 1996-05-10 | 1999-10-19 | Sharp Laboratories Of America, Inc. | Method for preventing oxidation in the formation of a via in an integrated circuit |
KR100215846B1 (en) * | 1996-05-16 | 1999-08-16 | 구본준 | Wiring Formation Method of Semiconductor Device |
US5855811A (en) * | 1996-10-03 | 1999-01-05 | Micron Technology, Inc. | Cleaning composition containing tetraalkylammonium salt and use thereof in semiconductor fabrication |
US5899738A (en) * | 1997-05-23 | 1999-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for making metal plugs in stacked vias for multilevel interconnections and contact openings while retaining the alignment marks without requiring extra masking steps |
US5904565A (en) * | 1997-07-17 | 1999-05-18 | Sharp Microelectronics Technology, Inc. | Low resistance contact between integrated circuit metal levels and method for same |
US6277733B1 (en) * | 1998-10-05 | 2001-08-21 | Texas Instruments Incorporated | Oxygen-free, dry plasma process for polymer removal |
-
1999
- 1999-12-29 SG SG9906679A patent/SG93856A1/en unknown
-
2000
- 2000-04-18 JP JP2000116901A patent/JP2001038700A/en active Pending
-
2003
- 2003-06-10 US US10/458,145 patent/US20030196989A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4952275A (en) * | 1989-12-15 | 1990-08-28 | Microelectronics And Computer Technology Corporation | Copper etching solution and method |
US5780358A (en) * | 1996-04-08 | 1998-07-14 | Chartered Semiconductor Manufacturing Ltd. | Method for chemical-mechanical polish (CMP) planarizing of cooper containing conductor layers |
Also Published As
Publication number | Publication date |
---|---|
JP2001038700A (en) | 2001-02-13 |
US20030196989A1 (en) | 2003-10-23 |
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