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SG11202109921QA - Process for transferring a useful layer to a carrier substrate - Google Patents

Process for transferring a useful layer to a carrier substrate

Info

Publication number
SG11202109921QA
SG11202109921QA SG11202109921QA SG11202109921QA SG 11202109921Q A SG11202109921Q A SG 11202109921QA SG 11202109921Q A SG11202109921Q A SG 11202109921QA SG 11202109921Q A SG11202109921Q A SG 11202109921QA
Authority
SG
Singapore
Prior art keywords
transferring
carrier substrate
useful layer
useful
layer
Prior art date
Application number
Inventor
Didier Landru
Oleg Kononchuk
Mohamed Nadia Ben
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202109921QA publication Critical patent/SG11202109921QA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043Making grooves, e.g. cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Macromolecular Compounds Obtained By Forming Nitrogen-Containing Linkages In General (AREA)
  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Wiring (AREA)
SG11202109921Q 2019-03-15 2020-02-26 Process for transferring a useful layer to a carrier substrate SG11202109921QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1902674A FR3093859B1 (en) 2019-03-15 2019-03-15 Method of transferring a useful layer onto a support substrate
PCT/FR2020/050369 WO2020188169A1 (en) 2019-03-15 2020-02-26 Method for transferring a useful layer to a carrier substrate

Publications (1)

Publication Number Publication Date
SG11202109921QA true SG11202109921QA (en) 2021-10-28

Family

ID=67384010

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202109921Q SG11202109921QA (en) 2019-03-15 2020-02-26 Process for transferring a useful layer to a carrier substrate

Country Status (9)

Country Link
US (1) US11876015B2 (en)
EP (1) EP3939078A1 (en)
JP (1) JP7500911B2 (en)
KR (1) KR20210134784A (en)
CN (1) CN113491004B (en)
FR (1) FR3093859B1 (en)
SG (1) SG11202109921QA (en)
TW (1) TWI824112B (en)
WO (1) WO2020188169A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3134229B1 (en) * 2022-04-01 2024-03-08 Commissariat Energie Atomique METHOD FOR TRANSFERRING A THIN LAYER TO A SUPPORT SUBSTRATE

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214399A (en) 2002-12-27 2004-07-29 Sumitomo Mitsubishi Silicon Corp Manufacturing method for semiconductor substrate and wafer peeling-heat treatment apparatus
FR2861497B1 (en) 2003-10-28 2006-02-10 Soitec Silicon On Insulator METHOD FOR CATASTROPHIC TRANSFER OF A FINE LAYER AFTER CO-IMPLANTATION
EP2293326A3 (en) 2004-06-10 2012-01-25 S.O.I.TEC Silicon on Insulator Technologies S.A. Method for manufacturing a SOI wafer
US7456080B2 (en) * 2005-12-19 2008-11-25 Corning Incorporated Semiconductor on glass insulator made using improved ion implantation process
FR2912259B1 (en) * 2007-02-01 2009-06-05 Soitec Silicon On Insulator PROCESS FOR PRODUCING A SUBSTRATE OF THE "SILICON ON INSULATION" TYPE
FR2938120B1 (en) * 2008-10-31 2011-04-08 Commissariat Energie Atomique PROCESS FOR FORMATION OF A MONOCRYSTALLINE LAYER IN THE MICROELECTRONIC DOMAIN
US8357974B2 (en) * 2010-06-30 2013-01-22 Corning Incorporated Semiconductor on glass substrate with stiffening layer and process of making the same
JP5703853B2 (en) 2011-03-04 2015-04-22 信越半導体株式会社 Manufacturing method of bonded wafer
JP2015516672A (en) * 2012-02-26 2015-06-11 ソレクセル、インコーポレイテッド System and method for laser splitting and equipment layer relocation
US9257339B2 (en) * 2012-05-04 2016-02-09 Silicon Genesis Corporation Techniques for forming optoelectronic devices
FR3020175B1 (en) * 2014-04-16 2016-05-13 Soitec Silicon On Insulator METHOD OF TRANSFERRING A USEFUL LAYER
JP6563360B2 (en) * 2016-04-05 2019-08-21 信越化学工業株式会社 Method for manufacturing composite wafer having oxide single crystal thin film

Also Published As

Publication number Publication date
TW202036784A (en) 2020-10-01
EP3939078A1 (en) 2022-01-19
FR3093859B1 (en) 2021-02-12
CN113491004A (en) 2021-10-08
JP2022527048A (en) 2022-05-30
CN113491004B (en) 2024-09-13
JP7500911B2 (en) 2024-06-18
FR3093859A1 (en) 2020-09-18
KR20210134784A (en) 2021-11-10
TWI824112B (en) 2023-12-01
US11876015B2 (en) 2024-01-16
US20220157650A1 (en) 2022-05-19
WO2020188169A1 (en) 2020-09-24

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