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SG11201806451VA - Method and system for forming memory fin patterns - Google Patents

Method and system for forming memory fin patterns

Info

Publication number
SG11201806451VA
SG11201806451VA SG11201806451VA SG11201806451VA SG11201806451VA SG 11201806451V A SG11201806451V A SG 11201806451VA SG 11201806451V A SG11201806451V A SG 11201806451VA SG 11201806451V A SG11201806451V A SG 11201806451VA SG 11201806451V A SG11201806451V A SG 11201806451VA
Authority
SG
Singapore
Prior art keywords
international
etch
ho1l
pct
cuts
Prior art date
Application number
SG11201806451VA
Inventor
Hoyoung Kang
Anton Devilliers
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of SG11201806451VA publication Critical patent/SG11201806451VA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P50/692—
    • H10P50/695—
    • H10P50/696—
    • H10P50/71—
    • H10P76/2041—
    • H10W20/087—
    • H10W20/089—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

WO 17 / 13 238 1 Al (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (10) International Publication Number (43) International Publication Date WO 2017/132381 Al 3 August 2017 (03.08.2017) WIPO I PCT 111111111111110111011111111111010111110111111110111111110111H 011111111111110111111 (51) International Patent Classification: HO1L 21/027 (2006.01) G03F 7/00 (2006.01) HO1L 21/768 (2006.01) HO1L 21/3213 (2006.01) (21) International Application Number: PCT/US2017/015136 (22) International Filing Date: 26 January 2017 (26.01.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/288,846 29 January 2016 (29.01.2016) US (71) Applicant: TOKYO ELECTRON LIMITED [JP/JP]; Akasaka Biz Tower, 3-1 Akasaka 5-chome, Minato-ku, Tokyo 107-6325 (JP). (71) Applicant (for JP only): TOKYO ELECTRON U.S. HOLDINGS, INC. [US/US]; 2400 Grove Boulevard, Aus- tin, Texas 78741 (US). (72) Inventor: KANG, Hoyoung; 200 Wilkins Ln., Guilder- land, New York 12303 (US). (74) Agent: MATHER, Joshua D.; Tokyo Electron U.S. Hold- ings, Inc., 2400 Grove Boulevard, Austin, Texas 78741 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: with international search report (Art. 21(3)) (54) Title: METHOD AND SYSTEM FOR FORMING MEMORY FIN PATTERNS (57) : Techniques disclosed herein, provide a method and fabrication structure for accurately increasing feature density for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A multiline layer is formed of three or more different materials that provide differing etch characteristics. Etch masks, including interwoven etch masks, are used to selectively etch cuts within selected, exposed materials. Structures can then be cut and formed. Forming structures and cuts can be recorded in a memorization layer, which can also be used as an etch mask.
SG11201806451VA 2016-01-29 2017-01-26 Method and system for forming memory fin patterns SG11201806451VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662288846P 2016-01-29 2016-01-29
PCT/US2017/015136 WO2017132381A1 (en) 2016-01-29 2017-01-26 Method and system for forming memory fin patterns

Publications (1)

Publication Number Publication Date
SG11201806451VA true SG11201806451VA (en) 2018-08-30

Family

ID=59387112

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201806451VA SG11201806451VA (en) 2016-01-29 2017-01-26 Method and system for forming memory fin patterns

Country Status (7)

Country Link
US (2) US10115726B2 (en)
JP (1) JP6715415B2 (en)
KR (1) KR102207120B1 (en)
CN (1) CN108701588B (en)
SG (1) SG11201806451VA (en)
TW (1) TWI633583B (en)
WO (1) WO2017132381A1 (en)

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US9991156B2 (en) 2016-06-03 2018-06-05 International Business Machines Corporation Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
US10388644B2 (en) 2016-11-29 2019-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing conductors and semiconductor device which includes conductors
CN109411337A (en) * 2017-08-16 2019-03-01 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
US10734238B2 (en) * 2017-11-21 2020-08-04 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for critical dimension control
US10566207B2 (en) * 2017-12-27 2020-02-18 Samsung Electronics Co., Ltd. Semiconductor manufacturing methods for patterning line patterns to have reduced length variation
US10439047B2 (en) * 2018-02-14 2019-10-08 Applied Materials, Inc. Methods for etch mask and fin structure formation
EP3618103A1 (en) * 2018-08-30 2020-03-04 IMEC vzw A patterning method
US20200090980A1 (en) * 2018-09-13 2020-03-19 Nanya Technology Corporation Method for preparing semiconductor structures
US10903082B2 (en) 2018-09-21 2021-01-26 Varian Semiconductor Equipment Associates, Inc. Spacer sculpting for forming semiconductor devices
US11024511B1 (en) 2020-04-21 2021-06-01 Winbond Electronics Corp. Patterning method
JP2022032500A (en) 2020-08-12 2022-02-25 キオクシア株式会社 Pattern formation method and template manufacturing method
CN114005736B (en) * 2021-09-29 2025-09-05 长江存储科技有限责任公司 Method for preparing a semiconductor structure
US12400859B2 (en) 2022-07-28 2025-08-26 International Business Machines Corporation Metal hard mask for precise tuning of mandrels
US12451354B2 (en) 2022-09-09 2025-10-21 Tokyo Electron Limited Double patterning method of patterning a substrate

Family Cites Families (18)

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KR100674970B1 (en) * 2005-04-21 2007-01-26 삼성전자주식회사 Fine pitch pattern formation method using double spacers
US7429536B2 (en) * 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7914971B2 (en) * 2005-08-12 2011-03-29 Semiconductor Energy Laboratory Co., Ltd. Light exposure mask and method for manufacturing semiconductor device using the same
JP4566862B2 (en) * 2005-08-25 2010-10-20 富士通株式会社 Resist pattern thickening material, resist pattern forming method, semiconductor device and manufacturing method thereof
US7759197B2 (en) * 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7323374B2 (en) * 2005-09-19 2008-01-29 International Business Machines Corporation Dense chevron finFET and method of manufacturing same
KR100932333B1 (en) * 2007-11-29 2009-12-16 주식회사 하이닉스반도체 Hard Mask Pattern of Semiconductor Device and Formation Method
KR101532012B1 (en) * 2008-12-24 2015-06-30 삼성전자주식회사 Semiconductor device and pattern forming method of semiconductor device
US7871873B2 (en) * 2009-03-27 2011-01-18 Global Foundries Inc. Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material
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US9240329B2 (en) * 2014-02-23 2016-01-19 Tokyo Electron Limited Method for multiplying pattern density by crossing multiple patterned layers
WO2016022518A1 (en) * 2014-08-08 2016-02-11 Applied Materials, Inc. Multi materials and selective removal enabled reverse tone process
US10020196B2 (en) * 2015-09-24 2018-07-10 Tokyo Electron Limited Methods of forming etch masks for sub-resolution substrate patterning
US9991156B2 (en) * 2016-06-03 2018-06-05 International Business Machines Corporation Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

Also Published As

Publication number Publication date
TW201737309A (en) 2017-10-16
US20190027481A1 (en) 2019-01-24
WO2017132381A1 (en) 2017-08-03
JP6715415B2 (en) 2020-07-01
CN108701588A (en) 2018-10-23
TWI633583B (en) 2018-08-21
CN108701588B (en) 2023-03-14
JP2019508889A (en) 2019-03-28
KR102207120B1 (en) 2021-01-22
KR20180100699A (en) 2018-09-11
US10115726B2 (en) 2018-10-30
US20170221902A1 (en) 2017-08-03

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