SG10201913373WA - High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency - Google Patents
High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiencyInfo
- Publication number
- SG10201913373WA SG10201913373WA SG10201913373WA SG10201913373WA SG10201913373WA SG 10201913373W A SG10201913373W A SG 10201913373WA SG 10201913373W A SG10201913373W A SG 10201913373WA SG 10201913373W A SG10201913373W A SG 10201913373WA SG 10201913373W A SG10201913373W A SG 10201913373WA
- Authority
- SG
- Singapore
- Prior art keywords
- charge trapping
- high resistivity
- insulator substrate
- trapping efficiency
- resistivity silicon
- Prior art date
Links
- 239000012212 insulator Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02516—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02579—P-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Chemical Vapour Deposition (AREA)
- Elimination Of Static Electricity (AREA)
- Inorganic Insulating Materials (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662412937P | 2016-10-26 | 2016-10-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201913373WA true SG10201913373WA (en) | 2020-03-30 |
Family
ID=60162290
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201903090SA SG11201903090SA (en) | 2016-10-26 | 2017-10-09 | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
SG10201913373WA SG10201913373WA (en) | 2016-10-26 | 2017-10-09 | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201903090SA SG11201903090SA (en) | 2016-10-26 | 2017-10-09 | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
Country Status (7)
Country | Link |
---|---|
US (4) | US10546771B2 (en) |
EP (4) | EP4456146A3 (en) |
JP (3) | JP6831911B2 (en) |
CN (2) | CN115763496A (en) |
SG (2) | SG11201903090SA (en) |
TW (3) | TWI774584B (en) |
WO (1) | WO2018080772A1 (en) |
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FR3066858B1 (en) * | 2017-05-23 | 2019-06-21 | Soitec | METHOD FOR MINIMIZING DISTORTION OF A SIGNAL IN A RADIO FREQUENCY CIRCUIT |
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US10468486B2 (en) * | 2017-10-30 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company Ltd. | SOI substrate, semiconductor device and method for manufacturing the same |
US10943813B2 (en) * | 2018-07-13 | 2021-03-09 | Globalwafers Co., Ltd. | Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability |
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-
2017
- 2017-10-09 SG SG11201903090SA patent/SG11201903090SA/en unknown
- 2017-10-09 SG SG10201913373WA patent/SG10201913373WA/en unknown
- 2017-10-09 WO PCT/US2017/055722 patent/WO2018080772A1/en unknown
- 2017-10-09 CN CN202211496480.6A patent/CN115763496A/en active Pending
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TWI721223B (en) | 2021-03-11 |
TW202205372A (en) | 2022-02-01 |
CN115763496A (en) | 2023-03-07 |
TW202117803A (en) | 2021-05-01 |
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EP4456146A3 (en) | 2025-04-30 |
EP3792965A1 (en) | 2021-03-17 |
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US20180114720A1 (en) | 2018-04-26 |
US20200126847A1 (en) | 2020-04-23 |
EP4057326A1 (en) | 2022-09-14 |
EP3533081A1 (en) | 2019-09-04 |
JP2021005720A (en) | 2021-01-14 |
US20210013093A1 (en) | 2021-01-14 |
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