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SG10201804989UA - Vertical Memory Device - Google Patents

Vertical Memory Device

Info

Publication number
SG10201804989UA
SG10201804989UA SG10201804989UA SG10201804989UA SG10201804989UA SG 10201804989U A SG10201804989U A SG 10201804989UA SG 10201804989U A SG10201804989U A SG 10201804989UA SG 10201804989U A SG10201804989U A SG 10201804989UA SG 10201804989U A SG10201804989U A SG 10201804989UA
Authority
SG
Singapore
Prior art keywords
memory device
vertical memory
channel layer
gate electrode
electrode layers
Prior art date
Application number
SG10201804989UA
Inventor
Hwan Lee Kyung
Seok Kim Yong
Hun Kim Tae
Taek Kim Byoung
Hee Lim Jun
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201804989UA publication Critical patent/SG10201804989UA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/697—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having trapping at multiple separated sites, e.g. multi-particles trapping sites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer. FIG. 1
SG10201804989UA 2017-07-13 2018-06-12 Vertical Memory Device SG10201804989UA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020170089171A KR102385568B1 (en) 2017-07-13 2017-07-13 Vertical-type memory device

Publications (1)

Publication Number Publication Date
SG10201804989UA true SG10201804989UA (en) 2019-02-27

Family

ID=65000740

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201804989UA SG10201804989UA (en) 2017-07-13 2018-06-12 Vertical Memory Device

Country Status (4)

Country Link
US (1) US10636808B2 (en)
KR (1) KR102385568B1 (en)
CN (1) CN109256390B (en)
SG (1) SG10201804989UA (en)

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US11758716B2 (en) * 2018-09-05 2023-09-12 Micron Technology, Inc. Electronic devices including vertical memory cells and related methods
US10991718B2 (en) * 2019-07-30 2021-04-27 Sandisk Technologies Llc Three-dimensional memory device containing a vertical semiconductor channel containing a connection strap and method of making the same
US10991705B2 (en) 2019-07-30 2021-04-27 Sandisk Technologies Llc Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same
US11024645B2 (en) 2019-07-30 2021-06-01 Sandisk Technologies Llc Three-dimensional memory device containing a silicon nitride ring in an opening in a memory film and method of making the same
US10991706B2 (en) * 2019-07-30 2021-04-27 Sandisk Technologies Llc Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same
US11069708B2 (en) * 2019-11-12 2021-07-20 Macronix International Co., Ltd. Memory device and method for manufacturing the same
US11355553B2 (en) 2019-12-05 2022-06-07 International Business Machines Corporation Resistive random access memory integrated under a vertical field effect transistor
WO2021208076A1 (en) * 2020-04-17 2021-10-21 Yangtze Memory Technologies Co., Ltd. Memory device
CN111710683A (en) * 2020-06-04 2020-09-25 长江存储科技有限责任公司 Three-dimensional memory and preparation method thereof
CN112687699B (en) * 2020-12-24 2023-12-26 长江存储科技有限责任公司 Three-dimensional memory and preparation method thereof
CN113013172B (en) * 2021-03-05 2022-01-25 长江存储科技有限责任公司 Three-dimensional memory and manufacturing method thereof

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US9536970B2 (en) 2010-03-26 2017-01-03 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory devices and methods of fabricating the same
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US8987805B2 (en) * 2012-08-27 2015-03-24 Samsung Electronics Co., Ltd. Vertical type semiconductor devices including oxidation target layers
US9076879B2 (en) * 2012-09-11 2015-07-07 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory device and method for fabricating the same
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Also Published As

Publication number Publication date
US10636808B2 (en) 2020-04-28
US20190019809A1 (en) 2019-01-17
KR20190007762A (en) 2019-01-23
CN109256390A (en) 2019-01-22
CN109256390B (en) 2024-04-16
KR102385568B1 (en) 2022-04-12

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