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SG10201803467SA - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
SG10201803467SA
SG10201803467SA SG10201803467SA SG10201803467SA SG10201803467SA SG 10201803467S A SG10201803467S A SG 10201803467SA SG 10201803467S A SG10201803467S A SG 10201803467SA SG 10201803467S A SG10201803467S A SG 10201803467SA SG 10201803467S A SG10201803467S A SG 10201803467SA
Authority
SG
Singapore
Prior art keywords
interlayer insulating
semiconductor device
etch stop
insulating layer
stop layer
Prior art date
Application number
SG10201803467SA
Inventor
Woo Kyung You
Eui Bok Lee
Jong Min Baek
Su Hyun Bark
Jang Ho Lee
Sang Hoon Ahn
Hyeok Sang Oh
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201803467SA publication Critical patent/SG10201803467SA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

of the Disclosure A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise. Fig. 2
SG10201803467SA 2017-08-02 2018-04-25 Semiconductor device SG10201803467SA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020170098008A KR102356754B1 (en) 2017-08-02 2017-08-02 Semiconductor device

Publications (1)

Publication Number Publication Date
SG10201803467SA true SG10201803467SA (en) 2019-03-28

Family

ID=65231762

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201803467SA SG10201803467SA (en) 2017-08-02 2018-04-25 Semiconductor device

Country Status (4)

Country Link
US (2) US10475739B2 (en)
KR (1) KR102356754B1 (en)
CN (1) CN109390273B (en)
SG (1) SG10201803467SA (en)

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KR102451171B1 (en) 2018-01-25 2022-10-06 삼성전자주식회사 Semiconductor device
US10468297B1 (en) * 2018-04-27 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Metal-based etch-stop layer
US11769692B2 (en) 2018-10-31 2023-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. High breakdown voltage inter-metal dielectric layer
KR102759920B1 (en) 2019-07-01 2025-02-04 삼성전자주식회사 Semiconductor device
KR102751330B1 (en) * 2019-07-03 2025-01-07 삼성전자주식회사 Integrated circuit device and method of manufacturing the same
KR102732300B1 (en) * 2019-07-17 2024-11-19 삼성전자주식회사 Semiconductor device and method for fabricating thereof
US10991618B2 (en) * 2019-09-03 2021-04-27 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of manufacture
KR102816111B1 (en) * 2020-05-07 2025-06-05 삼성전자주식회사 Semiconductor device
KR102766439B1 (en) * 2021-01-08 2025-02-12 삼성전자주식회사 Method of forming a wiring structure
KR20220105189A (en) * 2021-01-18 2022-07-27 삼성전자주식회사 Semiconductor device and method manufacturing the same
US11670546B2 (en) * 2021-03-04 2023-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
KR20220165506A (en) 2021-06-08 2022-12-15 삼성전자주식회사 Semiconductor device and method for fabricating thereof
US20230060269A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Forming Interconnect Structures in Semiconductor Devices
JP2023128046A (en) * 2022-03-02 2023-09-14 キオクシア株式会社 Semiconductor device and manufacturing method thereof

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US6245690B1 (en) * 1998-11-04 2001-06-12 Applied Materials, Inc. Method of improving moisture resistance of low dielectric constant films
JP4457426B2 (en) * 1999-03-16 2010-04-28 ソニー株式会社 Manufacturing method of semiconductor device
JP4858895B2 (en) * 2000-07-21 2012-01-18 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US6440838B1 (en) 2001-11-20 2002-08-27 Taiwan Semiconductor Manufacturing Co., Ltd Dual damascene structure employing laminated intermediate etch stop layer
US6635576B1 (en) * 2001-12-03 2003-10-21 Taiwan Semiconductor Manufacturing Company Method of fabricating borderless contact using graded-stair etch stop layers
US6734116B2 (en) 2002-01-11 2004-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Damascene method employing multi-layer etch stop layer
US6525428B1 (en) 2002-06-28 2003-02-25 Advance Micro Devices, Inc. Graded low-k middle-etch stop layer for dual-inlaid patterning
JP4086673B2 (en) 2003-02-04 2008-05-14 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
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Also Published As

Publication number Publication date
KR102356754B1 (en) 2022-01-27
US10475739B2 (en) 2019-11-12
US20190304903A1 (en) 2019-10-03
US20190043803A1 (en) 2019-02-07
KR20190014338A (en) 2019-02-12
CN109390273A (en) 2019-02-26
CN109390273B (en) 2023-09-22

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