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SE9001317L - PERIODRAEKNARE - Google Patents

PERIODRAEKNARE

Info

Publication number
SE9001317L
SE9001317L SE9001317A SE9001317A SE9001317L SE 9001317 L SE9001317 L SE 9001317L SE 9001317 A SE9001317 A SE 9001317A SE 9001317 A SE9001317 A SE 9001317A SE 9001317 L SE9001317 L SE 9001317L
Authority
SE
Sweden
Prior art keywords
gate
counter
output
input signal
multiplier
Prior art date
Application number
SE9001317A
Other languages
Swedish (sv)
Other versions
SE9001317D0 (en
Inventor
M Takahashi
Original Assignee
Ando Electric
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ando Electric filed Critical Ando Electric
Publication of SE9001317D0 publication Critical patent/SE9001317D0/en
Publication of SE9001317L publication Critical patent/SE9001317L/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/02—Input circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/02—Input circuits
    • H03K21/026—Input circuits comprising logic circuits

Landscapes

  • Manipulation Of Pulses (AREA)
  • Measuring Frequencies, Analyzing Spectra (AREA)

Abstract

PURPOSE:To reduce the irregularity of the cycle of an input signal by connecting a multiplier and a frequency divider between the input signal and a counter and making the output of the frequency devider a gate signal. CONSTITUTION:An input signal 11 is multiplied by (n) by a multiplier 1 and the output of the multiplier 1 is divided into 1/m in its frequency by a frequency divider 2. The output of the frequency divider 2 is supplied to a counter 3 as a gate signal 12 while he counter 3 opens and closes a gate following the gate signal 12 to count a reference clock 13 only during a gate open time. This count value becomes count data 14 as the output of the counter 3 to make it possible to reduce not only the irregularity of a gate time but also the cycle irregularity of the input signal.
SE9001317A 1989-04-21 1990-04-11 PERIODRAEKNARE SE9001317L (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1102781A JPH02281154A (en) 1989-04-21 1989-04-21 Cycle counter

Publications (2)

Publication Number Publication Date
SE9001317D0 SE9001317D0 (en) 1990-04-11
SE9001317L true SE9001317L (en) 1990-10-22

Family

ID=14336687

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9001317A SE9001317L (en) 1989-04-21 1990-04-11 PERIODRAEKNARE

Country Status (3)

Country Link
JP (1) JPH02281154A (en)
FI (1) FI901979A0 (en)
SE (1) SE9001317L (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5883558B2 (en) * 2010-08-31 2016-03-15 セイコーエプソン株式会社 Frequency measuring device and electronic device

Also Published As

Publication number Publication date
JPH02281154A (en) 1990-11-16
SE9001317D0 (en) 1990-04-11
FI901979A0 (en) 1990-04-20

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