SE513516C2 - Method and apparatus for routing in a circuit-switched network - Google Patents

Abstract

Hence, according to the invention, a multi-channel multi-access bitstream (B) carrying isochronous channels is accessed, said isochronous channel being used for the transfer of asynchronous traffic, and a data packet from a node connected to said bitstream is received in an isochronous channel thereof. Then, it is determined if said data packet is to be transmitted to another node connected to said bitstream using another channel of said isochronous channels. If so, said data packet is transmitted to said another node using said another channel of said isochronous channels on said bitstream.

Description

15 20 25 30 35 513 516 2 The bandwidth for each wavelength of the bus, i.e. each bitstream of each fiber, is divided into recurring frames of fixed length, which frames are in turn divided into time slots of fixed size. The number of time slots in a frame thus depends on the bit rate of the network. The time slots are divided into two groups, control time slots and data time slots. Control time slots are usually used for transmitting signaling messages between the nodes of the network's internal function. The data time slots are usually used for the transmission of data between end users connected to the various nodes.

Each node is set up to dynamically set up, take down and modify DTM channels by dynamically allocating time slots.

When DTM channels are used for the transmission of asynchronous traffic, such as TCP / IP packets, a mechanism is needed to effect routing of the packets through the DTM network. Routing solutions that are currently available are, however, developed for use in other types of network architectures and therefore propose mechanisms that provide poor utilization of the advantageous aspects of a DTM-type network.

It is therefore an object of the invention to provide a routing solution in a DTM type network, which solution makes better use of the features of such a network.

Summary of the Invention The above and other objects are achieved by the invention as defined in the appended claims.

Thus, in accordance with the invention, a multi-channel multi-access bitstream carrying isochronous channels is accessed, the isochronous channels being used for transmitting asynchronous traffic, and a data packet is received from a node connected to the bitstream in an isochronous channel thereof.

It is then determined whether the data packet is to be sent to another node connected to the bitstream using any other channel of said isochronous channels. If so, the data packet is sent to the second node using the second channel of the isochronous channels on the bitstream.

The invention thus provides routing of the data packet among single-channel multi-channel bitstream currents, in conventional solutions a router is usually provided to interconnect two or more separate networks or network sections, and to provide routing of data packets between such network sections. .

The routing solution according to the invention differs from this conventional arrangement in that the routing is achieved within a single network section, more specifically among the channels on a multi-channel multi-access bitstream.

Accordingly, a routing mechanism according to the invention which provides routing among channels of a single bitstream need not be provided at a starting point of the bitstream, i.e. at the point of interconnection, typically via a switch or the like, with another bitstream. Note, however, that this does not mean that a routing mechanism according to the invention is limited to routing with respect to channels of a single bit stream, since it is also possible to use conventional routing from said bit stream to another bit stream without deviating from the inventive idea.

It will be appreciated that the routing mechanism of the invention gives a network designer greater freedom in architecture in designing networks. An example of this is given below with reference to Fig. 5. According to a preferred embodiment of the invention, the routing mechanism does not access channels on the bitstream. Instead, such channels are bypassed, usually in the interface of one not to be routed by the routing mechanism. device providing the routing mechanism. Consequently, the traffic in the bypassed channels will be disregarded QQh_unaffected by the routing mechanism. Of course, this requires the provision of means for separating channels of the isochronous channels to be received and channels not to be received.

According to an embodiment of the invention, however, if a data packet is received on a channel carrying asynchronous traffic which is to be routed by the routing device but also extends beyond the routing device, ie a multicast channel which does not terminate in the routing device , further transmission of the data packet to other nodes connected to the bitstream is not prevented using the isochronous channel from which the data packet was received. Accordingly, a channel, for example, may be a multicast channel, one data packet reaching a set of receivers, but the data packet being simultaneously routed to another channel on the bitstream, for example to reach another set of receivers.

As mentioned initially, a preferred use of the invention is in a network operating according to a (DTM), i.e. a so-called DTM network, said isochronous channels being DTM channels in a DTM network.

By definition, protocol for “Dynamic synchronous Transfer Mode” “DTM network” a circuit-switched, time-multiplexed network of the type referred to here, a formation is transmitted between nodes in the network on bit streams.

Each bitstream is divided into regular, recurring frames of fixed size, so-called DTM frames, each of which comprises a number of time slots of fixed size, which time slots are divided into control time slots and data time slots. Thus, at any given time, a time slot position in a DTM frame defines either a control time slot or a data time slot. Control time slots are used for control signaling between nodes in the network and data time slots are used for the transmission of user data (often referred to as utility traffic).

In a DTM network, write access to the time slots in a DTM frame is further distributed among the nodes connected to the bitstream carrying the DTM frame, each node usually having write access to at least one control. un., 10 15 20 25 30 35 513 516 5 slot and at least one dynamically adaptable set of data time slots within each recurring frame. Having write access to a time slot position in a frame further means having write access to the time slot position within each recurring "frame".

In a DTM network, a node will use the data time slots to which it has write access to set up so-called DTM channels by allocating one or more of the data time slots_to each DTM channel. Therefore, as referred to herein, a DTM channel is defined by one or more time slots occupying the same time slot position within each DTM frame by the bitstream from which the DTM channel is carried. However, if, for example, a DTM channel passes over two bit streams, the channel can of course be defined by different sets of time slot positions on the two bit streams. Furthermore, a DTM channel can be either a control channel or a data channel, depending on whether control or data time slots are allocated to the channel. In addition, a DTM channel can be a one-to-one channel (unicast channel), a one-to-several channel (multicast channel) or a one-to-all channel (broadcast channel). network capacity is changed, DTM channels can be set up, taken down or modified, the latter by changing the number of time slots allocated to a DTM channel, and the distribution of write access to time slots between the different nodes can be dynamically modified as different nodes develop different needs for control signaling and data transmission.

According to another preferred embodiment of the invention, a routing mechanism according to the above-mentioned type is performed in relation to a single memory which provides temporary storage of data packets in its memory locations, whereby the memory locations are temporarily allocated for storage of the respective data packets. The memory is then accessed_for writing / reading data packets regardless of which channel a data packet is received / sent on, and is thus used as a shared memory of all channels. This provides a relatively simple design for handling data packets relative to multi-channel routing according to the invention.

Further aspects and advantages of the invention will become apparent to those skilled in the art from the appended claims and from the following detailed description of exemplary embodiments thereof.

Brief Description of the Drawings Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Fig. 1 schematically shows an example of the structure of a bitstream in a circuit-switched, time-multiplexed network operating according to a DTM protocol; Fig. 2 schematically shows the transmission of asynchronous traffic on one of the isochronous channels carried by the bitstream shown in Fig. 1; Fig. 3 schematically shows an exemplary embodiment of a device according to the invention; Fig. 4 schematically shows another exemplary embodiment of a device according to the invention; Fig. 5 schematically shows a net comprising the device shown in Fig. 4.

Detailed Description of an Exemplary Embodiment An example of the structure of a multi-channel bitstream B with multiaccess in a circuit-switched, time-multiplexed network operating according to a DTM protocol will now be described with reference to Fig. 1.

As shown in Fig. 1, the bitstream B is divided into recurring frames of substantially fixed size, the start of each frame being defined by a time slot F for frame synchronization. Each frame has a length of l25ps.

Each frame is further divided into a plurality of time slots of fixed size, typically 64 bits. When using the frame length of 125ps, the time slot size of 64 bits and the bit rate of 2 Gbps, the total number of time slots within each frame will be approximately 3900.

The time slots are divided into control time slots C1, C2, C3 and C4, and data time slots D1, D2, D3 and D4. The control time slots are used for control signaling between the nodes in the network, while the data time slots are used for the transmission of payload traffic. Each node connected to the bitstream B is typically allocated at least one control time slot, ie each node will have write access to at least one control time slot. Furthermore, write access to data time slots is distributed among the nodes connected to the bitstream.

Consequently, a node N1 (which is connected to the bitstream B) will have access to a control time slot C1 and a set of data time slots D1 within each frame of the bitstream, and so on. The set of time slots allocated to a node such as control time slot (s) and / or data time slot (s) occupy the same time slot position within each frame of the bitstream.

During operation of the network, each node can increase or decrease its access to control time slots and / or data time slots, thereby redistributing access to control time slots and / or data time slots between the nodes. For example, a node that has a low need for transmission capacity can give away its access to data time slots to a node that has a greater need for transmission capacity. Furthermore, the time slots allocated to a node do not have to be consecutive time slots but can be located anywhere within the frame; * 'W _ Also note that each frame starts with the frame synchronization time slot, which defines the frame rate of the bitstream and ends with one or more several filling time slots G.

In Fig. 1, at (c), it is further assumed that the node N2, which has access to its control time slot C2 and its range of data time slots D2, has set up four channels CH1, CH2, CH3 and CH4 on the bitstream. As shown, each channel has a allocated set of time slots each. In the example, the transmission capacity on channel CH1 is greater than the transmission capacity on channel CH2, since the number of time slots allocated to channel CH1 is greater than the number of time slots allocated to channel CH2. The time slots allocated to a channel occupy the same time slot positions in each recurring frame of the bitstream.

An example of the transmission of asynchronous traffic on one of the isochronous channels carried by the bitstream B shown in Fig. 1 will now be described with reference to Fig. 2. In Fig. 2 it is assumed that the channel CH3, in Fig. 1, is set up for to carry asynchronous traffic in the form shown by sequentially transmitted variable size data packets, which could be, for example, TCP / IP packets or Ethernet frames. (Note that Fig. 2 only shows the sequence of time slots transmitted within the channel CH3). Since Fig. 1 schematically indicates that the channel CH3 comprises seven time slots in each frame on the bitstream B, the first seven time slots transmitted on the channel CH3, i.e. the next seven subsequent time slots, will be transmitted in the next frame. and set the time slots in Fig. 2 to be transmitted in a frame, so on.

Fig. 2 shows three data packets transmitted on the channel CH3.

Each data packet is encapsulated [?] According to a predefined encapsulation protocol. In Fig. 2, it is assumed that the encapsulation protocol defines that each data packet is to be divided into a number of data blocks of 64 data bits (which corresponds to the size of a time slot), that a start_of¿packet-time slot S is to be added at the beginning of each data packet, and that an end_of_packet time slot E should be added at the end of each data packet, thereby forming encapsulated data packets P1, P2, and P3. In the event of a gap between the packets, the bitstream is provided with so-called idle time slots, which identify the gaps as containing no valid data.

An embodiment of the device according to the invention will now be described with reference to Fig. 3. In Fig. 10, the device 110 comprises a port 111, which in turn comprises an interface 113 for incoming channels and an interface 114. for outgoing channels, which provide read and write access to a bitstream B, which may be, for example, the bitstream B shown in Fig. 1. The interfaces for incoming and outgoing channels provide synchronization of the work of the device in relation to frame and the time slot frequency of the bitstream B.

The incoming channel interface and the outgoing channel interface are connected to an incoming channel channel manager 115 and an outgoing channel manager 116, respectively. The channel manager 115 for incoming channels and the channel manager 116 for outgoing channels have a buffer manager 120 and a control unit both connected to a routing processor 117, shared memory 119, 121. The routing processor 117 is in turn connected to a routing memory 118.

In operation, the incoming channel interface 113 receives (arrow 1) data packets from the channels monitored by the interface, such as the encapsulated TCP / IP packets on the channel CH3 shown in Fig. 2. Each data packet is encapsulated according to a predefined protocol and is typically received as a set of consecutive, 64-bit sequential data blocks.

The incoming channel interface 113 then forwards, while maintaining sequential order, each received data block to the incoming channel manager 115 (arrow 2). Each data block forwarded to the incoming channel manager 115 is accompanied by a channel identifier indicating the channel from which it was received.

After receiving enough blocks at the front of a data packet to be able to derive information indicating the size of the data packet, the incoming channel manager will send a request (arrow 3) containing the size of the data packet to the buffer manager 120. The request will thereby inform the buffer manager 120 that the channel manager 115 for incoming channels needs to store a data packet of the specified size in the shared memory 119.

The buffer manager 120 will then allocate an address in the shared memory 119 for the data packet, the allocated address space being not less than the data packet. The buffer manager 120 will respond to the request by returning (arrow 4) a start address corresponding to the start of the address space of the channel manager 115 for incoming channels.

After receiving the start address from the buffer manager 120, the incoming channel manager will start writing the data blocks that make up the associated data packet in the shared memory 119 (arrow 5), starting with the start address received from the buffer manager 120, and increment the address one step for each data block written in the shared memory 119.

At the same time, the channel manager 115 for incoming channels sends the start address received from the buffer manager 120, together with that in the start portion of the data packet (arrow 6). (arrow 7) the specified address, to the routing processor 117 Using the routing memory 118 more the routing processor, based on the destination address received from the incoming channel interface 115, whether the associated data packet is to be sent from the outgoing channel interface 114 and, if so, - the outgoing channel to be used when sending the data packet.

After determining the outgoing channel for the data packet, the routing processor 117 sends a signal to the outgoing channel manager 116 (arrow 8) which contains an identifier and the start address received from the incoming channel manager. The channel identifier identifies the outgoing channel to be used when the associated data packet address is transmitted, and the start address indicates where in the shared memory 120 the associated data packet is to be read from. 10 15 20 25 30 35 513 516 11 After receiving the channel identifier for the outgoing channel and the start address from the routing processor 117, the channel manager 116 for outgoing channels accesses the shared memory (arrow 9) and starts reading (arrow 10) data blocks forming the associated data packet from the shared memory 119 with the start den on the start address received from the routing processor 117 and the address increments one step for each data block read out from the shared memory 119.

At the same time, the outgoing channel channel manager 116 continuously receives requests (arrow 11) for data blocks for each outgoing channel from the outgoing channel interface 114, which requests are sent from the outgoing channel interface at the rate at which time slots are allocated on the respective channels. channel passes on the outgoing bitstream accessed via the output channel 114.

The outgoing channel manager 116 forwards (arrow 12), triggered by the data block requests, when the requests relate to a channel identified by a channel identifier received from the routing processor 117, in sequential order, each data block of the associated data packet, the memory 119 starting from the specified start address, as it is read from the shared to the outgoing channel interface 114. The output channel interface 114 (arrow 13) then in turn forwards the received data blocks to the respective channels on the output bitstream.

After retrieving the last data block in a data packet from the shared memory 119 (arrow 14), the outgoing channel channel manager 120 returns the associated start address received from the routing processor 117 to the buffer manager 120. This informs the buffer manager that the processing of that data packet which is stored on the address area associated with the start address has been completed and that the buffer manager is now free to allocate the address area to a new data packet received via the incoming channel interface.

Furthermore, the controller 121 determines which channels are to be received by the incoming channel interface 113, which are usually the channels used for transmitting data packets that need to be routed by the routing processor 117. Channels not to be routed to the routing processor 117, according to decision consequently, the control unit 121, 114 is not processed by the routing processor. bypassed in the interfaces 113, for incoming / outgoing channels and Another embodiment of the device according to the invention will now be described with reference to Fig. 4.

In the device of Fig. 4, the only difference compared to the embodiment of Fig. 3 is that the channel manager 115 for incoming channels in Fig. 4 is provided with a cache memory 122. addresses for which no routing needs to be done The cache memory 122 contains a list of destinations of the routing processor 117 , as previously determined by the routing processor. A received data packet referring to an address in the list of destination addresses should not be directed to the routing processor 117. The routing processor continuously updates the contents of the cache 122.

Accordingly, when receiving a data packet, the incoming channel channel manager 115 will compare the destination packet's destination address with the destination addresses 122. If a match is found, the data packet is discarded in the incoming channel channel manager and will therefore not be directed to routers. thing processor 117, thereby reducing the load on the routing processor.

Note, however, that if the channel from which the data packet was received does not end in the device 110 but instead continues to one or more other nodes downstream, for example if the channel is a multicast channel or broadcast channel, the data packet is forwarded to nodes downstream of the same channel received regardless of whether it was discarded in the channel manager for incoming channels, if this bypass is made in the incoming / outgoing channels 113, 114 or in the handlers 115, 116 for incoming / outgoing channels are usually determined by the control unit 121).

A network utilizing the invention will now be described with reference to Fig. 5. In Fig. 5, a multi-channel multi-access bitstream B, which may be, for example, the bitstream B shown in the preceding figures, forms a. link in the form of a closed loop connecting a plurality of access nodes A which use circuit-switched time multiplexing according to a DTM protocol. An exchange node S which is connected to the link provides connectivity between the link and another link which also uses circuit-switched time division multiplexing according to the DTM protocol. On the latter link, a router R provides access to a packet-switched network, such as the Internet. Furthermore, the device 110 according to the invention, for example the device described with reference to Figs. 3 and 4, is connected to the bitstream B.

In Fig. 5, the node device 110 has typically set up an isochronous channel to the route R via the exchange S. When an end user connected to an access node A on the bitstream wants to send a data packet, it can set up a channel to the correct destination after its own choice, for example a channel to another access node on the bitstream B or a channel to the router R via the switch S. However, it can also use a channel to the node device 110, which then, after receiving the data packet, ensures that the data packet The channel is forwarded to the correct destination, for example via a channel to the router R. _ According to an alternative embodiment, multicast channels are set up from each node connected to the bitstream B to all other nodes connected to the bitstream B. If a end user, which is connected for an access to the node A on the bitstream B, wants to send a data packet to any destination one-to-several, it will simply send the packet by means of the multicast channel. If, when the one-to-several transmitted packet is read in the nodes receiving the multicast channel, it turns out that the destination address of the data packet refers to an end user connected to another access node on the bitstream, said second access node will ensure that the data packet is forwarded to that end user. However, if it turns out that the destination address of the data packet refers to end users who are not connected via any access node to the bitstream, the node device 110 will ensure that the data packet is forwarded to the correct destination, for example via a point-to-point channel to the router R. Although the invention has been described above with reference to exemplary embodiments of the invention, these should not be construed as limiting the scope of the invention.

Accordingly, as will be appreciated by those skilled in the art, various modifications, combinations, and changes may be made within the scope of the invention as defined by the appended claims. (1 (f.

Claims (19)

10 15 20 25 30 35 513 516 15 PATENT CLAIMS A method of routing asynchronous traffic in a circuit-switched circuit, comprising the steps of: synchronously, time-multiplexed network, receiving, on an isochronous channel on a multi-channel multi-access bitstream carrying isochronous channels, which isochronous channel is used for transmitting asynchronous traffic, a data packet from a node connected to the bitstream; deciding whether to send the data packet to another node connected to the bitstream using another channel of the isochronous channels; and, if so, sending the data packet to the second node using the second channel of the isochronous channels on the bitstream. The method of claim 1, determining which channels of the isochronous channels are to be included including the steps to be received and bypassing the channels not to be received. Method according to claim 1 or 2, comprising the step of discarding the data packet if it is not to be sent to another node connected to the bitstream using another channel of the isochronous channels. A method according to claim 1, 2 or 3, wherein further transmission of the data packet to other nodes connected to the bitstream using the isochronous channel from which the data packet was received is allowed. Method according to claim 1, 2, the circuit, when transmitted within the channel, is encapsulated according to a 3 or 4, wherein data-defined encapsulation protocol. 10 15 _20 25 30 35 515 516 16 A method according to any one of the preceding claims, wherein the steps are performed in a node connected to the multi-channel multi-access bitstream. A method according to any one of the preceding claims, wherein the steps are performed in a node which provides routing of data packets only among channels carried by said multi-channel multi-access bitstream. Method according to one of the preceding claims, wherein the network operates according to a protocol for “Dynamic synchronous Transfer Mode” (DTM). A method according to any one of the preceding claims, wherein the receiving step comprises temporarily allocating a location in a shared memory for storing the data packet at said location in the shared memory, and wherein the sending step comprises reading the data packet from the location in the shared memory. A device (110) crown traffic in a circuit-switched, which provides routing of asynchronous, time-multiplexed network, comprising: an interface (III) for providing access to a multi-channel multi-access bitstream carrying isochronous channels: and routing means (117) to determine whether a data packet received by the interface on an isochronous channel carrying asynchronous traffic is to be transmitted by the isochronous channels using another of the isochronous channels and, if so, direct the data packet there via the interface. 11. ll. Device according to claim 10, comprising means for determining which channels of the isochronous channels are to be received by the interface and which channels are to be bypassed by the interface. 10 15 20 25 30 35 513 516 17 The device of claim 10 or 11, wherein the interface comprises means (122) for determining whether the data packet is to be transmitted using any of the isochronous channels and, if so, for preventing the data packet is processed by said routing means. Device according to claim 10, 11 or 12, wherein the interface is arranged to forward the data packet using the isochronous channel from which the data packet was received, in addition to the decisions taken by the determining means. Device according to claim 10, 11, 12 or 13, when the data packet, when transmitted within the channel, is encapsulated according to a predefined encapsulation protocol. An apparatus according to any one of claims 10-14, wherein the routing means provides routing of data packets only among the channels carried by said multi-channel multi-access bitstream. Device according to any one of claims 10-15, wherein the network operates according to a protocol for “Dynamic synchronous Transfer Mode” (DTM). The apparatus of any of claims 10-16 further comprising a memory (119) for temporarily storing data packets at a memory location therein, the memory location being temporarily allocated for storing said data packets, the interface being adapted to write the data packet at the allocated memory location upon receipt. of the data packet and reading the data packet from the allocated memory location when sending the data packet. 10 513 516 18 The apparatus of claim 17, further comprising a memory manager (120) configured to temporarily allocate a memory location for storing the data packet and to provide the interface with information indicating the memory location for storing the data packet. Device according to claim 17 or 18, the nose location is allocated for storing the data packet which is a result of a request made by the interface upon receipt of the data packet.