RU51428U1 - FAULT-RESISTANT PROCESSOR OF INCREASED FUNCTIONAL RELIABILITY - Google Patents

Abstract

The utility model relates to the field of automation and computer technology and is intended to increase the reliability of the processor by correcting 46% of errors, the multiplicity of which does not exceed k-1, provided that the maximum number of errors in the code set is detected. This is achieved by introducing a correction block for detecting and correcting errors in the control memory of the processor, by introducing a control block to detect and correct errors of the arithmetic-logical device when performing arithmetic and logical operations.

Description

The utility model relates to computer technology and can be used to increase the reliability of the functioning of the computer processor.

It is known self-correcting discrete device [1], containing the original circuit, the first encoding device, the scheme of the error syndrome, error decoder, corrector, the second, third and fourth encoding devices, the first to fourth convolution schemes, the error indicator circuit, the OR element, the device inputs are connected to the original circuit and to the inputs of the first encoder, to the inputs of the second encoder, and the outputs of the original circuit are connected to the inputs of the third and fourth encoders, to the first inputs of the corrector, the outputs to They are the device outputs, the outputs from the first to fourth encoding devices are connected respectively to the inputs from the first to fourth convolution schemes, the outputs of the first and third convolution schemes are connected to the inputs of the error syndrome circuit, the outputs of the second and fourth convolution schemes are connected to the inputs of the error symptom circuit, the outputs schemes of the error syndrome and the error sign are connected to the inputs of the error decoder, the first group of outputs of the error decoder is connected to the second inputs of the corrector, and the second group of outputs is connected to the input of the element OR, from the output of which the "device failure" signal is removed.

The disadvantage of this device is the limited scope of its application, since it allows to ensure high reliability of the operation of only computer storage devices.

The closest in technical solution is the processor [2], containing a control node, an operational node, the first group of inputs

the control node is the processor inputs, the second group of inputs of the control node is connected to the first outputs of the operational node, the outputs of the control node are connected to the first inputs of the operational node, the second inputs of which are data inputs, and the second outputs are data outputs.

The disadvantage of this device is the low reliability of operation, since it does not provide for the detection and correction of errors when performing arithmetic and logical operations (information converters: adder, shift registers, devices for performing logical operations).

The aim of the invention is to increase the reliability of the processor due to the detection and correction of errors.

This goal is achieved in that the processor containing the control unit, the operation unit, the first inputs of the control unit are the inputs of the processor, the second group of inputs of the control unit is connected to the first outputs of the operation unit, the outputs of the control unit are connected to the first inputs of the operation unit, the second inputs of which are inputs data, and the second outputs are data outputs, characterized in that it further comprises an operation code decoder, a clock, a control unit, a first comm tator, second switch, third switch, command counter, shift counter, address register, number register, adder register, additional register, additional code register, adder, correction block, logical operations unit, control memory, control unit, including correction shaper, which in turn, contains a functional diagram of the amendment when performing arithmetic operations, a functional diagram of the amendment when performing the shift operation, a functional diagram of the amendment when performing the OR operation, functional diagram

forming corrections during operation AND, a functional diagram for generating corrections during operation NOT, the inputs of the exchange device are connected to the first input of the control unit and to the first inputs of the second switch, the second inputs of which are connected to the outputs of the storage device, the first outputs of the second switch go to the input of the exchange device , the second outputs go to the input of the storage device, and the third outputs are connected respectively to the first inputs of the command counter, shift counter, register numbers, reg the adder register, additional register, additional code register, to the inputs of the operation code decoder, to the second inputs of the control unit, to the first input of the first switch, the first output of which is connected to the first input of the address register, the third input of the control unit is connected to the outputs of the operation code decoder, fourth input connected to the outputs of the clock generator, and the fifth input is connected to the first output of the control memory, the first output of the control unit is connected to the input of the control memory, the outputs of which are connected to the first inputs of the correction unit, the second output of the control unit is connected to the second input of the first switch, the second and third inputs of which are connected respectively to the outputs of the address register and command counter, and the memory cell address is taken from the second output, the third output of the control unit is connected respectively to the second inputs of the correction block, to the second inputs of the command counter, shift counter, address register, number register, adder register, additional register, additional code register, to p the first group of inputs of the third switch and the third group of inputs of the second switch is the output of the clock pulses, the first output of the correction unit is connected to the fourth input of the second switch, and the second, third, fourth and fifth outputs of the correction unit are connected respectively to the third, fourth fifth and sixth inputs of the counter commands, shift counter, address register, number register, adder register, additional register, register

additional code, to the first group of inputs of the third switch, to the third group of inputs of the second switch, and are the outputs of control signals, read signals, write signals, signals to set the devices to zero, outputs of the number register, adder register, additional register, additional code register are connected to the second inputs of the third switch and to the fifth inputs of the second switch, the output of the shift counter is connected to the sixth inputs of the second switch, the first, second and third outputs of the third utatora respectively connected to the inputs of the adder, logic unit operations and control inputs of the first unit block and the adder outputs logical operations are connected respectively to second and third inputs of the control unit which outputs are connected to second inputs of the seventh switch.

Figure 1 presents a block diagram of a device; figure 2 is a functional block diagram of the correction; figure 3 is a functional diagram of a control unit; figure 4 is a functional diagram of the formation of the amendment when performing arithmetic operations; figure 5 is a functional diagram of the formation of the amendment when performing the shift operation; figure 6 is a functional diagram of the formation of the amendment when performing the OR operation; Fig.7 is a functional diagram of the formation of the amendment when performing the operation And; on Fig is a functional diagram of the formation of the amendment when performing the operation is NOT.

The processor (figure 1) contains a control node 1, an operation node 2, an operation code decoder 3, a clock pulse generator 4, a control unit 5, a first switch 6, a second switch 7, a third switch 8, a command counter 9, a counter 10 shifts, a register 11 addresses, number 12 register, adder register 13, additional register 14, additional code register 15, adder 16, correction unit 17, logical operation unit 18, control unit 19, control memory 20, first inputs 21 of correction unit 17, second inputs 22 block 17 correction, the first outputs 23

correction block 17, second outputs 24 of correction block 17, second inputs 25 of control block 19, first inputs 26 of control block 19, third inputs of control block 19, first outputs 28 of control block 19, second outputs 29 of control block 19 (output 29 ₁ - error in the control bits, output 29 ₂ — error non-correctable error, output 29 _{3 —} correctable error), outputs 30 of the exchange device, outputs 31 of the storage device, outputs 32 to the exchange device, outputs 33 for generating the address of the storage device, outputs 34 for reading operands to storage device O clock outputs 35, 36 outputs control signals to outputs 37 for commands reading, outputs 38 for recording signals 39 outputs signals for setting to zero.

Correction block 17 (FIG. 2) contains a coding circuit 40, a comparison circuit 41, a first group of OR elements 42, a second group of 43 OR elements, a third group of 44 OR elements, a fourth group of 45 OR elements, a fifth group of 46 OR elements, a sixth group 47 OR elements, the seventh group of 48 OR elements, the element 49 NOT, the first group of 50 AND elements, the second group of 51 AND elements, the corrector 52, the decoder 53, the outputs 21 of the control memory 20, the input 22 allowing reading of the output information, the output 23 "Processor failure" outputs 24 for control signals of functional units processor s.

The control unit 19 (Fig. 3) contains a first group of 54 disambiguation elements, a second group of 55 discontinuity elements, a third group of 56 discontinuity elements, a first group of 57 OR elements, a second group of 58 OR elements, a third group of 59 OR elements, a fourth group of 60 OR elements , the fifth group of 61 OR elements, the sixth group of 62 OR elements, the seventh group of 63 OR elements, the eighth group of 64 OR elements, the ninth group of 65 OR elements, the tenth group of 66 OR elements, the eleventh group of 67 OR elements, the twelfth group of 68 elements OR, the thirteenth group of 69 elements OR, the first group of 70 elements AND, the second group of 71 elements

And, the third group of 72 AND elements, the fourth group of 73 AND elements, the fifth group of 74 AND elements, the sixth group of 75 AND elements, the seventh group of 76 AND elements, the eighth group of 77 AND elements, the first element 78 NOT, the second element 79 NOT, the shaper 80 , a decoder 81, a corrector 82, a shaper 83 of the amendment, which contains a functional diagram of the formation of the amendment when performing arithmetic operations, a functional diagram of the formation of the amendment when performing the shift operation, a functional diagram of the formation of the amendment when performing the OR operation, func an ion correction circuit for performing the operation AND, a functional correction circuit for performing the operation NOT, the first coding circuit 84, the second coding circuit 85, the first inputs 86 of the shaper 83 of the amendment, the second inputs 87 of the shaper 83 of the amendment, the third inputs 88 of the shaper 83 of the amendment, the first outputs 89 of the shaper 83 of the amendment, the second outputs 90 of the shaper 83 of the amendment, the third outputs 91 of the shaper 83 of the amendment.

Functional diagram of the correction when performing arithmetic operations (figure 4) contains the first element 92 AND, the second element 93 AND, the third element 94 AND, the fourth element 95 AND, the fifth element 96 AND, the sixth element 97 AND, the first element 98 OR, the second element 99 OR, the third element 100 OR, the fourth element 101 OR, the register 102, a group of elements 103 discontinuities, information inputs 87, input 86 that allows the reading of output information, information outputs 89, 90 of the functional circuit for generating corrections when performing arithmetic operations.

Functional diagram of the correction during the shift operation (Fig. 5) contains the first discontinuity element 104, the second discontinuity element 105, the third discontinuity element 106, the first element 107 I, the second element 108 I, the third element 109 I, the fourth element 110 I, the fifth element 111 AND, the sixth element 112 AND, the seventh element 113 AND, the eighth element 114 AND, the ninth

element 115 AND, tenth element 116 AND, eleventh element 117 AND, twelfth element 118 AND, first element 119 OR, second element 120 OR, third element 121 OR, fourth element 122 OR, information inputs 87, input 86 _{1 of the} control signal shift to the right , input 86 _{2 of the} control signal, shift to the left, input 86 allowing reading of the output information, outputs 89, 91 of the correction circuit when performing the shift operation.

Functional diagram of the correction when performing the logical operation OR (Fig.6) contains the first element 123 AND, the second element 124 AND, the third element 125 AND, the fourth element 126 AND, the fifth element 127 AND, the sixth element 128 AND, the seventh element 129 AND, the eighth element 130 AND, information inputs 87, input 86 permits reading of the output information, information outputs 89, 91 of the functional circuit for generating corrections when performing the logical OR operation.

Functional diagram of the correction when performing the logical operation AND (Fig. 7) contains the first element 131 OR, the second element 132 OR, the third element 133 OR, the fourth element 134 OR, the first element 135 AND, the second element 136 AND, the third element 137 AND, the fourth element 138 And, the information inputs 87, the input 86 permits the reading of the output information, the information outputs 89, 91 of the functional circuit for generating corrections when performing logical operation I.

The correction correction flowchart when performing the logical operation NOT (Fig. 8) contains the first element 139 NOT, the second element 140 NOT, the third element 141 NOT, the fourth element 142 NOT, the first element 143 of unequality, the second element 144 of unevenness, the third element 145 of ambiguity, the fourth element 146 of ambiguity, the first element 147 And, the second element 148 And, the third element 149 And, the fourth element 150 And, the fifth element 151 And, the sixth

element 152 And, information inputs 87, input 86 permitting the reading of output information, inputs 88 of the parity bits of the control bits, information outputs 89, 91 of the correction correction functional circuit when performing the logical operation NOT.

The inputs 30 of the exchange device are connected to the first input of the control unit 5 and to the first inputs of the second switch 7, the second inputs of which 31 are connected to the outputs of the storage device, the first outputs 32 of the second switch 7 go to the input of the exchange device, the second outputs go to the input 34 of the storage device and the third outputs are connected respectively to the first inputs of the counter 9 commands, counter 10 shifts, register 12 numbers, register 13 adder, register 14 additional, register 15 additional code, to the inputs of the decoder 3 code o operation to the second inputs of the control unit 5, to the first inputs of the first switch 6, the first output of which is connected to the first input of the address register 11, the third input of the control unit is connected to the outputs of the decoder 3 operation code, the fourth input is connected to the outputs of the generator 4 clock pulses, and the fifth input is connected to the first output of the control memory 20, the first output of the control unit 5 is connected to the input of the control memory 20, the outputs of which are connected to the first inputs of the correction unit 17, the second output of the control unit 5 is connected to the second input the first switch 6, the second and third inputs of which are connected respectively to the outputs of the address register 11 and the command counter 9, and the address of the memory cell of the storage device is removed from the second output 33, the third output of the control unit 5 is connected respectively to the second inputs of the correction unit 17, to the second inputs counter 9 commands, counter 10 shifts, register 11 addresses, register 12 numbers, register 13 adders, register 14 additional, register 15 additional code, to the first group of inputs of the third switch 8 and to the third group of inputs of the next switch 7 and is the output of 35 clock pulses, the first output of the correction unit 17 is connected to

the fourth input of the second switch 7, and the second, third, fourth and fifth outputs of the correction unit are connected respectively to the third, fourth fifth and sixth inputs of the counter 9 commands, counter 10 shifts, register 11 addresses, register 12 numbers, register 13 adder, register 14 additional register 15 additional code to the first group of inputs of the third switch 8, to the third group of inputs of the second switch 7, and are outputs 36 of the control signals, read signals 37, write signals 38, signals 39 setting the devices to zero status, outputs of register 12, register 13 of adder, register 14 of additional, register 15 of additional code are connected to the second inputs of the third switch 8 and to the fifth inputs of the second switch 7, the output of the counter 10 shifts is connected to the sixth inputs of the second switch 7, the first, second and the third outputs of the third switch 8 are connected respectively to the inputs of the adder 16, the logical operation unit 18 and to the first inputs of the control unit 19, the outputs of the adder 16 and the logical operation unit 18 are connected to the second and third inputs, respectively m control unit 19, which outputs are connected to second inputs of the seventh switch 7.

The processor includes two main devices: the control node 1 and the operational node 2.

The control node 1 coordinates the actions of the nodes of the operational node 2 with each other and with other computer devices, and also performs a set of operations including memory access commands. It generates control signals in a certain time sequence, under the action of which the required actions are performed in the nodes of the operational node 2.

Each such elementary action performed in the operating unit 2 during one clock period is called microoperation.

In certain clock periods, several microoperations can be performed simultaneously. This set of simultaneously executed

microoperation is called a microcommand, and the whole set of microcommands designed to solve a specific problem is called a microprogram.

The total time interval during which sampling, storage and conversion of one command into a set of control signals takes place is called the operation cycle of control unit 1.

Thus, the control node 1 converts the command into an appropriate set of control signals and provides:

reading a command located in the next memory cell;

decryption of the operation code (command);

finding operands (numbers) at the specified address contained in the command;

ensure the issuance of control signals to the operating unit to perform actions on them specified in the command operation code.

In this case, the firmware control unit 1 is used, in which the micro-commands are stored in the control memory 20.

In this case, the words representing the commands are stored in memory in sequentially numbered cells, which allows you to form the address of the next command by adding a unit to the address of the previous command, while the word consists of several parts: for example, an operation code indicating the type of operation and addresses of numbers, over which the corresponding operation should be made.

The decoder 3 operation code for the selected from the RAM command determines the number of the required firmware in the control memory 20.

The clock generator 4 is designed to generate clock and clock pulses.

The counter 9 commands is designed to generate the address of the memory cell of the next command, by natural sampling, i.e. adding to its contents a unit.

The register 11 addresses is designed to generate the address of the memory cell when the commands conditional or unconditional jump return.

The control unit 5 is designed to determine the address of the next microcommand in the control memory 20, generate the address of the next command (control the operation of the first switch 6), coordinate the work (issuing clock pulses) of the devices of the processor 1.

The control memory 20 is a permanent storage device and is designed to issue (depending on the operation code) the issuance of control signals (control signals, read signals, write signals, set signals to zero state) to the functional units of the processor. Moreover, the memory word contains information bits (for control signals) and control bits formed on the basis of the proposed coding method.

In this case, to form the values of the control bits of the control memory 20, information bits are represented as a two-line information matrix: ...

,

wherein:

1) a parity check is organized for each row of the information matrix;

2) right and left diagonal checks are carried out. The number of diagonal checks (the number of control bits of diagonal checks) is determined by the formula (parity bits are not transmitted):

R _D = k + 4.

Block 17 correction (figure 2) is designed to detect and correct errors that occur when reading information from

control memory 20. In this case, when reading the microcommands, the encoding circuit 40 generates (in the same way) the vector of control bits R ^{P of the} received code set.

Thus, during the information reading period, at the inputs of the comparison circuit 41, we have, respectively, the vectors of the control bits

The comparison circuit 41 is a bitwise comparison circuit and is intended to generate error syndrome values based on the transmitted and received information.

The result of adding, according to mod 2, the signal values of the transmitted and generated control bits will give an error syndrome:

E = e ₁ e ₂ e ₃ ......... e _{k + 4} .

The decoder 53 of the correction block 17 contains k + 4 inputs (the number of bits of the error syndrome) and L = l ₁ + l ₂ + l ₃ outputs (according to the number of matching circuits, which are k + 4 - input circuits I), where

- l ₁ - group of elements And (for various syndromes that characterize errors only in information bits;

- l ₂ - group of elements And (for various syndromes that characterize errors only in the control bits;

- l ₃ - group a group of elements And (for syndromes characterizing errors that occur simultaneously in the information and control bits.

In case of errors, a single signal is generated at one of its outputs

The outputs of the decoder 53 are combined into one output, respectively, using the first group of 42 OR elements, the second group of 43 OR elements, the third group of 44 OR elements, the fourth group of 45 OR elements, the fifth group of 46 OR elements, the sixth group 47

OR elements (from the second to third groups of OR elements are intended for generating control signals to the corrector 52, respectively, for the correction of the first, second ... k-th information bits).

The seventh group of 47 OR elements combines the outputs of the decoder 53, (the outputs of the circuits AND,) belonging to the subset l ₂ and corresponding to the occurrence of errors only in the control bits (for which the formation of control signals to the corrector 52 is not required).

The corrector 52 includes k-elements of ambiguity and is designed to correct errors that occur in the information bits of the control memory 20. When correcting errors, a function is implemented in mod2 relative to the control signals of the information bits of the control memory 20.

If errors occur that belong to a subset of n ₁ - for the same syndromes, indicating an error in different information bits (having the same meaning of the syndromes and additional checks, see the appendix), characterized by the presence of single values at the output of the first group of 42 OR elements and the absence of single values on outputs from the second 43 to the sixth group of 47 OR elements, using the seventh group of 48 OR elements, the second group of 42 OR elements, the element 49 NOT, the element 50 AND the signal 'Processor failure' is generated.

The operation node 2 is designed to perform arithmetic and logical operations and includes (Fig. 1) a shift counter 10, a number register 12, an ad register 13, an additional register 14, an additional code register 15, an adder 16, a logical operation block 18, a block 19 controls.

The counter 10 shifts is designed to count the number of shifts when performing operations of multiplication and division, the number of shifts of intermediate results and normalization.

The address register 11 is a memory register and is intended to store the address of the next command.

The 12th register is a memory register and is intended for storing operands when performing arithmetic and logical operations (storing the multiplicable when performing the multiplication and divisor when performing the division operation).

The register 13 of the adder (accumulator) is a shift register (to the right when performing the multiplication operation and to the left when performing the division operation), and is intended to store the divisible high order bits of the multiplication result.

Note that when performing the division operation, the control unit 5 analyzes the value of the sign discharge of the register 12 of the number and register 13 of the additional adder.

The additional register 14 is a shift register (to the right - when performing the multiplication operation and to the left - when performing the division operation), and is intended to store the multiplier and the least significant bits of the multiplication result when performing the multiplication operation and the division result when performing the division operation).

Note that when performing the multiplication operation, the control unit 5 analyzes the low-order value of the additional register 14.

The register 15 of the additional code is a memory register and is intended to store a negative number in the additional code (when performing the subtraction and division operations).

The adder 16 is a parallel n - bit adder and is designed to perform the operation of adding numbers.

Block 18 of logical operations is designed to perform logical operations AND, OR, NOT, summing mod2).

The control unit 19 (figure 3) is designed to detect and correct errors that occur when performing arithmetic and logical operations.

So, when performing an arithmetic operation, the result of the sum from the output of the adder 16, through the open second group of 71 AND elements, the second group of 58 OR elements is fed to the input of the second coding circuit 85 in which the values of the control bits relative to the received information are generated.

At the same time, the values of the control bits of the terms from the outputs 26 of the third switch 8 are fed to the inputs of the first group of 54 elements of ambiguity, where the summation of the same name control bits by mod2 is performed. At the same time, the values of the information bits of the terms go to the input 87 of the block 83 of the amendment shaper.

In this case, the values of information bits enter the input of the correction formation circuit when performing arithmetic operations (figure 4). Using groups of 92-97 AND elements, groups of 95-96 OR elements, the values of the transfer signals C _{i are formed} in accordance with the provisions discussed in the appendix. So, for example, when adding the number A = 0010 and the number B = 0110, a group of elements 93 opens and this leads to the formation of a transport signal C ₂ , and the presence of a single signal in the third category of one of the terms and the signal C ₂ leads to the opening of the 96 And element, which in turn leads to the appearance of a signal With ₃ . In the register 102 of the memory recorded values of the bits of the information matrix corrections. The transfer signal C ₂ corresponds to the information matrix:

and the transfer signal C ₃ corresponds to the information matrix:

Thus, the signals C _i determine the addresses of the bits of the information matrix corrections. The addition of the same-rank bits in mod2 on the group of 103 adders in mod2 will give the required information matrix of corrections.

Upon receipt of the enabling signal at input 86, the element 97 And opens and the received information goes to the outputs 89, 90 of the shaper 83 amendments (figure 3). At the same time, output 89 receives the values of the signals of the parity of the rows of the information matrix of amendments, and outputs 90 the values of the information bits of the information matrix of amendments A _Mtr . This information through the elements 59, 60 OR is fed to the inputs of the first coding circuit 84, where the right and left diagonal checks are organized.

As a result, we obtain the correction value: 1100 0110, which, upon a signal to the opening element 73 AND, is supplied to the first inputs of the second group of 55 elements of unequality.

For this example, the summation over mod2 of the values of the signals of the control bits of the first group of 54 elements of unequality will give the result:

which goes to the second inputs of the second group of 55 elements of disambiguation. As a result, at the output of the second group of 55 elements of ambiguity, we obtain the adjusted value of the control bits for the result of the sum:

which, with the correct summation of numbers A and B:

corresponds to the correct value of the control bits coming from the outputs of the second coding circuit 85 (10100101) to the first inputs of the third group 56 of unequal elements, the second inputs of which, through the element 62 OR receive the corrected values of the control bits 10100101.

If the values of the control bits coming from the outputs of the first coding circuit 84 coincide with the values of the control bits coming from the outputs of the second coding circuit 85, then at the output of the third group 56 of unequal elements we have zero values, i.e. summation operation is carried out correctly, if they do not match, an error has occurred.

The values of the signals from the outputs of the third group 56 elements of disambiguity are fed to the inputs of the decoder 81.

The decoder 81 contains k + 4 inputs (the number of bits of the error syndrome) and L = l ₁ + l ₂ + l ₃ outputs (according to the number of matching circuits, which are k + 4 - input circuits And), where

- l ₁ - group of elements And (for various syndromes that characterize errors only in information bits;

- l ₂ - group of elements And (for various syndromes that characterize errors only in the control bits;

- l ₃ - group a group of elements And (for syndromes characterizing errors that occur simultaneously in the information and control bits.

In case of errors, a single signal is generated at one of its outputs

The outputs of the decoder 81 are combined, respectively, in one output using the seventh group of 63 elements OR, the eighth group of 64

OR elements, the ninth group of 65 OR elements, the tenth (k-th) group of 66 OR elements, for generating control signals to the corrector, respectively, for correcting the first, second ... k-th information bits.

The eleventh group of 67 OR elements combines the outputs of the decoder 81, (the outputs of the circuits AND,) belonging to the subset l ₂ and corresponding to the occurrence of errors only in the control bits (for which the formation of control signals to the corrector is not required), from which the signal "Error in control bits" is removed - output 29 ₁ of the control unit 19.

In this case, the AND group of 74 elements is NOT closed through the element 78, and it is forbidden to output the values of the control bits to the output of the control unit 19, a decision is made to encode information bits by the encoding device when writing to the random access memory.

The corrector 82 includes k-elements of discontinuity and is intended to correct errors that occur in information bits.

When correcting errors, a function is implemented according to mod2 with respect to the control signals coming from the outputs of the OR elements:

If errors occur that belong to the subset n ₁ for the same syndromes, indicating an error in different information categories (having the same meaning of the syndromes and additional checks, see the appendix), characterized by the presence of single values at the outputs of the third group of 56 elements of ambiguity (twelfth group of 68 elements OR and the absence of unit values at the outputs from the seventh 63 to the eleventh 67 elements OR 13, using the thirteenth group of 69 elements OR, element 79 NOT, the eighth element 77 And form The 'Device Failure' signal is output, which is output 29 ₂ .

The absence of a signal at the outputs 29 ₁ , 29 ₂ and the presence of a signal at the output 29 ₃ indicates the presence of correctable errors in the information bits.

Thus, the signals of the information bits from the output of the adder 16 through the group of 61 OR elements are fed to the corrector 82. (if errors are corrected in them) and if there is an enable signal through the group of 75 AND elements together with the signals in the control bits (in the absence of errors ) go to the output of the control unit 19.

When monitoring the shift operations of the contents of the registers, the shaper 83 of the amendment implements the logic of the functional circuit of the formation of the amendment when performing the shift operation (Fig. 5).

Suppose you want to perform a shift operation to the right, the contents 1101 (results of private products) of register 13 of the adder, for which we have the following values of the control bits 11110000.

After performing the shift operation to the right and performing coding in the second coding scheme, we obtain a code set: s = 0110 00111001.

In this case, the bits of the correction matrix are formed according to the initial values of the information bits in accordance with the expressions presented in the appendix:

r ₄ = 0⊕u ₄ ; (0 is taken, since there is no transfer to the high order of the adder register) r ₃ = у ₄ ⊕у ₃ ; r ₂ = y ₃ ⊕y ₂ ; r ₁ = y ₂ ⊕y ₁ .

At the same time, at the first inputs of the elements 107, 108, 109, 110 And (Fig. 5) of the correction formation circuit when performing the shift operation to the right, we have the values of the signals, respectively, 1011, which when the control signal 86 _{1 is} shifted to the right through the elements 119, 120, 121 , 122 OR, and the supply of the enable signal to the elements 115, 116, 117, 118 And enter the outputs 89, 91 of the shaper 83 amendments. The information from the outputs 91 is fed to the shaper 80 which generates line parity bits

information matrix amendments. The values of the parity bits of the information matrix of the amendments and the values of the information bits of the matrix of corrections are supplied to the inputs of the first coding circuit 84.

After conducting diagonal checks at the output of the first encoder 84, we have the correction value: 1100 1001.

Having performed the addition operation by mod2 in the second group 55 of the initial value of the control bits with the correction value, we obtain the result:

which corresponds to the value of the control bits s obtained for the information bits after the shift operation.

If the values of the control bits generated by the first coding circuit 84 and the second coding circuit coincide, then the shift operation is performed correctly, if not, an error has occurred. In this case, the detection and correction of errors that occur is carried out in exactly the same way as when performing arithmetic operations.

If the shift operation to the right is performed for the additional register 14, then the transfer of the low-order value of the adder register 13 to the high-order bit of the additional register 14 is taken into account, i.e. functional diagram (figure 5) of the formation of the amendment when performing the shift operation implements the function:

r ₄ = y ₁ ^RG ⊕y ₄ ; r ₃ = y ₄ ⊕y ₃ ; r ₂ = y ₃ ⊕y ₂ ; r ₁ = y ₂ ⊕y ₁ .

When performing the shift operation to the left (when performing the division operation), the functional diagram for generating the correction when performing the shift operation implements the function: r ₄ = у ₄ ⊕у ₃ ; r ₃ = y ₃ ⊕y ₂ ; r ₂ = y ₂ ⊕y ₁ ; r ₁ = 0⊕у ₁ .

In this case, control signals are supplied to the inputs 86 ₂ , 86, then the circuit works in a similar way.

When performing a logical operation OR, the shaper corrections works as follows. Values of control bits of operands

are summed modulo in the first group of 54 adders in mod2, after which the result is fed to the first inputs of the second group of 55 adders in mod2, the second input of which receives the correction value. In this case, the functional diagram of the formation of the correction when performing the logical operation OR (Fig.6), for the formation of the information matrix of the correction, implements the logical function AND relative to the same bits of the operands.

So, for example, for the numbers A = 0101 01010101 and B = 0011 01101100, after performing the OR operation for information bits and adding the control bits of the terms under consideration in mod2, we obtain the code set 0111 00111001, for which the values of the control bits differ from the correct set of control bits 00001111 for the obtained value of information bits 0111.

In this case, the logical operations AND performed on the information bits of the operands under consideration on the elements 123, 124, 125, 126 AND (Fig.6) will give the result: 0001 (the operation AND is performed for the lower bits of the operands).

Then the matrix of corrections of the OR operation has the form:

the right and left diagonal checks of this matrix will give the result of the correction: 00110110.

Adding the summation result of the first group of 54 adders in mod2 with the correction value will give the correct value for the control bits:

If an error occurs, then its detection and correction is carried out as for the operations described above.

When performing the logical operation AND the shaper corrections works as follows. The values of the control bits of the operands are summed modulo in the first group of 54 adders by mod2, after which the result is fed to the first inputs of the second group of 55 adders by mod2, the second inputs of which receive the correction value. In this case, the functional diagram of the formation of the correction when performing the logical operation AND (Fig. 7), to form the information matrix of the correction, implements the logical function OR relative to the same bits of the operands on the group of logical elements 131, 132, 133, 134 OR. Further, the formation of the correction, the detection and correction of errors that occur is carried out in a similar way.

When monitoring the logical operation NOT, the formation of the correction is carried out by the functional diagram of the formation of the correction when the logical operation is NOT (Fig. 8), which generates the unit values of the information bits of the correction matrix based on the use of elements 148, 149, 150, 151, 152 AND, the values of the parity bits of the lines inverse matrix on the elements, respectively: 139, 140, 143 and 141, 142 144, their comparison with the current parity values of the parity bits received at inputs 88, outputting 89 values of information bits to the output (inputs of Group 59 elements tey OR) values and parity bits 90 to the output (input of the fourth group 60 elements OR). Further, the device operates in a similar manner.

When controlling the execution of the addition operation by mod2, it is not necessary to form an amendment to the result of summing, by mod2, the values of the control bits of the operands. In this case, the result of summing from the outputs of the first group of elements 54 of ambiguity through the third group of elements 72 AND, the sixth group 62 of elements OR comes to the moves of the third group 56 of elements of ambiguity, where it is compared with the values of the control bits generated at the outputs of the second coding circuit 85. Next, the device operates the same way.

The processor starts with the arrival of the Start signal at the input group of 30 inputs of the processor exchange device with peripheral units. By this command, block 5 issues a command to read the contents of the first memory cell from the control memory 20.

The "System Reset" command is located in the first memory cell, which sets the registers and blocks of the processor to the initial state. "1" is written to the 9 command counter, control device 1 issues micro-commands in the following sequence:

1) At the first clock, the microcommand signals and the values of the control bits are sent to the output of the correction unit 17, where the detection and correction of errors that occur is carried out in accordance with the functional diagram presented in figure 2.

In this case, when reading the micro-command by the encoding circuit 40, the control bit vector R ″ of the received code set is formed.

Thus, during the information reading period, at the inputs of the comparison circuit 41, we have, respectively, the vectors of the control bits

The comparison circuit 41 generates error syndrome values based on the transmitted and received information.

The result of adding, according to mod 2, the signal values of the transmitted and generated control bits will give an error syndrome:

E = e ₁ e ₂ e ₃ ......... e _{k + 4} .

In the event of errors, a single signal is generated at one of the outputs of the decoder 53.

In this case, the corrector 52 corrects errors that occur in the information bits of the control memory 20. When

error correction is implemented by the function mod2 relative to the control signals of the information bits of the control memory 20.

If errors occur that belong to the subset n ₁ - for the same syndromes, indicating an error in different information categories (having the same meaning of syndromes and additional checks, see the appendix), characterized by the presence of single values at the output of the first group of 42 elements OR 17 and the absence of single values at the outputs from the second 43 through the sixth group of 47 OR elements, using the seventh group of 48 OR elements, the second group of 42 OR elements, the NOT element 49, the 50 AND element, the signal 'Device failure' is generated.

Similarly, the correction unit 17 works when reading microcommands on all subsequent measures.

If there are no errors, or a correctable error has occurred, the set of microcommands is sent to the input of the counter reading of 9 commands and to the input of the address register 11, while the contents of the counter of 9 commands are sent to the address register 11 (or through the first switch 6 to the address inputs of the storage device with natural sample commands directly from the counter 9 teams);

2) On the second measure, the unit is added to the contents of the counter of 9 commands - the address of the next command is prepared;

3) At the third clock, the micro command signals are sent to the read input of the address register 11 and to the read input of the contents of the memory cell of the storage device at the specified address. In this case, the command stored in the first memory cell is recorded in the register 12 numbers;

4) At the fourth clock, the microcommand signals are fed to the read input of the 12th register, the input of the second switch 7, and to the input of the decoder 3 of the operation code, where they are decoded, after which the control unit 1 proceeds to the second stage of operation.

For example, consider the execution order of one of the commands written in the register on the 12th day after the first four measures.

Let the command for adding the contents of the register 13 of the adder with the number located in the storage device at the address specified in the address field of the register of the 12th number be written in the operation code field of the command for the contents of the 12th register. (when using a unicast command).

The control node 1 thus issues the following microcommands:

5) on the fifth clock, microcommand signals are fed to the read input of the 12th register, to the input of the second switch 7, the first switch 6, and to the write input of the address register 11 (the address stored in the 12th register is written to the address register 11, the contents of the 12th number register are reset );

6) At the sixth cycle, the microcommand signals are fed to the read input of address register 11, to the input of the first switch 6, to the read input of the storage device and to the write input of the 12th register (the second term is written from the storage device to the 12th register (we assume that the first term already in register 13 of the adder);

7) On the seventh cycle, the microcommand signals are fed to the read input of the number register 12 and the adder register 13, while the arithmetic-logic device performs the addition operation and writes the addition result to the adder register 13 as follows.

The result of the sum from the output of the adder 16 is sent to the control unit 19 (Fig. 3), in which, through an open second group of 71 AND elements, the second group of 58 OR elements is fed to the input of the second coding circuit 85 in which control bits are generated relative to the received information.

At the same time, the values of the control bits of the terms from the outputs 26 of the third switch 8 are supplied to the inputs of the first group of 54 elements

ambiguities, where summation of the same-named control bits by mod2 is performed. At the same time, the values of the information bits of the terms go to the input 87 of the block 83 of the amendment shaper.

In this case, the values of information bits enter the input of the correction formation circuit when performing arithmetic operations (figure 4). Using groups of 92-97 AND elements, groups of 95-96 OR elements, the values of the transport signals C _{i are formed} in accordance with the provisions considered in the appendix. So, for example, when adding the number A = 0010 and the number B = 0110, a group of elements 93 opens, and this leads to the formation of a transport signal C ₂ , and the presence of a single signal in the third category of one of the terms and the signal C ₂ leads to the opening of the 96 And element, which in turn leads to the appearance of a signal With ₃ . In the register 102 of the memory recorded values of the bits of the information matrix corrections. The transfer signal C ₂ corresponds to the information matrix:

and the transfer signal C ₃ corresponds to the information matrix:

Thus, the signals C _i determine the addresses of the bits of the information matrix corrections. The addition of the same-rank bits in mod2 on the group of 103 adders in mod2 will give the required information matrix of corrections.

Upon receipt of the enabling signal at input 86, the element 97 And opens and the received information goes to the outputs 89, 90 of the shaper 83 amendments (figure 3). In this case, output 89 receives the values of the signals of the parity of the rows of the information matrix

amendments, and from outputs 90 the values of the information bits of the information matrix of amendments A _Mtr . This information through the elements 59, 60 OR is fed to the inputs of the first coding circuit 84, where the right and left diagonal checks are organized.

As a result, we obtain the correction value: 1100 0110, which, upon a signal to the opening element 73 AND, is supplied to the first inputs of the second group of 55 elements of unequality.

For this example, the summation over mod2 of the values of the signals of the control bits of the first group of 54 elements of unequality will give the result:

which goes to the second inputs of the second group of 55 elements of disambiguation. As a result, at the output of the second group of 55 elements of ambiguity, we obtain the adjusted value of the control bits for the result of the sum:

which, with the correct summation of numbers A and B:

corresponds to the correct value of the control bits coming from the outputs of the second coding circuit 85 (10100101) to the first inputs of the third group 56 of unequal elements, the second inputs of which, through the element 62 OR receive the corrected values of the control bits 10100101.

If the values of the control bits coming from the first coding circuit 84 coincide with the values of the control bits coming from the outputs of the second coding circuit 85, then at the output of the third group 56 of unequal elements we have zero values, i.e. summation operation is carried out correctly, if they do not match, an error has occurred.

The values of the signals from the outputs of the third group 56 elements of disambiguity are fed to the inputs of the decoder 81.

In case of errors, a single signal is formed at one of its outputs.

The outputs of the decoder 81 are combined into one output, respectively, using the seventh group of 63 OR elements, the eighth group of 64 OR elements, the ninth group of 65 OR elements, the tenth (k-th) group of 66 OR elements, to generate control signals to the corrector, respectively, to correct the first , the second ... k-th information category.

The eleventh group of 67 OR elements combines the outputs of the decoder 81, (the outputs of the circuits AND,) belonging to the subset 1 ₂ and corresponding to the occurrence of errors only in the control bits (for which the formation of control signals to the corrector is not required), from which the signal "Error in control bits" is removed - output 29 ₁ of the control unit 19.

In this case, the AND group of 74 elements is NOT closed through the element 78, and it is forbidden to output the values of the control bits to the output of the control unit 19, a decision is made to encode information bits by the encoding device when writing to the random access memory.

The corrector 82 includes k-elements of discontinuity and is intended to correct errors that occur in information bits.

When correcting errors, a function is implemented according to mod2 with respect to the control signals coming from the outputs of the OR elements:

If errors occur that belong to the subset n ₁ for the same syndromes, indicating an error in different information categories (having the same meaning of the syndromes and additional checks, see the appendix), characterized by the presence of single values at the outputs of the third group of 56 elements of ambiguity (twelfth group of 68 elements OR and the absence of unit values at the outputs from the seventh 63 to the eleventh 67 elements OR 13, using the thirteenth group of 69 elements OR, element 79 NOT, the eighth element 77 And form The 'Device Failure' signal is output, which is output 29 ₂ .

The absence of a signal at the outputs 29 ₁ , 29 ₂ and the presence of a signal at the output 29 ₃ indicates the presence of correctable errors in the information bits.

Thus, the signals of the information bits from the output of the adder 16 through the group of 61 OR elements are fed to the corrector 82. (if errors are corrected in them) and if there is an enable signal through the group of 75 AND elements together with the signals in the control bits (in the absence of errors ) go to the output 28 of the control unit 19 and then through the second switch 7 go to the register 13 of the adder.

Similarly, the processor operates when performing logical operations.

8) On the eighth step, the micro-command “End of operations” is issued, the transition to the next operation is carried out, the control unit 5 is initialized and gives permission to start the next command, the address of which is indicated in the counter of 9 commands.

ANNEX 1.

1. A method of protecting computer storage devices

Correction of errors of a given multiplicity, provided that errors are detected in the remaining bits of information, can be achieved based on an iterative code.

The procedure for constructing a two-dimensional iterative code is as follows [3]. A given set of information symbols is divided into groups (blocks, modules) of information, by b - bits in each group. The resulting information modules are presented in the form of an information matrix (1):

Then the information is encoded using the parity method (by adding mod2 to the characters of the rows and columns of the resulting matrix). As a result, we have a two-dimensional iterative code that allows us to detect and correct any single error:

where H = h ₁ , h ₂ , ..., h _m is the line parity vector; Z = z ₁ , z ₂ , ..., z _b is the column parity vector. The parity vectors of rows and columns form the set of control bits R ₁ = {r ₁ , r ₂ , r _m , r _{m + 1} , ..., r _b }. Upon receipt of a code combination with respect to information bits, the values of the control bits are re-formed . In this case, the difference between the transmitted values of the control bits and received after receiving the information forms the error syndrome E:

Moreover, the bits of the error syndrome e ₁ e ₂ ... e _m (obtained with respect to the row parity vector) indicate the module of information that has an error, and the bits e _m e _{m + 1} ... e _b (obtained with respect to the column parity vector) indicate erroneous bit in the information module.

Since code combinations of rows and columns have a minimum distance d = 2, the minimum distance of this code is d = 4. This code allows you to correct any single error and detect a significant proportion of multiple errors.

The structures of errors not detected by the two-dimensional iterative code are shown in the figure:

Fig. 1 Structures of errors not detected by a two-dimensional iterative code: a) errors of multiplicity 4; b) - errors of multiplicity 6.

Fig.2 Error structures of a two-dimensional iterative code, leading to erroneous correction: a) errors of multiplicity 5; b) - errors of multiplicity 7.

In the general case, iterative codes of higher dimension can be constructed (three-dimensional, four-dimensional, etc.), where each

an information symbol will be a component of simultaneously x different codewords. The parameters of iterative codes of dimension x are as follows [3]:

where n _i , k _i , d _i are the length, the number of information bits, the minimum distance of the code sets of rows and columns, respectively.

Based on this, to build iterative codes should use checks that have the highest detecting ability.

Thus, the organization of diagonal checks of the matrix under consideration will allow us to identify error structures that are not detected by iterative code that implements parity checks of rows and columns.

The structure of diagonal checks that detect the errors in question has the form shown in Fig. 3.

Fig. 3. Diagonal check structure:

- the results of the right diagonal checks; - results of left diagonal checks

Left diagonal checks are formed according to the rule:

The results of the right diagonal checks are formed by summing the values of the following information bits:

In this case, the total number of diagonal checks is 2l, or:

Example 1. Let the word in question consists of four information bits that have zero meanings. For this code set, the information matrix has the form:

In this case, the parity checks of the rows and columns of the information matrix will give zero values and, in addition, the results of all right and left diagonal checks will have zero values. If an error occurs in all information bits, we have an even error that cannot be detected by a two-dimensional iterative code, because parity checks of rows and columns of the information matrix have zero values:

At the same time, the right and left diagonal checks will give a result of 101.

Proposition 1. An iterative code that implements right and left diagonal checks detects all even errors not detected by the two-dimensional iterative code and identifies odd errors perceived by the two-dimensional iterative code as being correctable.

In turn, there are error structures that are not detected by iterative code that implements right and left diagonal checks and checks for the parity of rows and columns. The structures of the considered errors are presented in Fig. 4.

Fig. 4 Error structures not detected by diagonal checks and checks of rows and columns.

So, for example, with respect to the information matrix having zero values, the following error structure will not be detected by diagonal checks.

In order to exclude the occurrence of the considered errors, the information matrix should contain no more than two rows.

Proposition 2. For the information matrix bx2, an iterative code that implements right and left diagonal checks detects the maximum number of possible errors (with the exception of the set 2 ^k -1 forbidden code sets that are transformed into allowed code sets).

Thus, when using iterative code that implements right and left diagonal checks, the code set is transmitted in the form:

For this example, the encoding of information is as follows: r ₁ = y ₁ ; r ₂ = y ₂ ⊕y ₃ ; r ₃ = y ₄ ; r ₄ = y ₃ ; r ₅ = y ₁ ⊕y ₄ ; r ₆ = y ₂ .

The result of the addition of the values of the signals of the control bits transmitted and received will give an error syndrome:

where the bits of the error vector r ₁ , r ₂ , ............ r _l - correspond to the right diagonal check, r _l , r _{l + 1} , ............ r _2l - left and formed relative to the received information bits;

- the values of the received control bits.

Property 1. There are such error configurations in information and control bits for which the error syndromes have the same meanings.

To distinguish these errors, when generating the values of the error syndromes, additional diagonal checks are organized:

Thus, each error from the set of errors M = (2 ⁿ ) k can be associated with the value of the error syndrome and the value of additional diagonal checks.

Property 2. Each set of values of the error syndrome and the value of additional checks corresponds to a subset of Q-errors of various configurations.

Corollary 1. To distinguish between errors belonging to this subset, it is necessary to limit the multiplicity of correctable errors and increase the number of control bits (perform additional coding of information bits).

In this regard, the proposed encoding method includes the following provisions:

1) in order to ensure the correction of about 50% of the errors that occur, it is advisable to limit to the correction of errors whose multiplicity does not exceed k-1;

2) for each row of the information matrix, a parity check is organized, i.e. the information matrix is presented in the form:

3) for the obtained information matrix, right and left diagonal checks are organized. The number of diagonal checks (the number of control bits of diagonal checks) is determined by the formula:

4) the code set is transmitted in the form:

5) the result of adding the signal values of the transmitted and generated control bits will give an error syndrome:

6) when the error syndrome is formed with respect to the received and generated values of the control bits, additional diagonal checks are organized, the number of which is determined by the expression:

7) as a result, we have many errors of a given multiplicity (in this case, from single to multiplicity k-1, defined by the expression: ) characterized by a certain value of the error syndrome and additional verification.

8) the set N is divided into four subsets N = n ₁ + n ₂ + n ₃ + n ₄ ,

Where

n ₁ - syndromes having the same additional checks (uncorrectable errors, a sign of device failure);

n ₂ - a subset of groups (each group includes 2 ^k - the same values of the syndromes) in the presence of errors only in information bits;

n ₃ - a subset of groups (each group includes 2 ^k - the same values of the syndromes) in the presence of errors only in the control bits;

n ₄ - a subset of groups (each group includes 2 ^k - the same values of the syndromes) in the presence of errors simultaneously in the information and control bits.

Note that for errors not exceeding the multiplicity k-1 there are no erroneous code sets that can be transformed into allowed (serviceable) code sets.

Based on the obtained coding rules, a decoding strategy is formed that solves the problem of distinguishing errors in information and control bits and the rules for correcting errors that arise, which includes the following points:

1) identical additional checks are revealed, according to which error syndromes belonging to the subset n ₁ are excluded from the set N (uncorrectable errors are detected for which the "Device failure" signal is generated);

2) groups of identical syndromes (indicating an error in the corresponding information bits) are determined for the subset n ₂ ;

3) groups of error syndromes belonging to a subset of n _{3 are} determined for which correction of information bits is not required;

4) groups of the same values of the error syndromes belonging to the subset n ₄ and that allow correcting errors in the corresponding information bits are revealed.

For the considered example that implements the proposed encoding method, we have:

- total number of errors - 4768

- the number of identical error syndromes having the same additional checks (subset n ₁ ) - 2544 (the number of detected errors);

- 2224 - the number of correctable errors (46%);

- the number of errors only in information categories is 224 (l ₁ = 14 - groups, each of which includes 16 identical syndromes);

- the number of errors only in the control categories - 592 (l ₂ = 37 - groups, each of which includes 16 identical syndromes);

- the number of errors having distortions simultaneously in the information and control bits is 1408 (l ₃ = 88 - groups, each of which includes 16 identical syndromes).

Table 1 shows a part of the values of the error syndromes for the subsets n ₂ , n ₃ , n ₄ . (excluded are the syndromes of errors of the subset n ₁ having the same values of additional checks).

TABLE 1. MISTAKE Inf. bit Accepted by the Kyrgyz Republic Formed. KR Syndrome _{1 1 2 2 3 4} r ₁ r ₂ r ₃ r ₄ r ₅ r ₆ r ₇ r ₈ r ₉ r ₁₀ r ₁ r ₂ r ₃ r ₄ r ₅ r ₆ r ₇ r ₈ r ₉ r ₁₀ e ₁ e ₂ e ₃ e ₄ e ₅ e ₆ e ₇ e ₈ e ₉ e ₁₀ Only in control Information only Both in control and in information

The proposed encoding method allows you to:

Correct an error of a given multiplicity;

detect the maximum number of errors (with the exception of erroneous code sets that are transformed into allowed code sets);

signal a malfunction of the memory device when an uncorrectable error occurs.

2. A method for detecting errors converters information

2.1. General Provisions

According to their functional purpose, discrete computer devices can be conditionally divided into information storage devices (storage device, number register, buffer memory registers, etc.) and information converters (adders, shift registers and other discrete nodes of the operating and control computer devices).

Currently, the most widely used correction codes are used to ensure fault tolerance of information storage and transmission devices; at the same time, methods for using correction codes to ensure fault tolerance of information converters are not sufficiently developed.

As the simplest method of monitoring the operation of the adder can be used for parity [4]. When adding the numbers a and b, the digits of the sum s are formed in accordance with the expressions:

Adding all n of the above equalities modulo 2, we obtain:

p _s = p _a ⊕p _b ⊕p _s ,

where p _s is the parity of the sum; p _a , p _b - the parity of the terms; p _c - parity of transfers. This control scheme allows you to detect only single and odd number of errors, in addition, errors in the transfer chain are not detected, since this leads to an even number of errors - in the transfer discharge and in the discharge category.

The operation of the adders can be controlled using duplication or paraphase logic, however, this requires high hardware costs, which does not allow to provide the required reliability of the operation of these devices.

Using the method of protection of information storage devices discussed above to detect the maximum number of errors that occur in information converters allows us to most fully satisfy the above requirements, but there is a need to address a number of issues related to adapting this encoding method to the functional and design features of these devices.

2.2. Adder operation control

Parallel-action adders, in which the transmission of numbers and the formation of the sum occurs simultaneously for all digits, have a predominant distribution in modern computers.

Consider the main provisions of the method of controlling the operation of addition by example.

Suppose you want to add two four bit numbers:

A = 0111 and B = 0011, which are stored in fault-tolerant RAM, i.e. encoded by the considered method.

In this case, the information matrix for the number A has the form:

the right column of which contains the values of the bits of the parity check of the rows of the information matrix.

Accordingly, the right and left diagonal checks of the information matrix will give the result:

0000 1111.

Thus, from RAM to the operating device of the processor, the number A comes in the form: 0111 0000 1111.

The information matrix of the number B has the form:

the number B is fed to the input of the adder in the form:

0011 01101100.

Arithmetic summation of information bits will give the result:

The information matrix S _M has the form:

accordingly, the right and left diagonal checks of the information matrix will give the signal values in the control bits: 11111111.

Thus, as a result of the addition operation, the code set should be generated at the output of the arithmetic device: 1010 11111111.

However, the arithmetic addition of the control bits of the terms will give the result:

which differs from the correct value: 11111111.

Similarly, the addition of control bits of the terms in mod 2 will give the result:

which is also different from the correct value.

In this regard, for the formation of the correct values of the control bits, it becomes necessary to determine the correction, for example, to the value of the control bits S _{k mod2} .

The rules for the formation of the amendment can be obtained by constructing information matrices that take into account the transfer of a unit to the senior level, if there are units in the same category.

Property 3. With the simultaneous presence of units in the lowest information bits of the terms and the absence of a transfer chain in the remaining bits, the correction value is: C ₁ = 01011010, which is obtained as a result of arithmetic addition of the numbers A ₁ = 0001, B ₁ = 0001, the formation of the information matrix from the result 0010:

and coding this matrix by conducting right and left diagonal checks: 01011010.

Property 4. With the simultaneous presence of units in the second digits of the terms and the absence of a transfer chain (the presence of units in the same digits of the terms or the presence of a unit in the considered digit of one of the terms and the transfer of the transfer from the least significant bit to this category) in the remaining digits, the correction is based on the information matrices:

and is equal to: C ₂ = 01100011.

Property 5. With the simultaneous presence of units in the third digits and the absence of a transfer chain in the remaining digits, the amendment

the amendment is formed on the basis of the information matrix:

and is equal to: C ₃ = 10100101.

For the considered example, with the simultaneous presence of units in the fourth digits of the terms, the correction value is not given, since the presence of units in the fourth digits of the terms leads to overflow of the bit grid.

Property 5 If there is a transfer chain in the first and second digits of the terms, the correction value is equal to:

or it is obtained on the basis of the information matrix A _M4 , formed on the basis of addition by mod2 of the same digits of the information matrices AM ₁ and A _M2 :

Property 6 If there is a transfer chain in the first and third digits of the terms, the correction value is equal to:

or it is obtained on the basis of the information matrix A _M5 , formed on the basis of addition by mod2 of the same digits of the information matrices A _M1 and A _M3 :

Property 7 If there is a transfer chain in the second and third digits of the terms, the correction value is equal to:

or based on information matrices A _M2 and A _M3 :

Property 8. If there is a transfer chain in the first, second, and third digits of the terms, the correction value is equal to:

or based on information matrices A _M1 , A _M2, and A _M3 .

Property 9. In the absence of a transfer chain in the information bits (the absence of units in the equivalent bits of the terms), the correction value is: 0000 0000.

For the example under consideration (the addition of the numbers A = 0111 and B = 0011), a correction of C ₇ = 1001 110 is required.

Then, mod2 addition of the values of the control bits of these terms and the correction will give the result:

which corresponds to the correct value of the control digits for the result of the sum S = 1010 obtained as a result of arithmetic addition of numbers A = 0111 and B = 0011.

The proposed method allows you to control the operation of the ALU adder and at the same time allows you to:

detect the maximum number of errors (with the exception of errors that are transformed into allowed code sets);

to correct the erroneous operation of the adder (information bits) according to the generated values of the control bits (the frequency of the error to be corrected to k-1) according to the rules for correcting memory errors;

detect and correct errors of arbitrary configuration in the control bits (control bits received as a result of encoding the result of the sum are transmitted);

signal the occurrence of uncorrectable errors.

2.3 Control operation of addition by mod2

Consider the main points of the method for controlling the addition operation by mod2 using an example.

Suppose you want to add two four bit numbers:

A = 0101 and B = 0011, which are stored in fault-tolerant RAM, i.e. encoded by the considered method.

In this case, from RAM to the operating device of the processor, the number A comes in the form of a code set: 0101 0101 0101, And the number B comes in the form: 0011 0110 1100.

When performing the addition operation on mod2 of information and control bits of the considered terms, we obtain the code set 0110 0011 1001.

The information matrix of the result has the form:

the right and left diagonal checks of this matrix will give the result: 00111001, which allows us to formulate property 10.

Property 10. The result of adding modulo control bits of terms according to mod2 corresponds to the result of adding mod2 information bits of the terms being considered.

This property allows you to control the addition operation by mod2 and at the same time detect and correct errors that occur according to the rules of the proposed encoding method.

2.4. Shear control

Consider the main provisions of the method of controlling the shift operation on the example of a code set: 0111 0000 1111

Let it be required to carry out a shift operation to the right by one bit, as a result we obtain a code set: 0011.

The information matrix of the result has the form:

the right and left diagonal checks of this matrix will give the result: 01101100, which differs from the initial set of control bits 00001111.

In this regard, it becomes necessary to formulate an amendment to the original code set, which allows one to obtain a set of control bits corresponding to the value of information bits obtained by shifting to the right. To this end, we construct a matrix of corrections for a shift to the right, the digits of which are formed as follows: r ₄ = 0⊕у ₄ ; (0 if one unit from another register is not transferred to the high order; otherwise, r ₄ == y ₁ ⁱ ⊕у ₄ , where y ₁ ^{i is the} value of the transfer signal from another register, for example, to the high order of the register from the adder multiplication operations) r ₃ = у ₄ ⊕у ₃ ; r ₂ = y ₃ ⊕y ₂ ; r ₁ = y ₂ ⊕y ₁ .

For this example, we get the code set: 0100.

In this case, the matrix of corrections when shifting to the right has the form:

.

When coding this matrix by the proposed method, we obtain the correction value: 01100011.

Adding mod2 to the original value of the control bits with the correction value will give the correct value of the control bits when shifting the information bits to the right:

When the information bits are shifted to the left, the bits of the correction matrix are formed as follows: r ₄ = у ₄ ⊕у ₃ ; r ₃ = y ₃ ⊕y ₂ ; r ₂ = y ₂ ⊕y ₁ ; r ₁ = 0⊕у ₁

For the considered example, we obtain the values of the digits of the matrix of corrections when shifting to the left: 1001, respectively, the matrix of corrections when shifting to the right has the form:

The right and left diagonal checks of this matrix will give the result: 10010011.

When mod2 is added to the initial set of control bits and the correction value, we obtain the result:

which corresponds to the value of information bits shifted to the left.

Indeed, when shifting the information bits of the considered example, we have: 1110.

Accordingly, the matrix of information bits looks like:

for which we have a set of values of control bits: 10011100.

Property 11. Adding mod2 to the original value of the control bits with the correction value when shifting to the right (left) will give the correct value of the control bits when shifting the information bits.

This property allows you to control the shift operation and at the same time detect and correct errors that occur according to the rules of the proposed encoding method.

2.5. Monitoring the logical operation OR

Consider the main provisions of the method of controlling the operation OR by example.

Suppose you want to perform a logical OR operation with respect to two four bit numbers:

A = 0101 and B = 0011, which are stored in fault-tolerant RAM, i.e. encoded by the considered method.

In this case, from RAM to the operating device of the processor, the number A comes in the form of a code set: 0101 01010101, and the number B comes in the form: 0011 01101100.

When performing the OR operation for information bits and adding the control bits of the terms under consideration in mod2, we obtain the code set 0111 00111001, in which the values of the control bits differ from the correct set of control bits for the obtained value of information bits 0111.

To form the correction, we construct the correction matrix using the logical AND operation with respect to the information bits of the operands under consideration, as a result we obtain the code set: 0001 (the AND operation is performed for the lower bits of the operands).

In this case, the matrix of corrections of the OR operation has the form:

the right and left diagonal checks of this matrix will give the result of the correction: 00110110.

Property 12. The addition operation in mod2 of the obtained values of the control bits and the correction value generated on the basis of the matrix of corrections for the logical OR operation will give the correct value of the control bits.

Indeed, for the considered example, we have the result:

which is correct for code set 0111, obtained as a result of the logical OR operation, which allows you to control the OR operation and at the same time detect and correct errors that occur according to the rules of the proposed encoding method.

2.6. Monitoring the execution of a logical operation AND

Consider the main provisions of the method of controlling the operation And on an example.

Suppose you want to perform the logical operation AND for two four bit numbers:

A = 0101 and B = 0011, which are stored in fault-tolerant RAM, i.e. encoded by the considered method.

In this case, from RAM to the operating device of the processor, the number A comes in the form of a code set: 0101 01010101, and the number B comes in the form: 0011 01101100.

When performing the And operation for information bits and addition of the control bits of the operands in question mod2, we obtain the code set 0001 00111001, in which the values of the control bits differ from the correct set of control bits 00110110 for the obtained value of the information bits 0001.

To form the correction, we construct the correction matrix using the logical OR operation relative to the information bits of the operands under consideration, as a result we obtain the code set: 0111.

In this case, the correction matrix of the operation And has the form:

the right and left diagonal checks of this matrix will give the result of the correction: 00001111.

Property 13. The operation of adding, by mod2, the obtained values of the control bits and the correction value generated on the basis of the correction matrix for the logical operation AND, will give the correct value of the control bits.

Indeed, for the considered example, we have the result:

which is correct for code set 0001, obtained as a result of the logical operation AND, which allows you to control the operation AND and at the same time detect and correct errors that occur according to the rules of the proposed encoding method.

2.7. Logical operation control is NOT

Consider the main provisions of the method of controlling the inversion operation by example.

Suppose you want to perform a logical operation NOT for four bit numbers: A = 0101 which are stored in fault-tolerant RAM and encoded by the method considered.

In this case, from RAM to the operating device of the processor, the number A comes in the form of a code set: 0101 01010101.

The information matrix of the initial number A has the form:

When performing the operation NOT for information bits, we obtain a code set 1010 01010101, for which the values of the control bits differ from the correct set of control bits 11111111 for the obtained value of information bits 1010. Accordingly, the information matrix constructed of the relative inverse value of the number has the form:

To form the correction, we use the correction matrix for the logical operation NOT, which is obtained by adding mod2 of the same digits of the original information matrix and the information matrix constructed with respect to the inverse value of the original number. As a result, we have:

Note: The rightmost column of the correction matrix for a logical operation is NOT the result of adding mod2 bits of the parity check of the original and inverse information matrices. For matrices containing four information bits (in this case), this column always has zero values, which is not typical for matrices of higher dimension. At the same time, the remaining columns of the considered matrix in their digits always have only unit values.

The right and left diagonal checks of this matrix will give the result of the correction: 10101010.

Property 13. The addition operation in mod2 of the obtained values of the control bits and the correction value generated on the basis of the correction matrix for the logical operation NOT gives the correct value of the control bits.

Indeed, for the considered example, we have the result:

which is correct for the code set 1010 obtained as a result of the logical operation NOT, which allows you to control the operation NOT and at the same time detect and correct errors that occur according to the rules of the proposed encoding method.

The proposed method allows you to control the processor and at the same time allows you to:

detect the maximum number of errors (with the exception of errors that are transformed into allowed code sets);

Correct erroneous operation of the processor when performing arithmetic and logical operations;

detect and correct errors of arbitrary configuration in the control bits (control bits obtained as a result of encoding the results of operations are transmitted);

signal the occurrence of uncorrectable errors.

INFORMATION SOURCES

1. Patent for invention No. 2210805 according to application 99111190/09 dated 05/31/09, authors: Tsarkov A.N., Bezrodny B.Yu., Novikov N.N., Romanenko Yu.A., Pavlov A.A.

2. Kalabekov B. A., Microprocessors and their use in signal transmission and processing systems, M.: Radio and communications, 1988, 368 S. (p. 30, fig. 1.3).

3. Khetagurov Y. A. Rudnev Yu.P. Improving the reliability of digital devices using redundant coding methods. M .: Energy, 1974, 270 p.

4. Orlov I.A., Kornyushko V.F., Burlyaev V.V. Operation and repair of computers, organization of the computer center. M .: Energoatomizdat, 1989, 400 p.

Claims (8)

1. A fault-tolerant processor of increased reliability of operation, comprising a control unit, an operating unit, the first inputs of the control unit are processor inputs, a second group of inputs of the control unit is connected to the first outputs of the operation unit, the outputs of the control unit are connected to the first inputs of the operation unit, the second inputs of which are inputs data, and the second outputs are data outputs, characterized in that it further comprises an operation code decoder, a clock, a block control, first switch, second switch, third switch, command counter, shift counter, address register, number register, adder register, additional register, additional code register, adder, correction block, logical operation block, control memory, control unit, including shaper amendment, which in turn contains a functional diagram of the amendment when performing arithmetic operations, a functional diagram of the formation of the amendment when performing the shift operation, a functional diagram forming an amendment when performing the OR operation, a functional diagram of forming an amendment when performing an AND operation, a functional diagram of generating an amendment when performing an operation NOT, the inputs of the exchange device are connected to the first input of the control unit and to the first inputs of the second switch, the second inputs of which are connected to the outputs of the storage device, the first outputs of the second switch go to the input of the exchange device, the second outputs go to the input of the storage device, and the third outputs are connected respectively but to the first inputs of the command counter, shift counter, number register, adder register, additional register, additional code register, to the inputs of the operation code decoder, to the second inputs of the control unit, to the first input of the first switch, the first output of which is connected to the first input of the address register , the third input of the control unit is connected to the outputs of the operation code decoder, the fourth input is connected to the outputs of the clock generator, and the fifth input is connected to the first output of the control memory, the first output of the block the control is connected to the control memory input, the first outputs of which are connected to the first inputs of the correction unit, the second output of the control unit is connected to the second input of the first switch, the third and fourth inputs of which are connected respectively to the outputs of the address register and command counter, and the cell address is removed from the second output the memory of the storage device, the third output of the control unit is connected respectively to the second inputs of the correction unit, to the second inputs of the instruction counter, shift counter, address register, number register a, the adder register, the additional register, the additional code register, to the first group of inputs of the third switch and to the third group of inputs of the second switch is the output of the clock pulses, the first output of the correction unit is connected to the fourth input of the second switch, and the second, third, fourth and fifth outputs correction blocks are connected respectively to the third, fourth fifth and sixth inputs of the command counter, shift counter, address register, number register, adder register, additional register, additional register body code, to the first group of inputs of the third switch, to the third group of inputs of the second switch and are the outputs of control signals, read signals, write signals, signals to set the devices to zero, the outputs of the number register, adder register, additional register, additional code register are connected to the second inputs of the third switch and the fifth inputs of the second switch, the output of the shift counter is connected to the sixth inputs of the second switch, the first and second outputs of the third switch under are connected respectively to the inputs of the adder, the logical operations unit, and the third outputs are connected respectively to the first and second inputs of the control unit, to the first and second inputs of the correction driver, to the first and second inputs, respectively, of the correction correction functional circuit when performing arithmetic operations, the correction correction functional diagram when performing the shift operation, the functional diagram of the formation of the amendment when performing the operation OR, the functional diagram of the formation of the amendment when performing walkie-talkie And, a functional circuit for generating corrections during the operation NOT, the outputs of the adder and a block of logical operations are connected respectively to the third and fourth inputs of the control unit, the first outputs of a functional circuit for generating corrections when performing arithmetic operations, a functional circuit for generating corrections when performing a shift operation, a functional circuit the formation of the amendment during the operation OR, functional diagram of the formation of the amendment during the operation AND, the functional circuit ph corrections during the operation are NOT the first outputs of the corrector and are connected to the fifth input of the control unit, the second outputs of the correction corrector during the operation are NOT the second outputs of the corrector and are connected to the sixth input of the control unit, the second outputs of the corrections when arithmetic operations, the functional diagram of the formation of the amendment when performing the shift operation, the functional diagram of the formation of the amendment during the operation OR, the functional circuit for generating corrections during the operation AND are the third outputs of the amendment driver and are connected to the seventh input of the control unit, the first and second outputs of the control unit are connected to the seventh inputs of the second switch, and the third outputs are connected to the third input of the amendment and, respectively to the second input of the functional diagram of the formation of the amendment when performing operation NOT. 2. The fault-tolerant processor with increased reliability of operation according to claim 1, characterized in that the correction unit comprises a coding circuit, a comparison circuit, a first group of OR elements, a second group of OR elements, a third group of OR elements, a fourth group of OR elements, a fifth group of OR elements, the sixth group of OR elements, the seventh group of OR elements, the NOT element, the first group of AND elements, the second group of AND elements, the corrector, the decoder, the first outputs of the control memory are connected to the first inputs of the corrector and I encode the inputs circuit, the outputs of which are connected to the first inputs of the comparison circuit, the second inputs of the comparison circuit are connected to the second outputs of the control memory, and the outputs are connected to the inputs of the decoder and to the inputs of the first group of OR elements, the outputs of which are connected to the first input of the first AND element, the outputs of the decoder are combined into groups, respectively, by a second group of OR elements, a third group of OR elements, a fourth group of OR elements, a fifth group of OR elements, a sixth group of OR elements, outputs from the second to fifth group of OR elements And connected from the first to fourth input of the seventh group of OR elements and from first to fourth input of the second group of AND elements, the fifth input of which is connected to the enable input, and the outputs are connected to the second inputs of the corrector, the output of the sixth group of OR elements is connected to the fifth input of the seventh group of elements OR, the output of which through the element is NOT connected to the second input of the first element AND, the output of the first element AND is the output "Processor failure", the corrector outputs are the outputs of the control signals. 3. The fault-tolerant processor of increased reliability of operation according to claim 1, characterized in that the control unit comprises a first group of disambiguity elements, a second group of discontinuity elements, a third group of discontinuity elements, a first group of OR elements, a second group of OR elements, a third group of OR elements, a fourth group of OR elements, fifth group of OR elements, sixth group of OR elements, seventh group of OR elements, eighth group of OR elements, ninth group of OR elements, tenth group of elements OR, the eleventh group of OR elements, the twelfth group of OR elements, the thirteenth group of OR elements, the first group of AND elements, the second group of AND elements, the third group of AND elements, the fourth group of AND elements, the fifth group of AND elements, the sixth group of AND elements, the seventh group of elements And, the eighth group of elements AND, the first element is NOT, the second element is NOT, a shaper, a decoder, a corrector, a first coding circuit, a second coding circuit, a shaper, the first inputs of the shaper, the second inputs of the shaper equal, the third inputs of the amendment driver, the first outputs of the amendment driver, the second outputs of the amendment driver, the third outputs of the amendment driver, the first outputs of the third switch are connected to the first inputs of the first group of AND elements, the second group of AND elements, the third group of AND elements, the fourth group of AND elements , the sixth group of elements And, the seventh group of elements And, to the first input of the shaper amendments and, accordingly, to the first inputs, the second outputs of the third switch are connected to the second inputs the corrector of the correction and to the inputs of the first group of elements of disambiguation, the outputs of which are connected to the third inputs of the block of formation of the amendment, to the second inputs of the third group of elements of And and the first inputs of the second group of elements of disambiguation, the first outputs of the shaper of the amendment are connected to the inputs of the third group of elements OR, the outputs of which connected to the first inputs of the first coding circuit, the second outputs of the correction driver are connected to the first inputs of the fourth group of OR elements, the second inputs of which are connected to the output m of the shaper, and the outputs are connected to the second inputs of the first coding circuit, the third outputs of the correction shaper are connected to the inputs of the shaper, the outputs of the first coding circuit are connected to the second inputs of the fourth group of AND elements, the outputs of which are connected to the second inputs of the second group of unequal elements, the first inputs of the sixth group disambiguation elements are connected to the outputs of the third group of AND elements, the outputs of the second group of disambiguation elements are connected to the second inputs of the sixth group of OR elements, the outputs to otoroy connected to the first inputs of the third group of elements of disambiguation, the outputs of the block of logical operations are connected to the inputs of the first group of elements OR, the outputs of which are connected to the second inputs of the first group of elements AND, the outputs of the first group of elements AND are connected to the first inputs of the second group of elements OR and to the first inputs of the fifth group of OR elements, the outputs of the adder are connected to the second inputs of the fifth group of OR elements and to the second inputs of the second group of AND elements, the outputs of which are connected to the second inputs of the second group element OR, the outputs of the second group of OR elements are connected to the inputs of the second coding circuit, the outputs of which are connected to the first inputs of the fifth group of AND elements and to the second inputs of the third group of disambiguation elements, the outputs of which are connected to the inputs of the twelfth group of OR elements and to the inputs of the decoder, the first group the decoder outputs are connected to the inputs of the seventh group of OR elements, the outputs of which are connected to the second inputs of the seventh group of AND elements and to the first inputs of the thirteenth group of OR elements, the second group of decoder outputs the radiator is connected to the inputs of the eighth group of OR elements, the outputs of which are connected to the third inputs of the seventh group of AND elements and to the second input of the thirteenth group of OR elements, the third group of outputs of the decoder is connected to the inputs of the ninth group of OR elements, the outputs of which are connected to the fourth inputs of the seventh group of AND elements and to the third inputs of the thirteenth group of OR elements, the fourth group of outputs of the decoder is connected to the inputs of the tenth group of OR elements, the outputs of which are connected to the fifth inputs of the seventh group of elements And to the fourth inputs of the thirteenth element OR, the fifth group of outputs of the decoder is connected to the inputs of the eleventh group of elements OR, the output of which is connected to the fifth inputs of the thirteenth group of elements OR, through the first element NOT to the second inputs of the fifth group of elements AND is the output of the control unit "error in the control bits ", the output of the thirteenth group of elements OR through the second element is NOT connected to the first input of the eighth group of elements And is the output of the control unit" correctable error ", the output of the twelfth group The OR elements are connected to the second input of the eighth group of AND elements, the output of which is the output of the “uncorrectable error” control unit, the outputs of the seventh group of AND elements are connected to the first inputs of the corrector, the second inputs of which are connected to the outputs of the fifth group of OR elements, and the outputs are connected to the second the inputs of the sixth group of AND elements, the outputs of the fifth group of AND elements are connected to the third inputs of the sixth group of AND elements, the outputs of which are the outputs of the control unit. 4. The fault-tolerant processor of increased reliability of operation according to claim 1, characterized in that the functional circuit for generating the correction when performing arithmetic operations contains the first element And, the second element And, the third element And, the fourth element And, the fifth element And, the sixth element And, the first OR element, second OR element, third OR element, fourth OR element, register, group of disambiguation elements, information input, input that allows reading the output information, information outputs of the functional diagram the formation of corrections when performing arithmetic operations, the first bits of the terms through information inputs are connected to the first element And, the output of which is connected to the first input of the fourth element And to the first input of the register, the second bits of terms through information inputs are connected to the inputs of the second element And and to the inputs of the second OR element, the output of which is connected to the second input of the fourth AND element, the output of the fourth element AND is connected to the first input of the third OR element, the second input of which is connected to the output I will give the first OR element, and the output is connected to the second input of the register and to the first input of the fifth AND element, the third bits of the terms are connected to the inputs of the third AND element and to the inputs of the second OR element, the output of which is connected to the second input of the fifth AND element, the output of the fifth AND element connected to the first input of the fourth OR element, the second input of which is connected to the output of the third AND element, and the output is connected to the third input of the register, the outputs of the register are connected to the inputs of the group of disambiguity elements, the output of which is connected to to the first inputs of the sixth element AND, the second input of the sixth element AND is connected to the input enabling the reading of the output information, the outputs of the sixth element AND are information outputs of the circuit. 5. The fault-tolerant processor with increased reliability of operation according to claim 1, characterized in that the functional diagram for generating an amendment when performing a shift operation contains a first element of discontinuity, a second element of discontinuity, a third element of discontinuity, the first element And, the second element And, the third element And, the fourth element And, fifth element And, sixth element And, seventh element And, eighth element And, ninth element And, tenth element And, eleventh element And, twelfth element And, first element OR, second e OR element, third OR element, fourth OR element, information inputs, shift right control signal input, left shift control signal input, input allowing reading out the output information, corrections forming circuit outputs during the shift operation, the fourth bit of information inputs is connected to the first input of the first disambiguation element and to the first input of the first AND element, the output of which is connected to the first input of the first OR element, the third bit of information inputs is connected to the first input of the second about the disambiguation element and to the second input of the first disambiguation element, the output of which is connected to the first input of the second And element and to the first input of the fifth And element, the second bit of information inputs is connected to the first input of the third disambiguation element and to the second input of the second disambiguation element, the output of which is connected to the first input of the third element And and to the first input of the sixth element And, the first bit of information inputs is connected to the first input of the eighth element And and to the second input of the third ele unequality event, the output of which is connected to the first input of the fourth AND element and to the first input of the seventh AND element, the input of the "right shift" control signal is connected to the second inputs from the first to fourth And elements, the input of the "left shift" control signal is connected to the second inputs with fifth through sixth elements AND, outputs of the second, third and fourth elements AND are connected respectively to the first inputs of the second, third and fourth elements OR, outputs of the fifth, sixth, seventh and eighth elements AND are connected respectively about to the second inputs of the first, second, third and fourth elements OR, the outputs of which are connected to the first inputs of the ninth, tenth, eleventh and twelfth elements And, the second inputs of which are connected to the input allowing the reading of the output information, the outputs from the ninth to twelfth elements AND are outputs correction correction schemes when performing a shift operation. 6. The fault-tolerant processor of increased reliability of operation according to claim 1, characterized in that the functional circuit for generating an amendment when performing the logical OR operation contains the first element AND, the second element And, the third element And, the fourth element And, the fifth element And, the sixth element And, the seventh element And, the eighth element And, information inputs, an input that allows the reading of output information, information outputs of the functional diagram of the formation of the correction when performing a logical operation OR, the first bits of the operands information inputs are connected to the inputs of the first element And, the output of which is connected to the first input of the fifth element And, the second bits of the operands of information inputs are connected to the inputs of the second element And, the output of which is connected to the input of the sixth element And, the third bits of the operands of information inputs are connected to the inputs of the third element And, the output of which is connected to the first input of the seventh element And, the fourth bits of the operands of the information inputs are connected to the inputs of the fourth element And, the output of which is connected to the first Valid eighth AND gate, the entrance allowing information read output connected to second inputs of the fifth to eighth AND gates whose outputs are the outputs of functional circuits forming correction when performing a logical OR operation. 7. The fault-tolerant processor of increased reliability of operation according to claim 1, characterized in that the functional circuit for generating the correction when performing the logical operation AND contains the first OR element, the second OR element, the third OR element, the fourth OR element, the first AND element, the second AND element, the third element And, the fourth element And, information inputs, an input that allows the reading of the output information, information outputs of the functional circuit of the formation of the correction when performing the logical operation And, the first bits of opera ranks of information inputs are connected to the inputs of the first OR element, the output of which is connected to the first input of the first element And, the second bits of the operands of information inputs are connected to the inputs of the second OR element, the output of which is connected to the first input of the second element And, the third bits of the operands of information inputs are connected to the inputs the third OR element, the output of which is connected to the input of the third AND element, the fourth bits of the operands of the information inputs are connected to the inputs of the fourth OR element, the output of which is The key to the first input of the fourth AND gate, the second inputs of the first to fourth AND gates are connected to the input of allowing the reading output data, and outputs data outputs are functional generating circuit when performing correction logic operation I. 8. The fault-tolerant processor of increased reliability of operation according to claim 1, characterized in that the functional circuit for generating an amendment when performing a logical operation NOT contains the first element NOT, the second element NOT, the third element NOT, the fourth element NOT, the first element of disambiguity, the second element of disambiguity , the third element of the disambiguation, the fourth element of the discontinuity, the first element And, the second element And, the third element And, the fourth element And, the fifth element And, the sixth element And, information inputs, input allowing the reading of output information, the inputs of the parity bits of the control bits, the information outputs of the correction correction functional circuit when performing the logical operation NOT, the information inputs are connected respectively to the inputs from the first to fourth elements of NOT, the outputs of the first and second elements are NOT connected to the inputs of the first element of disambiguation, output which is connected to the first input of the third element of disambiguation, the outputs of the third and fourth elements are NOT connected to the inputs of the second element disambiguity, the output of which is connected to the first input of the fourth disambiguation element, the second inputs of the third and fourth discontinuity elements are connected to the inputs of the parity bits of the control discharges, the outputs of the third and fourth discontinuity elements are connected respectively to the first inputs of the first and second elements And, the second inputs of which are connected to the input allowing the reading of output information, which is also connected to the inputs from the third to sixth elements And, the outputs from the first to the sixth element in And are the information outputs of the functional diagram of the formation of the amendment when performing a logical operation NOT.