RU2837139C1 - Reduced instruction set of micro-operating system byte-code and device with limited resources - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to a device with limited resources for running a virtual machine. Device contains microcircuits in the form of intelligent security elements and secure micro controller unit chips, wherein the reduced command set executed by the virtual machine comprises a first command, wherein the first command contains an operation code, wherein the information on the parameters of the first command is contained implicitly in the operation code; a second command, which is a high-frequency command having a plurality of command formats; third command, which contains commands having different command formats based on the number of different parameters; fourth command, which contains commands of frequently used data type and commands of seldom used data type, wherein commands of frequently used data type have multiple formats of commands, and commands of the infrequently used data type have one command format; fifth command, which is a command having a single-byte index of a set of constants; sixth command, which is a macro command; wherein the reduced command set based on the register is configured to reduce the need for memory of microcircuits for permanent storage by minimizing the size of the byte code.

EFFECT: reducing the size of the byte code, which reduces the requirements for the memory of the microcircuit for permanent storage and increases efficiency of executing the code with limited resources of the computing device.

7 cl, 1 dwg, 22 tbl

Description

Field of technology

The present invention relates to the field of virtual machine instruction set technology and, in particular, relates to a reduced bytecode instruction set of a micro-operating system and a resource-constrained device.

State of the art

The Java programming language is an object-oriented language. A "class" describes a set of data (domain descriptions) and data for operation with various methods. Class fields and methods describe the state and behavior of an object. Intelligent SE (Secure Element), a security chip with MCU (Micro Controller Unit) have limited resources, and Java Card virtual machine, which can run applications written in Java, is widely used nowadays. Applications written in Java must generate a Class file through a Java compiler, and then convert the Class file to a Cap file using a conversion tool provided by Java Card, load it into the chip, and execute it by Java Card virtual machine. There are problems with the poor execution performance of the Java Card instruction set based on the operand stack compared to the bytecode of the register-based instruction set.

Disclosure of the essence of the invention

Taking into account the shortcomings existing in the prior art, the object of the present invention is to provide a reduced set of bytecode instructions of a micro-operating system and a resource-limited device such as intelligent SE, secure MCU chips, which can be used with various object-oriented and architecture-independent programs to minimize the size of the bytecode, which can not only reduce the memory requirements of the chip for permanent storage, but also improve the efficiency of code execution.

To solve the above problem, the technical solution adopted in the present invention is as follows:

a reduced set of bytecode instructions for a microoperating system, including:

the first command, where the first command contains the operation code, and the information about the parameters of the first command is expressed implicitly in the operation code;

the second command, which is a high-frequency command that has many command formats;

the third command, which contains a command that has different command formats based on a different number of parameters;

a fourth command that contains a frequently used data type command and a rarely used data type command, wherein the frequently used data type command has a plurality of command formats and the rarely used data type command has one command format;

the fifth command, which is a command that has a one-byte index of a set of constants;

the sixth command, which is a macro command.

Additionally, in the reduced command set as described above, the first command contains:

an instruction that implicitly includes both an operand and a register number in the opcode;

an instruction that implicitly includes a register number in the opcode;

an instruction that implicitly includes a constant operand in the opcode;

an array element access command that implicitly includes the array element type in the opcode;

a command that implicitly includes the type and parameters of the method call in the opcode.

Additionally, in the reduced command set as described above, the second command contains:

a frequently used arithmetic operation command that has many operation formats;

command to access an array element in 4-bit register format;

an array creation command that implicitly includes the array element type in the opcode;

branching instructions, which have a variety of instruction formats based on equal and unequal comparison results.

Additionally, in the reduced command set as described above, the third command contains:

a static method call command that has different command formats based on a different number of parameters;

a virtual method call command that has different command formats based on a different number of parameters;

private instance method invocation command, which has different command formats based on different number of parameters.

Additionally, in the reduced command set as described above, the fourth command contains:

the frequently used data types command, which includes the short data types command;

the rarely used data types command, which includes the int data types command.

Additionally, in the reduced command set as described above, the fifth command contains:

a static method call command that has a one-byte index into a set of constants;

a virtual method call command that has a one-byte index into a set of constants;

a static domain access command that has a one-byte index into a set of constants;

an instance domain access command that has a one-byte index into a set of constants.

Additionally, in the reduced command set as described above, the sixth command contains:

a macro command formed on the basis of replacing the static method call command;

a macro command formed by combining a set of related commands.

A device with limited resources, wherein a virtual machine is running on the device with limited resources, wherein the virtual machine is designed with the ability to execute a reduced set of commands according to any of paragraphs 1-7.

The positive effects of the present invention are: the present invention provides a register-based virtual machine instruction set for resource-constrained devices such as intelligent SEs, secure MCU chips, which can be used with various object-oriented and architecture-independent programs to reduce the size of bytecode as much as possible, which can not only reduce the memory requirements of the chip for persistent storage, but also improve the efficiency of code execution.

Brief description of the drawings

The figure illustrates a schematic diagram of a reduced instruction set of a bytecode micro-operating system according to an embodiment of the present invention.

Detailed description of embodiments

The present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments.

Instructions consist of a byte-long opcode that specifies the operation to be performed, followed by zero or more operands representing the value to be operated on. Each cell in the instruction format description represents a byte. A register in an instruction consists of 16 bits that can represent a boolean, byte, short, reference type, and return address; the int type requires two consecutively numbered pairs of registers. The null reference represents the value of the short type 0, i.e. (object) null = (short) 0. The last few registers in the method call stack frame are used to pass method parameters. The present invention provides a register-based TGoMOS virtual machine instruction set (hereinafter referred to as a reduced instruction set) for resource-constrained devices such as intelligent SEs, secure MCUs, which can be used with various object-oriented and architecture-independent programs to reduce the size of bytecode as much as possible, which can not only reduce the memory requirement of the chip for persistent storage, but also improve the efficiency of code execution.

As shown in Fig. 1, an embodiment of the present invention provides a reduced instruction set for a bytecode of a micro-operating system, wherein the reduced instruction set comprises: a first instruction, a second instruction, a third instruction, a fourth instruction, a fifth instruction, and a sixth instruction.

The first command consists of an operation code, and the information about the parameters of the first command is expressed implicitly in the operation code. The first command includes:

a. An instruction that implicitly includes both an operand and a register number in the opcode, such as the constant assignment instruction in Table 1 below.

Table 1 Command format Mnemonics Performance op const-0/r0 r0=0 const-0/r1 r1=0 const-0/r2 r2=0 const-0/r3 r3=0 const-0/r4 r4=0 const-1/r0 r0=1 const-1/r1 r1=1 const-1/r2 r2=1 const-1/r3 r3=1 const-1/r4 r4=1 const-2/r0 r0=2 const-2/r1 r1=2 const-2/r2 r2=2 const-2/r3 r3=2 const-2/r4 r4=2 const-3/r0 r0=3 const-3/r1 r1=3 const-3/r2 r2=3 const-3/r3 r3=3 const-3/r4 r4=3 const-4/r0 r0=4 const-4/r1 r1=4 const-4/r2 r2=4 const-4/r3 r3=4 const-4/r4 r4=4

From Table 1 it can be seen that the assignment of constants is a very frequent operation, and the use of the above encoding can significantly reduce the length of the bytecode of the method.

b. An instruction that implicitly includes a register number in the opcode, such as the constant assignment instruction in Table 2, the static domain access instruction in Table 3, the non-object result instruction called by the return method in Table 4, the object reference result instruction called by the method in Table 5, and the array member access instruction in Table 6.

Table 2 Command format Mnemonics Performance op AA const-c8/r0AA r0/1/2/3/4/5=AA
AA symbol extended to 16 bits const-c8/r1 AA const-c8/r2 AA const-c8/r3 AA const-c8/r4 AA const-c8/r5 AA

Table 3 Command format Mnemonics Performance op AA getstatic-o/r0 AA Returns the value of the static reference field to register r0-r4
AA: Index of constant set for static fields getstatic-o/r1 AA getstatic-o/r2 AA getstatic-o/r3 AA getstatic-o/r4 AA

Table 4 Command format Mnemonics Performance op mv-r/r0 Moves the non-object single word result of the most recent method call into registers r0-r4
This command must follow the method call. mv-r/r1 mv-r/r2 mv-r/r3 mv-r/r4

Table 5 Command format Mnemonics Performance op mv-ro/r0 Moves the non-object result of the most recent method call into registers r0-r1
This command must follow the method call. mv-ro/r1

Table 6 Command format Mnemonics Performance op A | B getarray-b/r0 rA rB
getarray-b/r1 rA rB
getarray-b/r2 rA rB
getarray-b/r3 rA rB
getarray-b/r4 rA rB
getarray-b/r5 rA rB r0-r5: Return value
rA: Array reference, 4-bit register
rB: Element index, 4-bit register

c. an instruction that implicitly includes a constant operand in the opcode;

d. an array element access command that implicitly includes the array element type in the opcode;

e. a command that implicitly includes the type and parameters of the method call in the opcode.

The reduced instruction set of the present invention further comprises a second instruction, and the second instruction is a high-frequency instruction having a plurality of instruction formats. The second instruction includes:

a. A frequently used arithmetic operation command that has many operation formats, such as the addition operation command in Table 7, the AND operation command in Table 8.

Table 7 Command format Mnemonics Performance op A | B add/2r rA rB rA=rA+rB op A | B add-c4/1r rA B rA=rA+B op A | B CC add-c8rA rB CC rA=rB+CC op AA B | C add/R44 rAA rB rC rAA=rB+rC op AA BB CC add rAA rBB rCC rAA=rBB+rCC op A | B iadd/2r rA rB rA=rA+rB op A | B CC iadd-c8rA rB CC rA=rB+CC op A | B CC _h CC _l iadd-c16rA rB CCCC rA=rB+CCCC op AA BB CC iadd rAA rBB rCC rAA=rBB+rCC

Because add operations are more common, providing multiple operation formats can reduce the bytecode size. Compared to the 4-byte length of the add rAA rBB rCC/iadd rAA rBB rCC instruction, using other instructions can reduce the size by 1 or 2 bytes.

Table 8 Command format Mnemonics Performance op A | B and/2r rA rB rA=rA & rB op A | B and-c4rA, B rA=rA & B op A | B s2b2s rA rB rA=rB & 0x00FF op A | B CC and-c8rA, rB, CC rA=rB & CC op AA B | C and/R44 rAA rB rC rAA=rB & rC op A | B CC _h CC _l and-c16rA rB CCCC rA=rB and CCCC op AA BB CC and rAA rBB rCC rAA=rBB & rCC op A | B iand/2r rA rB rA=rA & rB op A | B CC iand-c8rA, rB, CC rA=rB & CC op A | B CC _h CC _l iand-c16rA rB CCCC rA=rB and CCCC op AA BB CC iand rAA rBB rCC rAA=rBB & rCC

Because operations are more common, providing multiple operation formats can reduce the bytecode size. Compared to the 4-byte length of the and rAA rBB rCC/iand rAA rBB rCC instruction, using other instructions can reduce the size by 1 or 2 bytes. For example, the third line of the s2b2s rA rB instruction implicitly includes the 0xFF operand in the opcode, reducing the instruction length.

b. an array element access command in 4-bit register format, as shown in Table 9.

Table 9 Command format Mnemonics Performance op AA B | C getarray-o/R44 rAA rB rC rAA: Returns or sets the value of an 8-bit register
rB: Array reference, 4-bit register
rC: Element index, 4-bit register op AA BB CC getarray-b rAA rBB rCC rAA: Returns or sets the value of an 8-bit register
rBB: Array reference, 8-bit register
rCC: Element index, 8-bit register getarray-s rAA rBB rCC getarray-o rAA rBB rCC putarray-b rAA rBB rCC putarray-s rAA rBB rCC putarray-o rAA rBB rCC op AA BB CC igetarray rAA rBB rCC rAA: Returns or sets the value of an 8-bit register pair.
rBB: Array reference, 8-bit register
rCC: Element index, 8-bit register

Table 9 shows that 4-bit register format instructions are one byte smaller than 8-bit register format instructions, and a 4-bit register for frequently used instructions (such as getarray-o) can significantly reduce the bytecode length.

c. an array creation command that implicitly includes the array element type in the opcode, as shown in Table 10.

Table 10 Command format Mnemonics Performance op A | B newarray-b rA rB Creating an array of byte types
rA: Store reference to new arrays
rB: Number of array elements op AA B | C newarray rAA rB C Creating boolean, short, int and basic array types
rAA: Storing reference to new arrays
rB: Number of array elements
C: An array type whose value is given in the table below op CC _h CC _l A | B newarray-o rA rB CCCC Create a reference type array
rA: Store reference to new arrays
rB: Number of array elements
CCCC: Index of the constant set of an array element of a reference type

From Table 10, it can be seen that the first line of the command newarray-b rA rB is used more frequently, and the element type (byte) of the array element is implicitly included in the opcode, which can be reduced by 1 or 2 bytes compared to the other two commands.

d. Based on equal and unequal comparison results, branch instructions have a variety of instruction formats, including branch instructions that compare with 0 values, such as those in Table 11, and branch instructions that compare with two operands, such as those in Table 12.

Table 11 Command format Mnemonics Performance op AA BB ifeqz rAA BB rAA: 8-bit register for comparison
BB: 8-bit signed branch offset ifnez rAA BB op AA BB _h BB _l ifeqz/t16 rAA BBBB rAA: 8-bit register for comparison
BB: 16-bit signed branch offset ifnez/t16 rAA BBBB

Table 12 op A | B CC ifeq rA rB CC rA: First register to compare
rB: Second register to compare
CC: 8-bit signed branch offset ifne rA rB CC op A | B CC _h CC _l ifeq/t16 rA rB CCCC CCCC: 16-bit signed branch offset
Other commands similar to the above command ifne/t16 rA rB CCCC

In Table 12 above, the 8-bit offset instruction reduces the length of one byte.

The reduced command set of the present invention further includes a third command that contains a command that has a different command format based on a different number of parameters. The third command includes:

a. a static method call command that has different command formats based on different numbers of parameters, such as in Table 13;

b. a virtual method call command having different command formats based on different numbers of parameters, such as in Table 14;

c. a private instance method invocation command that has different command formats based on different numbers of parameters.

Table 13 Command format Mnemonics Performance op AA B | C invstatic/01 {rC} AA 0 or 1 register parameters
AA: Index of constant set for static methods
Number of parameters B
B=1 {rC}
B=0 {} op AA B | C D | E invstatic/23 {rC rD rE} AA 2 or 3 register parameters
AA: Index of constant set for static methods
Number of parameters B
B=3 {rC, rD, rE}
B=2 {rC, rD} op AA B | C D | E F | G invstatic/45 {rC rD rE rF rG} AA 4 or 5 register parameters
AA: Index of constant set for static methods
Number of parameters B
B=5 {rC, rD, rE, rF, rG}
B=4 {rC, rD, rE, rF} op AA _h AA _l B | C invstatic/01cp16{rC}AAAA 0 or 1 register parameters
AAAA: Index of constant set for static methods
Number of parameters B
B=1 {rC}
B=0 {} op AA _h AA _l B | CD | E invstatic/23cp16 {rC rD rE} AAAA 2 or 3 register parameters
AAAA: Index of constant set for static methods
Number of parameters B
B=3 {rC, rD, rE}
B=2 {rC, rD} op AA _h AA _l B | CD | EF | G invstatic/45cp16 {rC rD rE rF rG} AAAA 4 or 5 register parameters
AAAA: Index of constant set for static methods
Number of parameters B
B=5 {rC, rD, rE, rF, rG}
B=4 {rC, rD, rE, rF}

Table 14 Command format Mnemonics Performance op AA B | C D | E invvirtual/13 {rC rD rE} AA 1 or 3 register parameters
AA: Index of the set of constants for virtual methods
Number of parameters B
B=3 {rC, rD, rE}
B=2 {rC, rD}
B=1 {rC} op AA B | C D | E F | G invvirtual/45 {rC rD rE rF rG} AA 4 or 5 register parameters
AA: Index of the set of constants for virtual methods
Number of parameters B
B=5 {rC, rD, rE, rF, rG}
B=4 {rC, rD, rE, rF}

From Table 13-14 it can be seen that for method calls without parameters or with a relatively small number of parameters, the above-mentioned encoding instructions are relatively short, in particular, such calls are used more often, and the bytecode size of the method can be significantly reduced.

The reduced instruction set of the present invention further includes a fourth instruction that includes an instruction of a frequently used data type and an instruction of a rarely used data type, wherein the instruction of the frequently used data type has a plurality of instruction formats, and the instruction of the rarely used data type has an instruction format. The frequently used instruction data types include short instruction data types, and the rarely used instruction data types include int instruction data types.

The reduced instruction set of the present invention further comprises a fifth instruction, which is an instruction having a one-byte index of a set of constants. The fifth instruction includes:

a. a virtual method call instruction that has a one-byte index into a set of constants, as shown in Table 15;

b. a virtual method call instruction having a one-byte index into the constant set, as shown in Table 16;

c. a static domain access command that has a one-byte index into a set of constants, as shown in Table 17;

d. an instance domain access command that has a one-byte index into a set of constants, as shown in Table 18.

Table 15 Command format Mnemonics Performance op AA B | C invstatic/01 {rC} AA 0 or 1 register parameters
AA: Index of constant set for static methods
Number of parameters B
B=1 {rC}
B=0 {} op AA B | C D | E invstatic/23 {rC rD rE} AA 2 or 3 register parameters
AA: Index of constant set for static methods
Number of parameters B
B=3 {rC, rD, rE}
B=2 {rC, rD} op AA B | C D | E F | G invstatic/45 {rC rD rE rF rG} AA 4 or 5 register parameters
AA: Index of constant set for static methods
Number of parameters B
B=5 {rC, rD, rE, rF, rG}
B=4 {rC, rD, rE, rF} op AA _h AA _l B | C invstatic/01cp16{rC}AAAA 0 or 1 register parameters
AAAA: Index of constant set for static methods
Number of parameters B
B=1 {rC}
B=0 {} op AA _h AA _l B | CD | E invstatic/23cp16 {rC rD rE} AAAA 2 or 3 register parameters
AAAA: Index of constant set for static methods
Number of parameters B
B=3 {rC, rD, rE}
B=2 {rC, rD} op AA _h AA _l B | CD | EF | G invstatic/45cp16 {rC rD rE rF rG} AAAA 4 or 5 register parameters
AAAA: Index of constant set for static methods
Number of parameters B
B=5 {rC, rD, rE, rF, rG}
B=4 {rC, rD, rE, rF}

Table 16 Command format Mnemonics Performance op AA B | C D | E invvirtual/13 {rC rD rE} AA 1 or 3 register parameters
AA: Index of the set of constants for virtual methods
Number of parameters B
B=3 {rC, rD, rE}
B=2 {rC, rD}
B=1 {rC} op AA B | C D | E F | G invvirtual/45 {rC rD rE rF rG} AA 4 or 5 register parameters
AA: Index of the set of constants for virtual methods
Number of parameters B
B=5 {rC, rD, rE, rF, rG}
B=4 {rC, rD, rE, rF}

Table 17 Command format Mnemonics Performance op AA getstatic-o/r0 AA Returns the value of the static reference field to register r0-r4
AA: Index of constant set for static fields getstatic-o/r1 AA getstatic-o/r2 AA getstatic-o/r3 AA getstatic-o/r4 AA op BB AA getstatic-o/R8 rAA BB rAA: Returns the value of a static field, 8-bit register
BB: Index of constant set for static fields op BB _h BB _l AA getstatic-b/cp16rAA BBBB rAA: Returns or sets the value to be set of a static field, 8-bit register
BBBB: Index of constant set for static fields getstatic-s/cp16rAA BBBB getstatic-o/cp16rAA BBBB putstatic-b/cp16rAA BBBB putstatic-s/cp16rAA BBBB putstatic-o/cp16rAA BBBB op BB _h BB _l AA igetstatic rAA BBBB rAA: Returns or sets the value of the static field to be set, an 8-bit register pair
BBBB: Index of constant set for static fields

Table 18 Format Mnemonics Performance op CC A | B getfield-o rA rB CC rA: Gets or sets the value of an instance field
rB: Object register
CC: Instance domain constant set index op CC _h CC _l A | B getfield-b/cp16rA rB CCCC rA: Gets or sets the value of an instance field
rB: Object register
CCCC: Instance Domain Constant Set Index getfield-s/cp16rA rB CCCC getfield-o/cp16rA rB CCCC putfield-b/cp16rA rB CCCC putfield-s/cp16rA rB CCCC putfield-o/cp16 rA rB CCCC op CC _h CC _l A | B igetfield/cp16rA rB CCCC rA is a register pair that returns or sets the value of the instance field to be set
rB: Object register
CCCC: Instance Domain Constant Set Index iputfield/cp16rA rB CCCC

From Table 15-18 it can be seen that if a single-byte index of the constant set can be used, the bytecode length can be significantly reduced.

The reduced instruction set of the present invention further includes a sixth instruction, which is a macroinstruction. The sixth instruction includes a macroinstruction formed on the basis of replacing a static method call instruction, and a macroinstruction formed on the basis of merging a plurality of adjacent instructions, as shown in Table 19.

Command format Mnemonics Performance op0A BC DE arrayCopy rA rB rC rD rE short arrayCopy(byte[] src, short srcOff, byte[] dest, short destOff, short length) throws ArrayIndexOutOfBoundsException, NullPointerException, TransactionException;
The meaning of each register:
rA:src
rB:srcOff
rC:dest
rD: destOff
rE: length op0A BC DE arrayCopyNonAtomic rA rB rC rD rE short arrayCopyNonAtomic(byte[] src, short srcOff, byte[] dest, short destOff, short length) throws ArrayIndexOutOfBoundsException, NullPointerException, SystemException;
The meaning of each register:
rA:src
rB:srcOff
rC:dest
rD: destOff
rE: length op A | B C | D arrayFill rA rB rC rD short arrayFill(byte[] bArray, short bOff, short bLen, byte bValue) throws ArrayIndexOutOfBoundsException, NullPointerException;
The meaning of each register:
rA: bArray
rB: bOff
rC: bLen
rD: bValue op A | B C | D arrayFillNonAtomic rA rB rC rD short arrayFillNonAtomic (byte[] bArray, short bOff, short bLen, byte bValue) throws ArrayIndexOutOfBoundsException, NullPointerException;
The meaning of each register:
rA: bArray
rB: bOff
rC: bLen
rD: bValue op0A BC DE arrayCompare rA rB rC rD rE byte arrayCompare(byte[] src, short srcOff, byte[] dest, short destOff, short length) throws ArrayIndexOutOfBoundsException, NullPointerException;
The meaning of each register:
rA:src
rB:srcOff
rC:dest
rD: destOff
rE: length op0 | A B | C setShort rA rB rC short setShort(byte[] bArray, short bOff, short sValue) throws TransactionException, NullPointerException, ArrayIndexOutOfBoundsException;
The meaning of each register:
rA: bArray
rB: bOff
rC:sValue op A | B makeShort rA rB short makeShort (byte b1, byte b2)
The meaning of each register:
rA: b1
rB:b2 op A | B getShort rA rB short getShort(byte[] bArray, short bOff) throws NullPointerException, ArrayIndexOutOfBoundsException
The meaning of each register:
rA: bArray
rB: bOff op A | B C | D const-c4/2rA rB C D rA=C rB=D op A | C BB DD const-c4c8 rA rBB C DD rA=C rBB=DD op AA BB CC DD const-c8/2rAA rBB CC DD rAA=CC rBB=DD op A | B C | D mv/2 rA rB rC rD rA=rC, rB=rD op A | B CC getarray-b/I rA rB CC rA: Return value
rB: Array reference, 4-bit register
CC: Member index, 8-bit unsigned register op AA BB _h BB _l invstatic/1c BBBB AA AA: Index of constant set for static methods
BBBB: 16-bit signed constant parameter

Table 19 shows that macros for replacing static methods do not have to provide an index of the constant set, and since the frequency of such calls to static methods is relatively high, replacing them with appropriate macros can significantly reduce the size of the bytecode.

The instruction set of the TGoMOS virtual machine of the present invention is a reduced instruction set, and Table 20 below provides a brief list of the bytecode instruction set.

Table 20 op Mnemonics op Mnemonics op Mnemonics op Mnemonics 0 nop 52 mv-r/r3 104 ixor 156 getstatic-o/R8 1 const-0/r0 53 mv-r/r4 105 ishl 157 getstatic-b/cp16 2 const-0/r1 54 mv-r 106 ishr 158 getstatic-s/cp16 3 const-0/r2 55 mv-ro/r0 107 iushr 159 getstatic-o/cp16 4 const-0/r3 56 mv-ro/r1 108 goto 160 putstatic-b/cp16 5 const-0/r4 57 mv-ro 109 goto/t16 161 putstatic-s/cp16 6 const-1/r0 58 mv-e 110 icmp 162 putstatic-o/cp16 7 const-1/r1 59 imv 111 ifeqz 163 igetstatic 8 const-1/r2 60 imv/R8 112 ifnez 164 iputstatic 9 const-1/r3 61 imv-r 113 ifeqz/t16 165 new instance 10 const-1/r4 62 return-v 114 ifnez/t16 166 getfield-o 11 const-2/r0 63 return/r0 115 ifltz/t16 167 getfield-b/cp16 12 const-2/r1 64 return 116 ifgez/t16 168 getfield-s/cp16 13 const-2/r2 65 return-o 117 ifgtz/t16 169 getfield-o/cp16 14 const-2/r3 66 turn 118 iflez/t16 170 putfield-b/cp16 15 const-2/r4 67 s2b 119 ifeq 171 putfield-s/cp16 16 const-3/r0 68 s2i 120 ifne 172 putfield-o/cp16 17 const-3/r1 69 i2s 121 ifeq/t16 173 igetfield/cp16 18 const-3/r2 70 i2b 122 ifne/t16 174 iputfield/cp16 19 const-3/r3 71 add/2r 123 iflt/t16 175 invstatic/01 20 const-3/r4 72 add/R44 124 ifge/t16 176 invstatic/23 21 const-4/r0 73 add-c4/1r 125 ifgt/t16 177 invstatic/45 22 const-4/r1 74 add-c8 126 ifle/t16 178 invstatic/01cp16 23 const-4/r2 75 add 127 packed switch 179 invstatic/23cp16 24 const-4/r3 76 sub 128 sparseswitch 180 invstatic/45cp16 25 const-4/r4 77 mul 129 newarray-b 181 invvirtual/13 26 const-c4 78 div 130 newarray 182 invvirtual/45 27 cosnt-c8/r0 79 rem 131 newarray-o 183 invspecial/13 28 cosnt-c8/r1 80 iadd 132 fillarray 184 invspecial/45 29 cosnt-c8/r2 81 isub 133 arraylength 185 invinterface/13 30 cosnt-c8/r3 82 imul 134 getarray-b/r0 186 invinterface/45 31 cosnt-c8/r4 83 idiv 135 getarray-b/r1 187 invvirtual/r 32 cosnt-c8/r5 84 irem 136 getarray-b/r2 188 invstatic/r 33 const-c8 85 neg 137 getarray-b/r3 189 invspecial/r 34 const/r0 86 not 138 getarray-b/r4 190 invinterface/r 35 const/r1 87 and/2r 139 getarray-b/R44 191 throw 36 const/r2 88 and/R44 140 getarray-o/R44 192 instanceof 37 const/r3 89 and-c4/1r 141 putarray-b/R44 193 checkcast 38 const/r4 90 and-c8 142 putarray-o/R44 194 arrayCopy 39 const/r5 91 s2b2s 143 getarray-b 195 arrayCopyNonAtomic; 40 const 92 and 144 getarray-s 196 arrayFill 41 iconst-c4 93 or-c8 145 getarray-o 197 arrayFillNonAtomic 42 iconst-c8 94 or 146 putarray-b 198 arrayCompare 43 iconst-c16 95 xor-c8 147 putarray-s 199 setShort 44 icons 96 xor 148 putarray-o 200 makeShort 45 mv 97 shl 149 igetarray 201 getShort 46 mv/R8 98 shr 150 iputarray 202 const-c4/2 47 mv-o 99 ushr 151 getstatic-o/r0 203 const-c4c8 48 mv-o/R8 100 ineg 152 getstatic-o/r1 204 const-c8/2 49 mv-r/r0 101 inot 153 getstatic-o/r2 205 mv/2 50 mv-r/r1 102 iand 154 getstatic-o/r3 206 getarray-b/I 51 mv-r/r2 103 ior 155 getstatic-o/r4 207 invstatic/1c

An embodiment of the present invention further provides a resource-constrained device, wherein a virtual machine is running on the resource-constrained device, and the virtual machine is used to execute the above-mentioned reduced set of instructions.

The register-based virtual machine instruction set developed in the present invention is used for resource-constrained devices such as intelligent SE, secure MCU chips, which can be used with various object-oriented and architecture-independent programs to minimize the size of bytecode, which can not only reduce the memory requirement of the chip for persistent storage, but also improve the efficiency of code execution.

In order to verify the above-mentioned advantageous effects of the reduced instruction set of the present invention, the Java Card instruction set and the TGoMOS instruction set (the reduced instruction set of the present invention) are compared, in addition to the bytecode interpreter code, the virtual machine system implemented in the same chip has basically the same code, the instruction disables the labor-intensive cryptographic algorithm and the flash memory write operation, the average time of 10 execution results is used for comparison, and the comparison results are obtained. The comparison result of the size of the converted bytecode of the Java Card instruction set and the TGoMOS instruction set is shown in Table 21. The performance comparison results of the EDEP electronic wallet applications on the Java Card and TGoMOS platforms are shown in Table 22.

Table 21 Application/Library Package Java Card TGoMOS framework 0x41B 0x498 security 0x5A8 0x57A guomi 0x1D5 0x1F2 crs 0xE2 0xE3 securitydomian 0x12C 0x135 open 0x6A4 0x6BA prepaid 0x2352 0x24C4

Table 22 Operation type TGoMOS Java Card Increase productivity % Selecting an application 2898 3078 5.85 Initializing the ring memory configuration 5958 6826 12.72 Memory 3118 3232 3.53 Subtotal 14188 15690 9.57 Selecting an application 2904 3079 5.68 Initialization of consumption 5646 6438 12.30 Consumption 4192 4378 4.25 Getting balance 2214 2554 13.31 Subtotal 14956 16449 9.08 Selecting an application 2906 3080 5.65 Initializing connection consumption 5542 6439 13.93 Update file-1A 2501 2579 3.02 Update file-1E 2675 2756 2.94 Connection consumption 4164 4356 4.41 Getting balance 2214 2554 13.31 Subtotal 20002 21764 8.10

It can be seen from Table 21 that, compared with the Java Card instruction set, the bytecode size of the TGoMOS instruction set (the reduced instruction set of the present invention) is close to the Java Card instruction set. It can be seen from Table 22 that the performance of applying the EDEP electronic wallet to the TGoMOS virtual machine instruction set platform is better.

It is obvious that those skilled in the art can make various changes and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and its equivalent technology, the present invention is also intended to include these modifications and variations.

Claims (33)

1. A device with limited resources for running a virtual machine, containing chips in the form of intelligent secure elements (Secure Element) and secure Micro Controller Unit chips, characterized in that the reduced set of register-based commands executed by the virtual machine contains: the first command, where the first command contains the operation code, and information about the parameters of the first command is contained implicitly in the operation code; the second command, which is a high-frequency command that has many command formats; the third command, which contains commands that have different command formats based on the number of different parameters; a fourth command that contains commands of a frequently used data type and commands of a rarely used data type, wherein the commands of the frequently used data type have multiple command formats, and the commands of the rarely used data type have one command format; the fifth command, which is a command that has a one-byte index of a set of constants; the sixth command, which is a macro command; wherein the reduced register-based instruction set is designed to reduce the need for microcircuit memory for permanent storage by minimizing the size of the bytecode. 2. A device with limited resources according to paragraph 1, characterized in that the first command contains: an instruction that implicitly includes both an operand and a register number in the opcode; an instruction that implicitly includes a register number in the operation code; an instruction that implicitly includes a constant operand in the operation code; an array element access command that implicitly includes the array element type in the opcode; a command that implicitly includes the type and parameters of the method call in the opcode. 3. A device with limited resources according to paragraph 1, characterized in that the second command contains: a frequently used arithmetic operation command that has many operation formats; command to access an array element in 4-bit register format; an array creation command that implicitly includes the array element type in the opcode; a branching instruction that has multiple instruction formats based on equal and unequal comparison results. 4. A device with limited resources according to paragraph 1, characterized in that the third command contains: a static method call command that has different command formats based on a different number of parameters; a virtual method call command that has different command formats based on a different number of parameters; private instance method invocation command, which has different command formats based on different number of parameters. 5. A device with limited resources according to paragraph 1, characterized in that the fourth command contains: a frequently used data type command that includes a short data type command; a rarely used data type command that includes the int data type command. 6. A device with limited resources according to paragraph 1, characterized in that the fifth command contains: a static method call command that has a one-byte index into a set of constants; a virtual method call command that has a one-byte index into a set of constants; a static domain access command that has a one-byte index into a set of constants; an instance domain access command that has a one-byte index into a set of constants. 7. A device with limited resources according to paragraph 1, characterized in that the sixth command contains: a macro command formed on the basis of replacing the static method call command; a macro command formed by combining a set of related commands.