RU2836117C1 - Method of rejecting potentially unreliable digital integrated circuits by signal propagation delay time - Google Patents

Abstract

FIELD: microelectronics.

SUBSTANCE: invention relates to microelectronics and specifically to methods of rejecting potentially unreliable digital integrated circuits (DIC) by signal propagation delay both in the process of their manufacture and in the manufacture of radioelectronic equipment. Signal propagation delay time is measured at the DIC batch on all IC inputs. First criterion for rejection of potentially unreliable ICs is established by the absolute value of the signal propagation delay, which does not exceed the specified value, at supply voltage close to the critical value. Signal propagation delay time is measured at the same circuits and inputs at rated supply voltage. Constructing a table, where for each DIC the minimum value of the signal propagation delay time when one of the inputs is switched off is taken as a unit, and the other inputs are used to record coefficient Ki, which is equal to the ratio of the value of the signal propagation delay time along this input to the value of the minimum delay time value, taken as a unit. Second criterion for rejection is selected based on the value of the coefficient Ki, which does not exceed the specified value. Those DIC, in which two criteria coincide, are considered to be potentially unreliable.

EFFECT: high reliability of rejection results for potentially unreliable ICs.

1 cl, 3 tbl

Description

The invention relates to microelectronics, namely to methods for rejecting potentially unreliable digital integrated circuits (DICs) based on the signal propagation delay time both during their manufacturing process and during the manufacturing of electronic equipment.

A method for monitoring integrated circuits (IC) is known, patent RU 2285270 C1, authors Gorlov M.I., Plebanovich V.I., Smirnov D.Yu., including measuring their static parameters at nominal supply voltage, measuring the static parameters of the integrated circuit at reduced supply voltage in the range of 3.1-3.2 V, determining the differences in the values of the static parameters measured at nominal and reduced supply voltages, and comparing this difference with the reference value. The disadvantage of the method is that it does not cover defects that appear in the dynamic mode of operation of the integrated circuit.

There is also a known method [Pokrovsky F.M. Comparative assessment of the quality of CMOS ICs // Proceedings of the reports of the scientific and technical seminar "Noise and degradation processes in semiconductor devices". Moscow: MIET, 1996, pp. 265 - 272] of rejecting potentially unreliable CMOS ICs, based on measuring the critical supply voltage E _cr and its dependence on the repetition rate of test signals. The disadvantage of this method is low productivity, due to the determination of the signature in the i-th measurement cycle, a decrease in the supply voltage of the IC, determination of the signature in the (i + 1) cycle, comparison with the previous value, etc. until the signature analyzer records a failure in the operation of the IC, as well as low reliability.

The closest in technical essence and achieved effect is the method [Gorlov M.I., Emelyanov A.V., Smirnov D.Yu. Diagnostics in modern microelectronics. Minsk: Integralpoligraf, 2011. - 378 p.]. A supply voltage close to the critical one and an input test sequence of pulses with an amplitude limited by the supply voltage of the tested IC are applied to the tested IC to prevent false alarms and circuit breakdown. As an informative parameter for IC rejection, the signal propagation delay time when turning on and off is measured, which allows for a greater account of IC defects than measuring static parameters, and at the same time is an earlier stage of defect detection than an unstable signature. IC rejection is carried out by comparing the difference in the response values when turning on (off) between the average value of the response delay of a specific IC with the reference value.

The disadvantage of this method is low productivity.

It is known that the time parameters of digital integrated circuits increase with a decrease in supply voltage, which is equivalent to an increase in the duration of the transient process during operation [Kurachenko S.S., Prokhorenko V.A., Volnov V.V. New method for diagnosing integrated circuits // Electronic Industry, 1990. - No. 6. - P. 71-72]. Based on this principle, a method for predicting the performance of digital integrated circuits is proposed.

According to the circuit design and manufacturing technology, the time parameters for identical inputs should ideally be the same, but in fact they differ. The magnitude of the difference in the time parameters for identical inputs carries information about the imperfection of the surface and volume structure of p-n junctions. Therefore, by measuring the time parameters for identical inputs, their difference can be used to judge the potential reliability of these junctions, and, consequently, the reliability of the digital integrated circuit as a whole.

The proposed diagnostic method consists of measuring dynamic parameters on a batch of digital integrated circuits in which it is necessary to identify and then separate potentially unreliable circuits, for example, the signal propagation delay time when switching on (switching off), at all inputs separately at a supply voltage close to critical, and the same for all digital integrated circuits. The first criterion for rejecting potentially unreliable integrated circuits is established by the absolute value of the time (dynamic) parameter.

Then, on the same circuits, the same time parameter is measured for all inputs at the nominal supply voltage and a table is constructed, where for each digital integrated circuit, the minimum value of the signal propagation delay time when switching on (off) for one of the inputs is taken as one, and for the remaining inputs, the coefficient K _i is recorded, equal to the ratio of the signal propagation delay time for a given input to the value of the minimum delay time, taken as one, and the second evaluation criterion for rejection is selected, and those digital integrated circuits for which the two criteria coincide are considered potentially unreliable.

Specific values of the criteria are determined for each type of CIS depending on the severity of the reliability requirements.

The following experiment was conducted.

On 10 randomly selected K155LR1 type digital integrated circuits (two 2I-2OR-NOT elements, one with OR expansion), the signal propagation delay time was measured when switching off. at a supply voltage of U _H = 2 V and a pulse frequency of 10 MHz (table 1). This voltage is determined by reducing the supply voltage for each circuit until the digital integrated circuit still operates as intended.

Table 1

Scheme No. Signal propagation delay time when switching off ns, at U _supply = 2 V, by terminals (2, 3, 4, 5 - input terminals, 6 - output terminal) 2-6 3-6 4-6 5-6 1 120 70 100 80 2 120 120 120 100 3 130 100 100 100 4 140 100 100 90 5 160 100 110 90 6 150 100 110 90 7 120 100 110 100 8 150 110 100 110 9 130 100 100 110 10 120 100 100 90

If, based on the data obtained in table 1, we select the first criterion ns, then CIS No. 5, 6, 8 will be potentially unreliable.

Then we measured at nominal supply voltage (table 2).

Table 2

Scheme No. Signal propagation delay time when switching off ns, at U _pit = 5 V, by terminals 2-6 3-6 4-6 5-6 1 30 25 30 30 2 30 30 25 30 3 30 40 25 30 4 35 30 25 30 5 30 35 20 30 6 30 25 25 30 7 40 30 25 30 8 40 30 20 30 9 35 40 25 30 10 45 25 20 30

Based on the data obtained, a table of 3 increase factors was compiled. for all conclusions relative to the minimum value of K _i for each circuit.

Table 3

Scheme No. Values of the coefficient K _i by the conclusions 2-6 3-6 4-6 5-6 1 1,2 1 1,2 1,2 2 1,2 1,2 1 1,2 3 1,2 1.6 1 1,2 4 1.4 1,2 1 1,2 5 1.5 1.75 1 1.5 6 1,2 1 1 1,2 7 1.6 1,2 1 1,2 8 2 1.5 1 1.5 9 1,2 1.6 1 1,2 10 2.25 1.25 1 1.5

According to table 3, with the second criterion K _i ≥ 1.75, schemes No. 5, 8, 10 will be potentially unreliable. The final conclusion for two criteria simultaneously is as follows: schemes No. 5, 8 will be potentially unreliable.

Tests conducted over 500 hours at maximum load and elevated temperature of 70°C confirmed the obtained results.

The technical result of the claimed method is an increase in the reliability of the results of rejecting potentially unreliable integrated circuits using the measurement of the signal propagation delay time due to the fact that the value of the signal propagation delay time is measured at two supply voltages, a coefficient K _i is introduced, equal to the ratio of the value of the signal propagation delay time at a given input to the value of the minimum delay time value, taken as a unit, and the rejection of potentially unreliable circuits is carried out according to two criteria.

Claims (1)

A method for rejecting potentially unreliable digital integrated circuits (DICs) by the signal propagation delay time, according to which, on a batch of digital integrated circuits in which it is necessary to identify and then separate potentially unreliable circuits, the signal propagation delay time is measured at all inputs of the IC, characterized in that the first criterion for rejecting potentially unreliable ICs is established by the absolute value of the signal propagation delay time, which does not exceed the established value, at a supply voltage close to the critical one, then the signal propagation delay time is measured on the same circuits and inputs at the nominal supply voltage and a table is constructed, where for each digital integrated circuit the minimum value of the signal propagation delay time when turning off one of the inputs is taken as one, and for the remaining inputs the coefficient Ki is recorded, equal to the ratio of the signal propagation delay time value at a given input to the value of the minimum delay time value taken as one, and the second criterion for rejecting is selected by the value of the coefficient Ki, which does not exceed the established value, and those digital integrated circuits for which the same two criteria are considered potentially unreliable.