RU2829493C2 - Shape-adaptive discrete cosine transform for geometric partitioning with adaptive number of regions - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to decoding means. Receiving, by means of a decoder, a bit stream containing an encoded current image, including a coding tree unit and signalling information, wherein the signalling information includes a set of sequence parameters comprising a flag indicating that a geometric partitioning is applied to the bitstream, a first geometric partitioning index information enabling determination, by a decoder, for a first straight line of a partitioning boundary in a coding tree unit, a first end point at the boundary of the coding tree unit and a second end point at the boundary of the coding tree unit, second geometric partitioning index information providing the determination, by a decoder, for a second straight line of the partition boundary in a coding tree unit, a first end point on the boundary of the coding tree unit and a second end point on the first straight line of the partition boundary. Current unit of the coding tree is decoded using the first geometric partitioning index information and second geometric partitioning index information for reconstructing the coding tree unit, wherein the reconstructed coding tree unit is partitioned into three non-rectangular areas of the first and second partitioning boundary straight lines.

EFFECT: reduction of blocking artefacts at the boundaries of the object.

3 cl, 6 dwg

Description

Field of technology to which the invention relates

The present invention relates generally to the field of video compression. In particular, the present invention is directed to a shape-adaptive discrete cosine transform for geometric partitioning with an adaptive number of regions.

State of the art

A video codec may include electronic circuitry or software that compresses or decompresses digital video. It may convert uncompressed video to a compressed format and vice versa. In the context of video compression, a device that compresses video (and/or performs some of its functions) may generally be called an encoder, and a device that decompresses video (and/or performs some of its functions) may be called a decoder.

The compressed data format may conform to a standard video compression specification. The compression may be lossy, since the compressed video lacks some information that was present in the original video. The consequence of this may be that the decompressed video may be of lower quality than the original uncompressed video, since there is not enough information to accurately reconstruct the original video.

Complex relationships may exist between video quality, the amount of data used to represent the video (e.g., as determined by the bit rate), the complexity of encoding and decoding algorithms, sensitivity to data loss and errors, ease of editing, random access, end-to-end delay (e.g., lag), etc.

Disclosure of the essence of the invention

In one aspect, a decoder includes a circuit configured to receive a bit stream, determine a first region, a second region, and a third region of a current block in accordance with a geometric partitioning mode, and decode the current block using an inverse discrete cosine transform for each of the first, second, and third regions.

In another aspect, the decoder includes a circuit configured to receive a bit stream, determine a first region, a second region and a third region of a current block and determine, in accordance with a geometric partitioning mode from a signal contained in the bit stream, a coding transform type for decoding each of the first region, the second region and/or the third region, a coding transform type characterizing at least an inverse block discrete cosine transform and a shape-adaptive inverse discrete cosine transform, and decoding the current block, wherein decoding the current block includes using a specific transform type for the inverse transform for each of the first region, the second region and/or the third region.

In another aspect, the method includes receiving, by a decoder, a bit stream, determining a first region, a second region and a third region of a current block in accordance with a geometric partitioning mode, determining, from a signal contained in the bit stream, a coding transform type for decoding the first region, the second region and/or the third region, the coding transform type characterizing at least an inverse block discrete cosine transform or a shape-adaptive inverse discrete cosine transform, and decoding the current block, wherein decoding the current block includes using a certain transform type for the inverse transform for each of the first region, the second region and/or the third region.

The details of one or more embodiments of the subject matter of the invention described herein are set forth below in the accompanying drawings and in the description. Other features and advantages of the subject matter of the invention described herein will be apparent from the description and drawings and from the claims.

Brief description of the drawings

For purposes of illustrating the invention, the drawings show aspects of one or more embodiments of the invention. However, it should be understood that the present invention is not limited to the precise arrangements and instruments shown in the drawings, in which:

Fig. 1 is an illustration showing an example of a residual block (e.g., the current block) with exponential partitioning, where there are three segments with different prediction errors;

Fig. 2 is a block diagram of a system illustrating an example video encoder capable of performing an adaptive discrete cosine transform (SA-DCT) for geometric partitioning with an adaptive number of regions, which can reduce the complexity and processing performance of encoding and decoding video;

Fig.3 is a flow chart illustrating an exemplary process for coding video with SA-DCT for geometric partitioning with an adaptive number of regions;

Fig.4 is a block diagram of a system illustrating an example decoder configured to decode a bitstream using an SA-DCT for geometric partitioning with an adaptive number of regions;

Fig. 5 is a flow chart illustrating an exemplary process for decoding a bitstream using SA-DCT for geometric partitioning with an adaptive number of regions; and

Fig. 6 is a block diagram of a computing system that can be used to implement any one or more of the methodologies disclosed herein and any one or more portions thereof.

The drawings are not necessarily drawn to scale and may be illustrated using dashed lines, schematic representations and fragmentary views. In some cases, details may be omitted that are not necessary for understanding the embodiments or that obscure other details. The same reference numerals in different drawings designate the same elements.

Implementation of the invention

Embodiments presented in this disclosure relate to encoding and decoding blocks in a geometric partition, where not all blocks are necessarily rectangular. Embodiments may include and/or may be configured to perform encoding and/or decoding using discrete cosine transforms (DCTs) and/or inverse DCTs. In some embodiments presented herein, the selection of a DCT is performed depending on the information content of the geometrically partitioned blocks. In some existing approaches to video encoding and decoding, all blocks are rectangular in shape, and the residual is encoded using a regular block DCT (B-DCT) for the entire rectangular block. However, in a geometric partition, where a block may be divided into multiple non-rectangular regions, using a regular B-DCT may inefficiently represent the underlying pixel information for some blocks and may require excessive computational resources to perform. In some implementations of the present subject matter, when using a geometric partitioning mode, the encoder may use a shape-adapted DCT (SA-DCT) as an alternative to or in addition to the B-DCT. In some embodiments, the encoder may select between the B-DCT and the SA-DCT for each region of a block, such as a geometrically partitioned block, based on the prediction error level of that region; the selection may be signaled in the bitstream for use in decoding. By encoding and/or decoding a non-rectangular region using the B-DCT or the SA-DCT and signaling such a selection, the bitrate may be reduced since the residual may be represented more efficiently, and as a result, the computational resources required to perform the processing may be reduced. The present subject matter is applicable to relatively large blocks, such as, for example, 128x128 or 64x64 blocks. In some implementations, the geometric partitioning may include partitioning the current block into an adaptive number of regions, such as three or more regions for a given current block; The DCT transform type (e.g. B-DCT or SA-DCT) can be signaled for each domain.

In an embodiment, the B-DCT may be a DCT performed using an invertible NxN matrix on an NxN block of numerical values, such as, but not limited to, the chroma and/or brightness values of a corresponding NxN pixel array. For example and as a non-limiting example, where an NxN matrix X is to be transformed, the "DCT-I" transform allows each element of the transformed matrix to be calculated as:

For k = 0,…, N-1. As an additional non-limiting example, the "DCT-II" transformation allows the transformed matrix values to be calculated as:

For k = 0,…, N-1. As an illustrative example, where the blocks are 4x4 pixel blocks, the generalized discrete cosine transform matrix may include a generalized discrete cosine transform matrix II of the form:

T =

where a is equal to ½, b is equal to , and c is equal to .

Some implementations may use an integer approximation of the transform matrix, which can be used for efficient hardware and software implementations. For example, if the blocks are 4x4 pixel blocks, the generalized discrete cosine transform matrix may include a generalized discrete cosine transform matrix II of the form:

T _INT = .

The inverse B-DCT can be calculated by multiplying the second matrix using the same NxN transformation matrix; the resulting result can be normalized to restore the original values. For example, the inverse DCT-I can be multiplied by 2/(N-1) to normalize.

The SA-DCT may be performed on a non-rectangular array of pixels. In an embodiment, the SA-DCT may be computed by performing a one-dimensional version of the DCT, such as DCT-I, DCT-II, etc., against vectors representing vertical columns of pixel values in the shape of interest, then grouping the resulting values into horizontal vectors and performing the one-dimensional DCT a second time, wherein the second DCT may result in the completion of the transformation of the pixel values. The variations of the SA-DCT may be further scaled and/or normalized with coefficients to correct for average weighting defects and/or non-orthonormalized defects introduced by the above-mentioned transformation, quantizing the output signals of the above-mentioned transformation, and/or inverting the output signals of the transformation and/or quantized output signals of the transformation. Further adjustments may be performed, without limitation, in advance of the above-mentioned SA-DCT process by subtracting an individual average value of the object image region from each pixel value or a scaled version thereof, possibly in combination with one or another of the scaling processes applied before and/or after the transform, quantization and/or inverse transform. Those skilled in the art, upon reading the entire present disclosure, will be aware of various alternative or additional variations of the SA-DCT process that may be applied in accordance with the above description.

Motion compensation may include an approach to predicting a video frame or part thereof given previous and/or future frames by taking into account the motion of the camera and/or objects in the video containing and/or represented by the current, previous and/or future frames. Motion compensation may be used in encoding and decoding video data for video compression, such as encoding and decoding using the Moving Picture Experts Group (MPEG)-2 standard (also called Advanced Video Coding (AVC)). Motion compensation allows a picture to be described in terms of a transformation of a reference picture into a current picture. A reference picture may be a previous or future picture in time compared to the current picture. When pictures can be accurately synthesized from previously transmitted and/or stored pictures, the compression efficiency can be improved.

Block partitioning used in this disclosure may relate to a method of coding video for finding areas of similar motion. Some form of block partitioning can be found in video codec standards, including MPEG-2, H.264 (also called AVC or MPEG-4 Part 10) and H.265 (also called High Efficiency Video Coding (HEVC)). In example approaches to block partitioning, non-overlapping blocks of a video frame can be divided into rectangular sub-blocks to find block partitions that contain pixels with similar motion. This approach can work well when all pixels in a block partition have similar motion. The motion of pixels in a block can be determined relative to previously encoded frames.

A shape-adaptive DCT and/or a B-DCT can be effectively used in geometric partitioning with an adaptive number of regions. Figure 1 is an illustration showing a non-limiting example of a residual block (e.g., the current block) 100 of size 64x64 or 128x128 with a geometric partition, where there are three segments, S0, S1 and S2 with different prediction errors; although, in Figure 1, for illustrative purposes, a larger or smaller number of segments can be alternatively or additionally used. The current block can be geometrically partitioned according to two linear segments (P1P2 and P3P4), which can partition the current block into three regions S0, S1 and S2. In this example, S0 can have a relatively high prediction error, while S1 and S2 can have a relatively lower prediction error. For the segment S0 (also called a region), the encoder can select and use the B-DCT to encode the residual. For the segments S1 and S2 with low prediction error, the encoder can choose and use SA-DCT. The choice of residual encoding transform can be based on the prediction error (e.g., the size of the residual). Since the SA-DCT algorithm is relatively simpler in terms of complexity and does not require as much computation as B-DCT, using SA-DCT for encoding with lower prediction error can reduce the complexity and processing performance of video encoding and decoding.

Accordingly, still referring to Fig. 1, the SA-DCT may be signaled as an additional transform choice for the full-block DCT for segments with low prediction errors. What is considered a low or high error may be a parameter that may be set at the encoder and may vary depending on the application. The transform type choice may be signaled in the bitstream. At the decoder, the bitstream may be analyzed and, for a given current block, the residual may be decoded using the transform type that is signaled in the bitstream. In some implementations, a number of coefficients associated with the transform may be alternatively or additionally signaled in the bitstream.

In more detail, still referring to Fig. 1, geometric partitioning with an adaptive number of regions may include video encoding and decoding technologies in which a rectangular block is further partitioned into two or more regions, which may be non-rectangular. For example, Fig. 1 illustrates a non-limiting example of geometric partitioning at the pixel level with an adaptive number of regions. An exemplary rectangular block 100 (which may have a width of M pixels and a height of N pixels, denoted as MxN pixels) may be partitioned along a line segment P1P2 and P3P4 into three regions (S0, S1 and S2). When pixels in S0 have similar motion, a motion vector may describe the motion of all pixels in this region, wherein the motion vector may be used to compress region S0. Similarly, when pixels in region S1 have similar motion, an associated motion vector may describe the motion of pixels in region S1. Similarly, when the pixels in the region S2 have similar motion, the associated motion vector may describe the motion of the pixels in the region S2. Such a geometric partition may be signaled to a receiver (e.g., a decoder) by encoding positions P1, P2, P3, P4 and/or representations of these positions, for example, without limitation, using coordinates such as polar coordinates, Cartesian coordinates, etc., indices into given patterns, or other characteristics of partitions) in the video bitstream.

Still referring to Fig. 1, when encoding video data using pixel-level geometric partitioning, a line segment P1P2 (or more specifically, points P1 and P2) can be determined. To determine the line segment P1P2 (or more specifically, points P1 and P2) that best partitions a block when using pixel-level geometric partitioning, the possible combinations of points P1 and P2 depend on the values of M and N, which are the block width and height. For a block of size MxN, there are (M-1)x(N-1)x3 possible partitions. Thus, determining the correct partition can become a computationally expensive motion estimation task for all possible partitions, which can increase the amount of time and/or increase the computing power required to encode the video, compared to encoding using rectangular partitioning (e.g., without pixel-level geometric partitioning). What constitutes the best or correct partition may be defined according to a metric and may vary from implementation to implementation.

In some implementations, still with reference to Fig. 1, the partitioning occurs iteratively, in the sense that a first partition may be determined (e.g., a line P1P2 and associated regions are determined) to form two regions, and then one of these regions is further partitioned. For example, the partitioning described with reference to Fig. 1 may be performed to partition a block into two regions. One of these regions may be further partitioned (e.g., to form a new region S1 and region S2). The process may continue to perform geometric partitioning at the block level until a stopping criterion is reached.

2 is a block diagram of a system illustrating an example video encoder 200 configured with SA-DCT and/or B-DCT for geometric partitioning with an adaptive number of regions that can reduce complexity and processing performance in encoding and decoding video. The example video encoder 200 receives an input video 205 that may be initially segmented or partitioned according to a processing scheme, such as a tree-structured macroblock partitioning scheme (e.g., a quadtree plus a binary tree). An example of a tree-structured macroblock partitioning scheme may include partitioning a picture frame into large block elements called coding tree units (CTUs). In some implementations, each CTU may be further partitioned one or more times into a number of sub-blocks called coding units (CUs). The final result of this partitioning may include a group of sub-blocks that may be called prediction units (PUs). In addition, transform units (TUs) may also be used. Such a partitioning scheme may include performing geometric partitioning with an adaptive number of regions in accordance with certain aspects of the present subject matter.

Continuing with reference to Fig. 2, an example video encoder 200 includes an intra-block prediction processor 215, a motion estimation/compensation processor 220 (also called an inter-prediction processor) configured to support geometric partitioning with an adaptive number of regions, a transform/quantization processor 225, an inverse quantization/inverse transform processor 230, a loop filter 235, a decoded picture buffer 240, and an entropy encoding processor 245. In some implementations, the motion estimation/compensation processor 220 may perform geometric partitioning. Bitstream parameters that signal geometric partitioning modes may be input to the entropy encoding processor 245 for inclusion in the output bitstream 250.

In the process of operation, still referring to Fig. 2, for each block of the frame of the input video 205, it can be determined whether the block is to be processed by intra-block picture prediction or by using motion estimation/compensation. The block can be provided to the intra-block prediction processor 210 or the motion estimation/compensation processor 220. If the block is to be processed by intra-block prediction, the intra-block prediction processor 210 can perform processing to output a predictor. If the block is to be processed by motion estimation/compensation, the motion estimation/compensation processor 220 can perform processing including using a geometric partition to output a predictor.

Still referring to Fig. 2, a residual can be generated by subtracting a predictor from an input video. The residual can be received by a transform/quantization processor 225, which can determine whether a prediction error (e.g., the size of the residual) is considered a "high" or "low" error (e.g., by comparing the size or error metric of the residual with a threshold). Based on the determination, the transform/quantization processor 225 can select a transform type, which can include a B-DCT and an SA-DCT. In some implementations, the transform/quantization processor 225 selects a B-DCT transform type where the residual is considered to have a high error, and selects a SA-DCT transform type where the residual is considered to have a low error. Based on the selected transform type, the transform/quantization processor 225 can perform transform processing (e.g., an SA-DCT or a B-DCT) to create coefficients that can be quantized. The quantized coefficients and any associated signaling information (which may include the selected transform type and/or the number of coefficients used) may be provided to the entropy encoding processor 245 for entropy encoding and including them in the output bitstream 250. The entropy encoding processor 245 may support encoding of signaling information related to the SA-DCT for a geometric partition with an adaptive number of regions. In addition, the quantized coefficients may be provided to the inverse quantization/inverse transform processor 230, which may produce pixels that may be combined with a predictor and processed by a loop filter 235, the output of which is stored in a decoded picture buffer 240 for use by a motion estimation/compensation processor 220, which is capable of supporting a geometric partition with an adaptive number of regions.

Referring now to Fig. 3, a flow chart of a process flow is shown illustrating an example process 300 for coding video with SA-DCT for geometric partitioning with an adaptive number of regions, which allows reducing the complexity and processing performance of encoding and decoding video. In step 310, a video frame can undergo an initial block segmentation, for example, using a macroblock partitioning scheme with a tree structure, which can include partitioning a picture frame into CTUs and CUs. In step 320, a block can be selected for geometric partitioning. According to a rule regarding a metric, the selection can include identifying that the block is to be processed according to a geometric partitioning mode. In step 330, the selected block can be partitioned into three or more non-rectangular regions according to the geometric partitioning mode.

At step 340, still referring to Fig. 3, a transform type (which is also referred to as a transform type) can be determined for each geometrically partitioned region. This step can include determining whether a prediction error (e.g., the size of the residual) is considered a "high" or "low" error (e.g., by comparing the size or metric of the residual error with a threshold). Based on the determination, a transform type can be selected, for example, using a "quadtree plus binary tree" decision process, as described below, where this transform type can include, but is not limited to, a B-DCT or an SA-DCT. In some implementations, a B-DCT transform type is selected when the residual is considered to have a high error, and an SA-DCT transform type is selected where the residual is considered to have a low error. Based on the selected transform type, transform processing (e.g., SA-DCT or B-DCT) can be performed to generate coefficients that can be quantized.

At step 350, still referring to Fig. 3, the determined type of transformation may be signaled in the bitstream. The transformed and quantized residual may be included in the bitstream. In some implementations, the number of transformation coefficients may be signaled in the bitstream.

4 shows a block diagram of a system illustrating a non-limiting example of a decoder 400 configured to decode a bitstream 470 using a DCT, including but not limited to an SA-DCT and/or a B-DCT, for geometric partitioning with an adaptive number of regions, which allows reducing the complexity and processing performance of video encoding and decoding. The decoder 400 includes an entropy decoder processor 410, an inverse quantization and inverse transform processor 420, a deblocking filter 430, a frame buffer 440, a motion compensation processor 450, and an intra-block prediction processor 460. In some implementations, the bitstream 470 includes parameters that signal a geometric partitioning mode and a transform type. In some implementations, the bitstream 470 includes parameters that signal a number of transform coefficients. The motion compensation processor 450 may reconstruct pixel information using geometric partitioning as described herein.

In operation and still referring to Fig. 4, the bit stream 470 can be received by the decoder 400 and input to the entropy decoder processor 410, which can entropy decode the bit stream into quantized coefficients. The quantized coefficients can be provided to the inverse quantization and inverse transform processor 420, which can determine the type of encoding transform (for example, B-DCT or SA-DCT) and perform inverse quantization and inverse transform according to the determined type of encoding transform to create a residual signal. In some implementations, the inverse quantization and inverse transform processor 420 can determine the number of transform coefficients and perform the inverse transform according to the determined number of transform coefficients.

Still referring to Fig. 4, the residual signal can be added to the output of the motion compensation processor 450 or the intra-block prediction processor 460 according to the processing mode. The output of the motion compensation processor 450 and the intra-block prediction processor 460 can include a prediction of a block based on a previously decoded block. The sum of the prediction and the residual can be processed by the deblocking filter 430 and stored in the frame buffer 440. For a given block (e.g., a CU or PU), when the bitstream 470 signals that the partitioning mode is a geometric partition at the block level, the motion compensation processor 450 can construct a prediction based on the geometric partitioning approach described in this document.

Fig. 5 is a flow chart illustrating an example process 500 for decoding a bitstream using SA-DCT for geometric partitioning with an adaptive number of regions that can reduce complexity and processing performance in video encoding and decoding. At step 510, a bitstream is received that may include a current block (e.g., CTU, CU, PU). Reception may include extracting and/or analyzing the current block and associated signaling information from the bitstream. The decoder may extract or determine one or more parameters characterizing the geometric partition. These parameters may include, for example, linear segment start and end indices (e.g., P1, P2, P3, P4); extracting or determining may include identifying and extracting the parameters from the bitstream (e.g., analyzing the bitstream).

At step 520, still referring to Fig. 5, the first region, the second region, and the third region of the current block may be determined in accordance with the geometric partitioning mode. The determination may include determining whether the geometric partitioning mode is enabled (e.g., "true") for the current block. If the geometric partitioning mode is not enabled (e.g., "false"), the decoder may process the current block using an alternative partitioning mode. If the geometric partitioning mode is enabled (e.g., "true"), three or more regions may be determined and/or processed.

In an optional step 530, still referring to Fig. 5, a type of encoding transformation may be determined. The type of encoding transformation may be signaled in the bitstream. For example, the bitstream may be analyzed to determine the type of encoding transformation, which may indicate a B-DCT or an SA-DCT. The determined type of encoding transformation may be intended for decoding the first region, the second region, and/or the third region.

At step 540, still referring to Fig. 5, the current block may be decoded. Decoding the current block may include using a certain type of transform for the inverse transform for each of the first region, the second region and/or the third region. Decoding may include determining associated motion information for each region and in accordance with the geometric partitioning mode.

Although several variants have been described in detail above, other modifications or additions are possible. For example, the geometric partitioning can be signaled in the bitstream based on rate-distortion decisions in the encoder. The coding can be based on a combination of regularly defined partitions (e.g., patterns), spatiotemporal partition prediction, and additional offsets. Each geometrically partitioned region can use motion-compensated or intra-block prediction. The boundary of the predicted regions can be smoothed before adding the residual.

In some implementations, a quadtree plus binary decision tree (QTBT) may be implemented. In QTBT, at the coding tree unit level, the QTBT partitioning parameters are dynamically derived to adapt to local characteristics without transmitting any overhead. Then, at the coding unit level, the decision tree structure of the joint classifier can eliminate unnecessary iterations and control the risk of false prediction. In some implementations, geometric partitioning with an adaptive number of regions may be available as an additional partitioning option, accessible at each QTBT leaf node.

In some implementations, the decoder may include a partition processor that produces a geometric partition for the current block and provides all partition-related information to dependent processes. The partition processor may directly influence motion compensation, since it may be performed on a segment-by-segment basis if the block is geometrically partitioned. In addition, the partition processor may provide shape information to the intra-block prediction processor and the transform coding processor.

In some implementations, additional syntax elements may be signaled at different hierarchical levels of the bitstream. An enable flag may be encoded in the sequence parameter set (SPS) to enable geometric partitioning with an adaptive number of regions for the entire sequence. In addition, a CTU flag may be encoded at the coding tree unit (CTU) level to indicate whether any coding units (CUs) use geometric partitioning with an adaptive number of regions. A CU flag may be encoded to indicate whether the current coding block uses geometric partitioning with an adaptive number of regions. Parameters that precisely define a linear segment within a block may be encoded. For each region, a flag may be decoded that may indicate whether the current region is inter- or intra-block predicted.

In some implementations, the minimum region size may be precisely defined.

The subject matter described herein provides numerous technical advantages. For example, some implementations of the present subject matter may provide for block partitioning that reduces complexity while increasing compression efficiency. In some implementations, blocking artifacts at object boundaries may be reduced.

It should be noted that any one or more aspects and embodiments described herein may be readily implemented using digital electronic circuits, integrated circuits, application-specific integrated circuits (ASICs) designed specifically for specific applications, computer hardware with field-programmable gate arrays (FPGAs), firmware, software, and/or combinations thereof, as implemented and/or implemented in one or more machines (e.g., one or more computing devices that are used as a user computing device for an electronic document, one or more server devices, such as a document server, etc.), programmed in accordance with the inventive ideas presented herein, as will be apparent to those skilled in the art of computer technology. These various aspects or features may include an implementation in one or more computer programs and/or software that are executable and/or interpretable in a programmable system that includes at least one programmable processor, which may be special-purpose or general-purpose and may be connected to receive data and instructions from a storage system and to transmit data and instructions to the storage system, to at least one input device and to at least one output device. The corresponding software coding can be easily prepared by skilled programmers based on the teachings of the present disclosure, as will be apparent to those skilled in the software field. The aspects and implementations discussed above using software and/or software modules may also include corresponding hardware to facilitate the implementation of computer-executable instructions of the software and/or software module.

Such software may be a computer program product that uses a machine-readable storage medium. A machine-readable storage medium may be any storage medium that is capable of storing and/or encoding a sequence of instructions for execution by a machine (e.g., a computing device) and that cause the machine to perform any of the methodologies and/or embodiments described in this document. Examples of a machine-readable storage medium include, but are not limited to, a magnetic disk, an optical disk (e.g., CD, CD-R, DVD, DVD-R, etc.), a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), a magnetic card, an optical card, a solid-state memory, EPROM, EEPROM, programmable logic devices (PLD), and/or any combinations thereof. Machine-readable storage medium, as used herein, is intended to include a single storage medium as well as a collection of physically separate storage media, such as, for example, a collection of compact discs or one or more hard disks in combination with computer memory. As used herein, the term machine-readable storage medium does not include temporary forms of signal transmission.

Such software may also include information (e.g., data) carried as a data signal on a carrier, such as a carrier. For example, computer-executable information may be included as a data-carrying signal embodied in the carrier, where the signal encodes a sequence of instructions or a portion thereof for execution by a machine (e.g., a computing device) and any associated information (e.g., data structures and data) that cause the machine to perform any of the methodologies and/or embodiments described herein.

Examples of a computing device include, but are not limited to, an e-book reader, a computer workstation, a terminal computer, a server computer, a portable device (e.g., a tablet computer, a smartphone, etc.), a web device, a network router, a network switch, a network bridge, any computer capable of executing a sequence of instructions specifying an action to be performed on that computer, and any combination thereof. In one example, a computing device may include and/or be included in a kiosk.

6 shows a schematic representation of one embodiment of a computing device in the form of an example computer system 600 that can execute a set of instructions for causing a control system to perform any one or more aspects and/or methodologies of the present disclosure. In addition, it is also contemplated that multiple computing devices can be used to implement a specially configured set of instructions that cause one or more devices to perform any one or more aspects and/or methodologies of the present disclosure. The computer system 600 includes a processor 604 and a memory 608 that communicate with each other and with other components via a bus 612. The bus 612 can include any of several types of bus structures, including, but not limited to, a memory bus, a memory controller, a peripheral bus, a local bus, and any combinations thereof that use any of a variety of bus architectures.

Memory 608 may include various components (e.g., computer-readable storage media), including, but not limited to, a random access memory component, a read-only component, and any combinations thereof. In one example, a basic input/output system (BIOS) 616, including basic routines that help transfer information between elements in computer system 600, such as during startup, may be stored in memory 608. Memory 608 may also include (e.g., stored on one or more computer-readable storage media) instructions (e.g., software) 620 that embody any one or more aspects and/or methodologies of the present disclosure. In another example, memory 608 may further include any number of program modules, including, but not limited to, an operating system, one or more application programs, other program modules, program data, and any combinations thereof.

The computing system 600 may also include a storage device 624. Examples of a storage device (e.g., storage device 624) include, but are not limited to, a hard disk drive, a magnetic disk drive, an optical disk drive in combination with an optical storage medium, a solid-state memory device, and any combinations thereof. The storage device 624 may be connected to the bus 612 via an appropriate interface (not shown). Examples of interfaces include, but are not limited to, SCSI, Advanced Attachment Technology (ATA), serial ATA, Universal Serial Bus (USB), IEEE 1394 (Firewire), and any combinations thereof. In one example, the storage device 624 (or one or more components thereof) may be connected via an interface to the computer system 600 (e.g., via an external port connector (not shown)). In particular, the memory device 624 and the associated computer-readable storage medium 628 may provide non-volatile and/or non-volatile storage of computer-readable instructions, data structures, program modules and/or other data for the computer system 600. In one example, the software 620 may reside, in whole or in part, on the computer-readable storage medium 628. In another example, the software 620 may reside, in whole or in part, in the processor 604.

The computing system 600 may also include an input device 632. In one example, a user of the computer system 600 may enter commands and/or other information into the computer system 600 via the input device 632. Examples of the input device 632 include, but are not limited to, an alphanumeric input device (e.g., a keyboard), a pointing device, a joystick, a game pad, an audio input device (e.g., a microphone, a voice response system, etc.), a cursor control device (e.g., a mouse), a touch pad, an optical scanner, a video capture device (e.g., a camera, a video camera), a touch screen, and any combinations thereof. The input device 632 may be interfaced to the bus 612 via any of a plurality of interfaces (not shown), including, but not limited to, a serial interface, a parallel interface, a game port, a USB interface, a FIREWIRE interface, a direct interface to the bus 612, and any combinations thereof. The input device 632 may include a touch screen interface, which may be part of the display 636 or be separate from it, as discussed further below. The input device 632 may be used as a user selection device for selecting one or more graphical representations in a graphical interface, as described above.

The user may also enter commands and/or other information into the computer system 600 via the storage device 624 (e.g., a removable disk, a flash disk, etc.) and/or the network interface device 640. A network interface device, such as the network interface device 640, may be used to connect the computer system 600 to one or more of a plurality of networks, such as the network 644, and to one or more remote devices 648 connected thereto. Examples of a network interface device include, but are not limited to, a network interface card (e.g., a mobile network interface card, a LAN card), a modem, and any combinations thereof. Examples of a network include, but are not limited to, a network (e.g., the Internet, an enterprise network), a local area network (e.g., a network associated with an office, building, campus, or other relatively small geographic area), a telephone network, a data network associated with a telephone/voice provider (e.g., a mobile phone provider's data and/or a telephone network), a direct connection between two computing devices, and any combinations thereof. A network, such as network 644, may use a wired and/or wireless communication mode. In general, any network topology may be used. Information (e.g., data, software 620, etc.) may be transmitted to and/or from computer system 600 using network interface device 640.

The computing system 600 may further include a video display adapter 652 for transmitting a displayed image to a display device, such as a display device 636. Examples of a display device include, but are not limited to, a liquid crystal display (LCD), a cathode ray tube (CRT), a plasma display, a light emitting diode (LED), and any combinations thereof. The display adapter 652 and the display device 636 may be used in combination with the processor 604 to provide a graphical representation of aspects of the present disclosure. In addition to the display device, the computer system 600 may include one or more other peripheral output devices, including, but not limited to, an audio speaker, a printer, and any combinations thereof. Such peripheral output devices may be connected to the bus 612 via a peripheral interface 656. Examples of a peripheral interface include, but are not limited to, a serial port, a USB connection, a Firewire connection, a parallel connection, and any combinations thereof.

The foregoing has described in detail illustrative embodiments of the present invention. Various modifications and additions can be made without departing from the spirit and scope of the present invention. The features of each of the various embodiments described above can be combined with features of other embodiments described, as appropriate, to provide a variety of combinations of features in associated new embodiments. Furthermore, while a number of specific embodiments have been described above, what has been described herein is merely illustrative of the application of the principles of the present invention. Furthermore, while specific methods herein may be illustrated and/or described as being performed in a particular order, the order of performance varies widely within the ordinary skill in achieving the embodiments disclosed herein. Accordingly, this description is intended to be used as an example only and does not otherwise limit the scope of the present invention.

In the above descriptions and claims, phrases such as "at least one of" or "one or more" may appear followed by a conjunctive list of elements or features. The term "and/or" may also appear in a list of two or more elements or features. Unless otherwise implicitly or clearly contradicted by the context in which it is used, such a phrase means any of the listed elements or features alone, or any of the listed elements or features in combination with any of the other listed elements or features. For example, each of the phrases "at least one of A and B," "one or more of A and B," and "A and/or B" means "A taken alone," "B taken alone," or "A and B together." A similar interpretation is also intended for lists of three or more items. For example, each of the phrases "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, and/or C" means "A taken alone," "B taken alone," "C taken alone," "A and B together," "A and C together," "B and C together," or "A and B and C together." In addition, the use of the term "based on" in the description above and in the claims means "based at least in part," so an unspecified feature or element is also permissible.

The subject matter described herein may be embodied in systems, devices, methods and/or articles depending on the desired configuration. The embodiments set forth in the preceding description do not represent all embodiments consistent with the subject matter described herein. Instead, they represent only some examples consistent with aspects related to the described subject matter. Although some embodiments have been described in detail above, other modifications or additions are possible. In particular, additional features and/or embodiments may be provided in addition to those set forth in this description. For example, the embodiments described above may be directed to various combinations and subcombinations of the disclosed features and/or combinations and subcombinations of several additional features disclosed above. In addition, the logical flows depicted in the accompanying drawings and/or described herein do not necessarily require the particular order shown or the sequential order to achieve the desired results. Other embodiments may fall within the scope of the following claims.

Claims (12)

1. A decoder comprising a circuit configured to: receiving a bit stream containing an encoded current picture, including a coding tree unit and signaling information, wherein the signaling information includes a sequence parameter set comprising a flag indicating that a geometric partitioning is applied to the bit stream, first geometric partitioning index information enabling a decoder to determine, for a first straight line of a partition boundary in the coding tree unit, a first end point on the boundary of the coding tree unit and a second end point on the boundary of the coding tree unit, second geometric partitioning index information enabling a decoder to determine, for a second straight line of a partition boundary in the coding tree unit, a first end point on the boundary of the coding tree unit and a second end point on the first straight line of a partition boundary; and decoding the coding tree unit using the first geometric partition index information and the second geometric partition index information to reconstruct the coding tree unit, wherein the reconstructed coding tree unit is divided into three non-rectangular regions by first and second straight partition boundary lines. 2. The decoder according to item 1, additionally comprising: an entropy decoder processor configured to receive a bit stream and decode the bit stream into quantized coefficients; an inverse quantization and inverse transform processor configured to process quantized coefficients, including performing an inverse discrete cosine transform in accordance with a specific type of coding transform; deblocking filter; frame buffer; and intra-block prediction processor. 3. A decoding method comprising the steps of: receiving, by a decoder, a bitstream containing an encoded current picture including a coding tree unit and signaling information, wherein the signaling information includes a sequence parameter set containing a flag indicating that a geometric partitioning is applied to the bitstream, first geometric partitioning index information enabling the decoder to determine, for a first straight line of a partition boundary in a coding tree unit, a first end point on the boundary of the coding tree unit and a second end point on the boundary of the coding tree unit, second geometric partitioning index information enabling the decoder to determine, for a second straight line of a partition boundary in a coding tree unit, a first end point on the boundary of the coding tree unit and a second end point on the first straight line of a partition boundary; and decoding the current coding tree unit using the first geometric partition index information and the second geometric partition index information to reconstruct the coding tree unit, wherein the reconstructed coding tree unit is divided into three non-rectangular regions by first and second straight partition boundary lines.