RU2815706C1 - Multifunctional diagnostic system - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering, in particular to automatic testing devices and can be used for testing custom VLSI at operating frequencies and verification of their designs on PLD during development. Multifunctional diagnostic system comprises a control computer with control consoles, a PCI_ Express port switch, a network ports switch, an external user network port, a JTAG control and monitoring port switch, a monitoring port switch and a group of K test modules. Each of the test modules comprises a manual control console, state display unit, reference frequency generator, test program non-volatile memory connection port, control PLD configuration control unit, configuration memory unit, non-volatile memory controller of test programs, non-volatile memory of test parameters setting subprograms, data and test results memory, temperature mode stabilization control unit and cooling fan rotation speed control unit, power control unit, programmable operating frequency generator, programmable exchange frequency generator, condition monitoring unit, unit of controlled power supplies, contacting device with fan and cooling radiator, unit of integrated logic analyser of state and control PLD. Control PLD comprises a logic analyser unit, a signature analyser unit and a hardware test action generation unit implemented on the control PLD resources.

EFFECT: broader functional capabilities of testing and high reliability of control when testing custom VLSI.

1 cl, 1 dwg

Description

TECHNICAL FIELD

The invention relates to the field of computer technology, in particular to automatic testing devices and can be used for testing custom VLSI chips at operating frequencies and verifying their FPGA designs during the development process.

BACKGROUND ART

When creating high-performance computing systems, custom VLSIs are increasingly used. With an increase in the computing power of VLSI, as well as the presence of large-volume RAM modules in them, it becomes especially important, in addition to reducing the overall time of their development and production, to reduce labor intensity and increase the reliability of performance monitoring before installing VLSI on computing modules, which is especially important in the production of large batches of custom VLSI circuits. Also, due to the high cost of custom-made VLSIs, it becomes relevant to sort them according to technical characteristics, for example, maximum frequencies and failure-free operation temperatures, to ensure the possibility of using functional components under various acceptable conditions.

A device for diagnostic monitoring of checks is known (RU No. 2631989 C1, IPC G06F 11/273, declared 09.22.2016, published 09.29.2017 Bulletin No. 28), containing a test generator, a model of the test object, standard micromodules, a switch, a comparison circuit, reference control object, counter for the number of detected faults, counter for the number of entered faults, divider, random number sensor, fault input unit, control unit, delay element, two OR elements, counter for setting the number of faults, control trigger, AND element, test generator control unit.

The disadvantage of this device for diagnostic monitoring of checks is the lack of the ability to verify designs of control objects during development, as well as the complexity of sorting by frequency characteristics and temperature groups when monitoring their performance.

The reason preventing the achievement of a technical result is the organization of a testing system based only on comparing the reactions of control objects with the reactions of reference objects.

Known microcircuit testers FORMULA-HF and FORMULA-HF-ULTRA are designed for functional and parametric testing of VLSI circuits (http://www.form.ru/products/chip/), containing an input interface for interaction with the control computer, a memory of test vectors of influences and memory of reaction vectors, testing control unit, blocks of input and output signal level converters, a clamping device board and a set of adapter boards for installing controlled VLSI.

The disadvantage of these microcircuit testers is the lack of ability to monitor the performance of VLSI at operating frequencies and the lack of the ability to verify designs of test objects during their development.

The reason preventing the achievement of a technical result is the limitation of the VLSI operating frequency by the supply cycle of test vectors of influences.

The closest device to the claimed invention, in terms of the set of characteristics, is the tester-verifier adopted as a prototype (RU No. 2795419, IPC G01R 31/3177, G06F 11/273, declared 10.28.2022, published 05.03.2023 Bulletin No. 13), containing external port 1 status monitoring, external port 2 network interface, external port 3 PCI Express interface, external port 4 JTAG monitoring and control, reference frequency generator 5, memory 6 of data and test results, programmable exchange frequency generator 7, control FPGA 8, memory 9 starting configuration, working configuration memory 10, programmable VLSI operating frequency generator 11, condition monitoring unit 12, contact device 13 with fan and VLSI cooling radiator, VLSI controllable power supply unit 14 and VLSI power control unit 15, non-volatile memory 18 parameter setting routines tests, controller 19 of non-volatile memory of test programs, external port 20 for connecting non-volatile memory of test programs, status display unit 21, manual control console 22, configuration control unit 23 of the control FPGA 8, temperature stabilization control unit 24, configuration memory 25 of the offline mode of the control FPGA 8 and block 26 for controlling the rotation speed of the cooling fan.

The disadvantages of this tester-verifier for custom VLSIs are the low reliability of monitoring the performance of large batches of custom VLSIs before installing them on computing modules, the complexity of detailed identification of the nature of failures when verifying projects and monitoring the performance of custom VLSIs, as well as the complexity of replicating tests between testers.

The reasons preventing the achievement of a technical result are a significant increase in testing time to increase the reliability of VLSI control, the lack of ability to monitor the state of the FPGA during verification of projects and VLSI at frequencies above the exchange frequency, as well as the lack of a common (central, unified) maintenance system.

OBJECTIVE OF THE INVENTION

The problem to be solved by the proposed invention is to create a multifunctional diagnostic complex for carrying out functional monitoring of custom VLSI systems, verifying VLSI projects by users in the process of their development and performing operational (high-speed) and high-quality (with high reliability of fault determination) performance monitoring of large batches of custom-made ones. VLSI.

The technical result of the proposed invention is to expand the testing functionality, reduce the duration and increase the reliability of control when testing custom VLSI circuits.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result when implementing the invention is achieved by the fact that the multifunctional diagnostic complex contains a control computer 1 with management consoles, a switch of 2 PCI_Express ports, a switch of 3 network ports, an external network port of 4 users, a switch of 6 JTAG control and management ports, a switch of 7 monitoring ports and a group of K test modules 5 ₁ , ..., 5 _K , each of which contains a manual control console 8, a status display unit 9, a reference frequency generator 10, a port 11 for connecting non-volatile memory of test programs, a control unit 12 for controlling the configuration of the control FPGA, a memory unit 13 configurations, controller 14 non-volatile memory of test programs, non-volatile memory 15 subroutines for setting test parameters, memory 20 of data and test results, temperature stabilization control unit 21 and cooling fan speed control unit, power control unit 22, programmable operating frequency generator 23, programmable generator 24 exchange frequencies, a state monitoring unit 25, a controlled power supply unit 26, a contact device 27 with a fan and a cooling radiator, an integrated logic analyzer unit 30 and a control FPGA 16, which contains a logic analyzer unit 17, a signature analyzer unit 18 and a hardware unit 19 generation of test effects, implemented on the resources of the control FPGA 16,

Moreover, the control computer 1 with management consoles is connected to a switch of 3 network ports, to a switch of 6 JTAG control and management ports and to a switch of 2 PCI Express ports, which is connected to the control FPGAs of 16 test modules 5 ₁ , ..., 5 _K , and the switch of 3 network ports, connected to an external network port of 4 users, to control FPGAs of 16 test modules 5 ₁ , ..., 5 _K and to a switch 7 monitoring ports, which is connected to blocks 25 for monitoring the state of test modules 5 ₁ , ..., 5 _K , and a switch 6 JTAG monitoring and control ports are connected to block 17 of the logic analyzer of the control FPGA 16 test modules 5 ₁ , ..., 5 _K and to block 30 of the integrated logic state analyzer, which is connected to a programmable generator 23 of the operating frequency and connected to the control and data exchange bus 29, which connects the contacting device 27 and the control FPGA 16 test modules 5 ₁ , ..., 5 _K ,

In addition, the contacting device 27 of test modules 5 ₁ , ..., 5 _K is connected to a programmable exchange frequency generator 24, to a temperature stabilization control unit 21 and cooling fan rotation speed control unit, to a test module status monitoring unit 25, and to a controllable power supply unit 26 and with a configuration bus 28 with a control FPGA 16, which is connected to a temperature stabilization control unit 21 and a cooling fan rotation speed control unit, with a power control unit 22, with a memory 20 of data and test results, with a non-volatile memory 15 subroutines for setting test parameters, with reference frequency generator 10, with a programmable operating frequency generator 23, with a programmable operating frequency generator 24, a monitoring unit 25, with a configuration control unit 12, with a non-volatile test program memory controller 14, with a manual control console 8 and with a status display unit 9, which connected to the manual control console 8, which is connected to the configuration control unit 12, connected to the configuration memory unit 13,

in addition, the condition monitoring unit 25 is connected to the temperature stabilization control unit 21 and the cooling fan rotation speed control unit and to the controlled power supply unit 26, which is connected to the power control unit 22,

Moreover, the controller 14 of the non-volatile memory is connected to port 11 for connecting the non-volatile memory of test programs, and the operating frequency generator 23 is connected to the logic analyzer block 17, which, together with the signature analyzer block 18 and the hardware generation of test actions block 19, is connected inside the control FPGA 16 to the control bus 29 and data exchange.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a functional diagram of a multifunctional diagnostic complex.

In Fig. 1 and in the text the following abbreviations and symbols are used:

KU - contacting device with a fan and cooling radiator;

1 - control computer with control consoles;

2 - PCI_Express port switch;

3 - network port switch;

4 - external network port of the user network; 5 ₁ , …, 5 _K - group of K test modules;

6 - switch of JTAG control and management ports;

7 - monitoring port switch;

8 - manual control console;

9 - status display block;

10 - reference frequency generator;

11 - port for connecting non-volatile memory of test programs;

12 - control unit for configuring the control FPGA;

13 - configuration memory block;

14 - controller of non-volatile memory of test programs;

15 - non-volatile memory of subroutines for setting test parameters;

16 - control FPGA;

17 - logic analyzer block;

18 - signature analyzer block;

19 - hardware generation unit for test actions;

20 - memory of data and test results;

21 - control unit for stabilizing the temperature regime and controlling the rotation speed of the cooling fan;

22 - power control unit;

23 - programmable operating frequency generator;

24 - programmable exchange frequency generator;

25 - condition monitoring unit;

26 - block of controlled power supplies;

27 - contact device with fan and cooling radiator;

28 - configuration bus;

29 - control and data exchange bus;

30 - block of integrated logic state analyzer.

DETAILED DESCRIPTION OF THE INVENTION

Increasing the reliability of VLSI performance monitoring and reducing the labor intensity of their monitoring are always in conflict.

To increase the reliability of VLSI performance monitoring, it is necessary to increase the length of test sequences, which, in turn, increases both the preparation time of test sequences and the time of VLSI testing itself.

This contradiction in the proposed multifunctional diagnostic complex is resolved as follows.

Increasing the reliability of control is carried out by increasing the length of test sequences, but at the same time reducing the time for data delivery and processing of test results. Reducing the time for data delivery is achieved through hardware generation of the latter. The time for processing test results is reduced by comparing not all result vectors with the standard, but only the signature - the checksum at the end of the test. This effect is especially noticeable when testing VLSI internal memories with special, regular and random codes. The most effective signature analyzers for these purposes are devices implemented on shift registers with trivial polynomials in feedback, for example, a signature analyzer (SU No. 1661767 A1, IPC G06F 11/00, announced 07.17.1989, published 07.07.1991 Bulletin No. 25 ).

Signature analyzers are capable of operating at high frequencies, do not require large hardware costs for their implementation and can be implemented on the internal resources of control FPGAs 16. In addition, pseudo-random data generators can also be implemented based on signature analyzers when the latter are implemented in hardware.

The development of reference signatures for various test sets of input data is carried out both on a software model for memories with direct access to input and output, and on a hardware model at the stage of verification of custom VLSI projects on FPGAs, in the case when internal data memories do not have direct outputs from VLSI, but accessible through processing and memory devices. In the latter case, developing reference signatures on a program model for long test data sequences is difficult due to the complexity of the processing device algorithms.

To further increase the completeness of testing custom VLSIs, the development of reference signatures for additional test sets of input data is carried out on the so-called reference VLSIs. Reference VLSIs should be considered those that, at the stage of monitoring trial (“pilot”) VLSI batches, satisfied all the tests of functional and diagnostic control, and which have the same signatures developed for additional test sets of input data.

The proposed multifunctional diagnostic complex allows users connected to it via an external network port 4, using a control computer 1 with control consoles, to remotely verify projects of custom-developed VLSI on FPGAs installed in a contact device 27 with a fan and a cooling radiator for test modules 5 ₁ , ..., 5 _K , as well as develop and debug tests for input control of the performance of large batches of custom VLSI, including reference signatures for additional test sets of input data.

The control computer 1 with control consoles is designed to provide users with exclusive access to test modules 5 ₁ , ..., 5 _K for executing test, monitor and utility programs when verifying projects of developed custom VLSIs, developing and debugging tests, as well as monitoring the performance of custom VLSIs.

In addition to the control computer 1 with control consoles, the multifunctional diagnostic complex includes K of the same type test modules 5 ₁ , ..., 5 _K , which can operate in various modes under the control of the control computer 1 with control consoles, to which they are connected through the corresponding port switches 2, 3, 6 and 7.

PCI_Express port switch 2 is designed to organize high-speed interaction of user test programs on the control computer 1 with control consoles with test modules 5 ₁ , ..., 5 _K.

Network switch 3 is designed to organize user interaction with the control computer 1 with control consoles and test modules 5 ₁ , ..., 5 _K via external network port 4, as well as the control computer 1 with control consoles and test modules 5 ₁ , ..., 5 _K c monitoring switch 7.

A switch of 6 JTAG ports is designed to provide user access to the control FPGA 16 and the FPGA for verification of VLSI designs, installed in a control room with a fan and a cooling radiator 27 for configuring the FPGA and interacting with the logic analyzer block 17 and the integrated logic analyzer block 30 using CAD FPGA tools.

The switch 7 monitoring ports is designed to implement the control computer 1 with control consoles for monitoring the state (temperature, supply voltage) of the tested custom VLSI and FPGA, intended for verification of VLSI projects, test modules 5 ₁ , ..., 5 _K.

Logic analyzer block 17 is designed to record the current timing diagrams of the interaction of the control FPGA 16 with VLSI or FPGA for verification of VLSI designs installed in a control unit with a fan and cooling radiator 27, for detailed identification of the nature of failures during testing.

Block 30 of the integrated logic state analyzer is designed to record the current time diagrams of interaction of the FPGA for verification of VLSI projects installed in the control unit with a fan and cooling radiator 27, with the control FPGA 16 for detailed identification of the nature of failures when debugging VLSI projects.

Block 18 of hardware generation of test effects is designed to generate various required test data sets of large length, in order to increase the reliability of testing custom VLSI, and reduce the overall testing time by reducing data exchange operations with the control computer 1 with control consoles.

Block 19 of the signature analyzer is designed to generate current control signatures of results on test data sets of large length in order to increase the reliability of testing custom VLSI and reduce the overall testing time by reducing data exchange operations with the control computer 1 with control consoles.

The control FPGAs 16 test modules 5 ₁ , ..., 5 _K are designed to execute a program loaded from the memory 13 configurations, connected to it through the configuration control unit 12, when the power is turned on, or loaded through the JTAG switch 6 from the control computer 1 with control consoles.

Memory 13 configurations is intended for storage in the corresponding (of the same name) sections of the starting, working and autonomous configurations, loaded into the control FPGA 16 via the configuration control unit 12, depending on the operating modes of the test modules 5 ₁ , ..., 5 _K .

The starting configuration of the control FPGA 16 is loaded when the power is turned on and provides configuration of the programmable operating frequency generator 23, the programmable exchange frequency generator 24, control of the controllable power supply unit 26 by interacting with the power control unit 22. In addition, the start program of the control FPGA 16 provides support for interaction with the control computer 1 with management consoles via the network interface, the PCI_Express interface, rewriting the configuration memory block 13 and implements the execution of the reconfiguration command of the control FPGA 16.

The working configuration of the control FPGA 16 implements the same as the starting one, and also provides current exchange with memory 20 of data and test results and the current interface for interaction via the control bus 29 and data exchange through the contacting device 27 with the custom VLSI or FPGA being tested (at the verification stage custom VLSI projects). In addition, if necessary, it provides recording of the program in VLSI and configuration of the FPGA installed in KU 27 via configuration bus 28 at the stage of verification of VLSI projects.

The autonomous configuration of the control FPGA 16 is designed to work in standalone mode, and implements the same as the working configuration with the exception of interaction with the control computer 1 with control consoles via the PCI_Express interface, but ensures the operation of the manual control console 8. In addition, this program provides support for the appropriate interfaces for interaction of the control FPGA 16 with the non-volatile memory 15 of the subroutines for setting test parameters, with the status display unit 9, with the non-volatile memory controller 14, to which the external memory of test programs is connected via port 11, and with the control unit 21 temperature stabilization.

Memory 20 of data and testing results is intended for storing initial vectors of influences and reference vectors of reactions, as well as storing the results of VLSI testing or verification of their designs.

The programmable exchange frequency generator 24 is designed to set the exchange frequency between the custom VLSI being tested and the control FPGA 16.

The programmable operating frequency generator 23 is designed to form a grid of VLSI or FPGA operating frequencies at the stage of verification of VLSI projects installed in KU 27, as well as generating the operating frequency of the logic analyzer block 17.

The reference frequency generator 10 is designed to generate the control FPGA 16 reference frequencies for interaction via the network interface and the PCI_Express interface, as well as the formation of the internal frequency of operation of the control FPGA 16 both with the control computer 1 with control consoles, and in offline mode.

The condition monitoring block 25 is designed to monitor the temperature regime of a custom VLSI or FPGA (at the stage of verification of VLSI projects) installed in the control unit 27, and the voltages of the block 26 of controlled power supplies, as well as to interact with block 21 when stabilizing the temperature regime of the VLSI.

The contact device 27 with a fan and a cooling radiator is intended for installation and connection of the tested custom VLSI or FPGA (at the stage of verification of VLSI projects) to the control FPGA 16, as well as cooling during testing.

Block 26 of controlled power supplies together with block 22 of power control are designed to provide power to VLSI or FPGA (at the stage of verification of VLSI projects) with specified ratings.

VERIFICATION OF VLSI PROJECTS

In the proposed invention, instead of labor-intensive mathematical time modeling of custom VLSI projects, verification of projects implemented on an FPGA is carried out, which is installed in KU 27 with a fan and cooling radiator instead of a custom VLSI.

The initial vectors of influences and reference vectors of reactions for verification of custom VLSI designs can be the data and results of functional modeling of their projects. Formal descriptions of custom VLSIs are compiled (implemented) on an FPGA, which is installed in KU 27 with a fan and a cooling radiator, in order to check these descriptions for correctness before releasing documentation for the production of VLSIs.

When verifying VLSI projects, the multifunctional diagnostic complex operates as follows.

Based on the current work plan in the proposed multifunctional diagnostic complex, the test modules necessary to ensure effective operation in the verification of VLSI projects are identified. As a rule, each user is allocated an individual module, however, with a limited number of test modules available for verification, and due to the fact that the verification intervals are quite short and correspond to the intervals of functional mathematical (machine) modeling, test modules can be distributed for use by several users - developers of custom VLSIs in a sequential mode, which leads to a reduction in the development time of custom VLSIs and acceleration of the preparation of tests for testing custom VLSIs.

After installing the FPGA test modules dedicated for verification into the CU 27 with a cooling fan and radiator for verification of custom VLSI projects and turning on the power, the basic program from the starting configuration section of the configuration memory block 13 is loaded into the control FPGA 16. If this program does not correspond to the verified custom VLSI project, then the corresponding program is loaded from the control computer 1 with control consoles into the working configuration section of the configuration memory block 13, and the control FPGA 16 is reconfigured from this section.

Next, after supplying power to KU 27 with a fan and a cooling radiator with an installed verification FPGA, it is configured by the next verification program of the VLSI being developed from the control computer 1 with control consoles via a switch of 2 PCI_Express ports or a switch of 6 JTAG control and management ports. After this, the control computer 1 with control consoles configures the programmable generators 24 of the exchange frequency and 23 of the operating frequency, as well as loading the memory 20 of data and test results to verify the designs of the VLSI being developed. Verification of the VLSI design is performed by submitting the initial vectors of influences from memory 20 and writing the verification result vectors into memory 20. At the end of the next verification interval, the verification results are read from memory 20 into the control computer 1 with control consoles for comparison with the standard.

At the same time, during verification, the control computer 1 with control consoles carries out temperature control of the FPGA and control of its supply voltages through the condition monitoring unit 25 and the monitoring port switch 7. If the temperature or supply voltage exceeds the specified limits, an emergency power shutdown is provided. This is due to the fact that at the verification stage, custom VLSI projects are debugged, which may contain errors that lead to overheating of the FPGA installed in KU 27 with a fan and cooling radiator.

TESTING OF VLSI WITH A CONTROL COMPUTER

In the proposed invention, testing custom-made VLSI chips with a control computer 1 with control consoles is carried out at individual workstations as part of a test module dedicated for this purpose with individual control consoles, and connected to the control computer 1 through a switch of 2 PCI_Express ports.

When testing custom VLSI with a control computer 1 with control consoles, the multifunctional diagnostic complex operates as follows.

Before installing the next custom VLSI in KU 27 of the dedicated test module, the corresponding input of the switch 2 PCI_Express ports is software blocked on the control computer 1 from the individual control console, the power of the test module is turned off and the direction of loading the configuration of the control FPGA 16 from the operating configuration section of the unit is set on the manual control console 13 configuration memories.

After installing the next custom VLSI in KU 27, the power is turned on to the dedicated test modules, into the control FPGAs 16 of which the program is loaded from the working configuration section of the configuration memory block 13, software unlocking on the control computer 1 of this input of the switch 2 PCI_Express ports is performed and its ports are scanned with individual control consoles to restore the operation of this test module with the control computer 1 without turning off its power and rebooting.

If this configuration does not correspond to the VLSI being tested, then, first of all, the program for the control FPGA 16 corresponding to the custom VLSI being tested is loaded into the working configuration section of the configuration memory block 13. After this, the corresponding software blocking on the control computer 1 of the corresponding input of the switch 2 PCI_Express ports is carried out from the individual control console, the power of the test module is turned off and on again, and its ports are scanned with individual control consoles to restore the operation of this test module with the control computer 1. After this This test module is completely ready to test VLSI of this type.

Next, from the individual control console, the generator 24 is programmed with the required exchange frequency, the generator 23 with the required operating frequency, as well as the initial vectors of influences are loaded into the memory 20 of data and test results and the controllable power supply unit 26 is configured by the power control unit 22.

Before applying power to KU 27, a short circuit of the VLSI power supply to ground is checked. The presence of a short circuit indicates a malfunction of the VLSI or its incorrect installation in KU 27. After checking the correct installation of the VLSI in KU 27 and the presence of a short circuit, the VLSI is rejected.

If there is no short circuit between the VLSI power supply and ground, the power supply on the custom VLSI circuit under test is turned on and it is tested.

The initial vectors of influences from the data memory and testing results 20 are issued to the VLSI under test, into which the test results are also recorded, which, upon completion of testing, are uploaded for comparison in the control computer 1 with the reference reaction vectors and the development of “pass” or “defect” signs.

There may be several testing intervals for one custom VLSI, depending on the complexity of the tasks being solved. Since the tests are carried out at operating (high) VLSI frequencies, throughout the entire test, the control computer 1 with control consoles carries out temperature control of the VLSI under test and controls its supply voltages through the condition monitoring unit 25 through a switch of 7 monitoring ports. If the temperature or supply voltage exceeds the specified limits, an emergency power shutdown is provided.

At the end of all testing intervals, the supply voltage is removed from the VLSI under test in KU 27, the cooling fan is turned off, and the tested VLSI is removed from the de-energized KU 27.

VLSI TESTING IN OFFLINE MODE

In the proposed invention, the preparation of the test module for autonomous operation is carried out using the control computer 1 with control consoles as follows. Using the manual control console 8, which is designed to set the operating modes of the test module and control its operation in offline mode, the configuration control unit 12 of the control FPGA 16 is switched to the configuration mode of the control FPGA 16 and loaded from the memory block 13 with the offline mode configuration. Initially, the memory block 13 of the starting, working and autonomous configuration is loaded by the control computer 1 with control consoles through a switch of 6 JTAG ports of test modules using CAD FPGA tools.

After turning on the power and loading from the memory block 13 of the autonomous configuration configurations into the control FPGA 16, the control computer 1 with control consoles through the network switch 3 test modules 5 ₁ , ..., 5 _K , non-volatile memory 15 subroutines for setting test parameters are written and through the non-volatile controller 14 test program memory, which is installed in port 11 for connecting non-volatile test program memory.

After these preliminary settings, the test modules become ready for independent autonomous operation without a control computer 1 with control consoles and can be disconnected from it.

Test programs stored in non-volatile memory connected to port 11 are executed sequentially and consist of the following stages:

- loading parameters (supply voltage, operating frequency and exchange frequency, test temperature) using subroutines from non-volatile memory 15;

- turning on the power supply of the VLSI under test;

- loading (if necessary) the working program into the VLSI under test;

- loading into memory 20 initial vectors of influences and reference vectors of reactions;

- starting the test, analyzing the end of the test and, in case of successful completion, moving on to the next program.

Subroutines from non-volatile memory 15 allow for autonomous, without a computer 1 with control consoles, setting the exchange frequency, using a programmable generator 24 of the exchange frequency, operating frequency, using a programmable generator 23 of the operating frequency, supply voltages, using the VLSI power control unit 22, and operating temperatures, using condition monitoring unit 25, according to the parameters contained in the test programs.

Manual control console 8 allows you to install:

- operating mode (with or without control computer 1) (switch);

- supply power to the test module (switch);

- allow VLSI power control (switch);

- perform a general reset (button);

- run the next test run (button);

- set an automatic or step-by-step (one program at a time) order of execution of test programs (switch).

The status display block 9 is designed to indicate the current state of the test module, which includes:

- availability of power on the test module (on/off);

- availability of power on the VLSI under test (on/off);

- operating mode (with control computer 1 with or without control consoles);

- configuration of the control FPGA (yes/no);

- readiness to launch the test program (yes/no);

- completion of VLSI testing (yes/no);

- errors during testing (yes/no);

- code of the time group of the tested VLSI;

- code of the temperature group of the VLSI being tested.

Block 21 for controlling temperature stabilization and controlling the rotation speed of the cooling fan is designed to compare the current temperature of the VLSI under test with the one specified by the program, and to control temperature stabilization during the test by smoothly changing the speed of the cooling fan.

Testing of large batches of custom-made VLSIs is carried out by test modules 5 ₁ , ..., 5 _K at individual workstations without a control computer 1 with control consoles in automatic mode as follows.

After installing the next tested custom VLSI in KU 27 on the manual control console 8, the configuration mode of the control FPGA 16 is set through the configuration control unit 12 from the memory block 13 with an autonomous configuration, the VLSI power control permission is set and power is supplied to the test module. If the control FPGA 16 is successfully configured, as evidenced by the corresponding indicator of the display unit 9 without supplying power to the VLSI under test, a short circuit of the VLSI power supply to ground is checked. The presence of a short circuit indicates a malfunction of the VLSI or its incorrect installation in KU 27. After checking the correct installation of the VLSI in KU 27 and the presence of a short circuit, the VLSI is rejected.

In the absence of a short circuit of the VLSI power supply to ground, all test programs are sequentially read and executed from the non-volatile program memory connected to port 11 in accordance with their content in automatic or step mode, specified on the manual control console 8.

Each program from the external non-volatile program memory consists of two parts. In the first part, the test parameters are set up: supply voltage, operating frequency and exchange frequency, as well as the stabilized temperature of the VLSI under test, which is carried out by executing the corresponding subroutines from the non-volatile memory 15 parameter setting subroutines. In the second part, 20 initial action vectors and reference reaction vectors are first written into memory, then the action vectors from memory 20 are issued to the VLSI under test, and the test results are automatically compared with the corresponding reference reaction vectors to generate “pass” or “defect” signs.

In the automatic mode of execution of test programs, all programs from the external non-volatile memory of test programs connected to external port 11 are carried out sequentially with their corresponding parameters. When performing tests step by step, it is necessary to start each program through the control console 8, which may be necessary to detail test errors.

If among the test programs there are programs for determining the time and temperature characteristics of VLSI, then at the end of the tests, the codes of the time and temperature group of the tested custom VLSI, characterized by the cutoff frequencies and temperature of failure-free operation, will be recorded on the status display block 9.

VLSI tests to determine their technical characteristics are carried out using special stress tests, in which VLSIs are most prone to errors, both with increasing operating frequency and with increasing operating temperature. Since the power consumption of a VLSI, and therefore its temperature, strongly depends on the frequency of its operation, a time group is first determined by executing the task at several specified operating frequencies, depending on the type of VLSI under test at the nominal temperature. This is ensured by the temperature stabilization control unit 21 and cooling fan rotation speed control by comparing the current VLSI temperature with the nominal one and changing the cooling fan rotation speed. The operating frequency determined in this way will most likely determine its time group. Determining the temperature group of the VLSI under study is carried out by checking the correctness of its operation at a given frequency and at other (higher) stabilized temperatures.

Routines for setting test parameters correspond to the components of a specific test module and are written to non-volatile memory 15 once. Test programs correspond to the specific tested type of custom-made VLSI and can change both during the transition of tests from one type of VLSI to another, and when finalizing (modifying) the test system for a specific VLSI. In this regard, the implementation of test program memory on external media connected to port 11 simplifies (facilitates) its replication.

Reducing the duration of testing custom VLSI in the proposed multifunctional diagnostic complex is carried out by reducing the time for exchange with the control computer 1 through the use of block 19 of hardware generation of test effects and block 18 of the signature analyzer.

Increasing the reliability of testing custom VLSI in the proposed multifunctional diagnostic complex is carried out by increasing the length of the test sequence within the permissible test time due to the existing possibility of reducing the duration of tests.

The expansion of functionality in the proposed multifunctional diagnostic complex is carried out by providing the logic analyzer block 17 and the integrated logic state analyzer block 30 with the ability to detail the timing diagram of test fragments at frequencies higher than the test execution frequency.

EXAMPLE OF IMPLEMENTATION OF THE INVENTION

The proposed multifunctional diagnostic complex can be implemented on the following elements:

As a control computer 1 with control consoles, a Kraftway server based on the Kraftway Express 200 platform can be used: Intel(R) Xeon(R) E2620V4 2.10 GHz 8 cores processor with 64 Gbyte RAM and 1 Tbyte hard drive. The monitor and keyboard of the control computer 1, as well as monoblocks with a keyboard connected to its network, can be used as control consoles.

Test modules 5 ₁ , …, 5 _K can be performed on the following elements:

control FPGA 16 - on a Xilinx ZYNQ-7 XC7Z007S-2CLG400E chip;

block 13 of memories for the starting, working and autonomous memory configuration of the control FPGA 16 - on chips on SPI memory N25Q064A11EF640;

unit 12 for controlling the configuration of the control FPGA 8 using CPLD XC2C64A chips;

condition monitoring unit 25 - on TMP461AIRUNT, MAX6656 and MAX1239EEE chips;

programmable generators with 24 exchange frequencies and 23 operating frequencies - on 570FCA000133DG microcircuits.

memory 20 of data and test results - using MT46N128M16LFDD-48 microcircuits;

non-volatile memory 15 routines for setting test parameters - using NAND Flash memory chips MTFC32GAXATEA-WT from MICRON;

unit 21 for controlling temperature stabilization and controlling the rotation speed of the cooling fan, as well as controller 14 for non-volatile memory of test programs using CPLD XC2C64A microcircuits;

Micro SD card MTSD256AHC6MS-1WT from MICRON can be used as a non-volatile memory of test programs;

Memory Card Sockets from MOLEX can be used as port 11 for connecting non-volatile memory of test programs.

Platform Cable USB II DLC10 from Xilinx and standard USB splitters can be used as a switch for 6 monitoring and control ports of JTAG test modules.

The above information allows us to conclude that the proposed multifunctional diagnostic complex solves the problem and corresponds to the declared technical result - expanding the testing functionality, reducing the duration and increasing the reliability of control when testing custom VLSI circuits.

Claims (5)

The multifunctional diagnostic complex contains a control computer 1 with management consoles, a switch of 2 PCI_Express ports, a switch of 3 network ports, an external network port of 4 users, a switch of 6 JTAG control and management ports, a switch of 7 monitoring ports and a group of K test modules 5 ₁ , ..., 5 _K , each of which contains a manual control console 8, a status display unit 9, a reference frequency generator 10, a port 11 for connecting non-volatile test program memory, a control FPGA configuration control unit 12, a configuration memory unit 13, a non-volatile test program memory controller 14, non-volatile memory 15 subroutines for setting test parameters, memory 20 of data and test results, temperature stabilization control unit 21 and cooling fan speed control unit, power control unit 22, programmable operating frequency generator 23, programmable exchange frequency generator 24, condition monitoring unit 25, unit 26 controlled power supplies, a contact device 27 with a fan and a cooling radiator, a block 30 of an integrated logic state analyzer and a control FPGA 16, which contains a logic analyzer block 17, a signature analyzer block 18 and a hardware test action generation block 19, implemented using the resources of the control FPGA 16 , Moreover, the control computer 1 with management consoles is connected to a switch of 3 network ports, to a switch of 6 JTAG monitoring and control ports and to a switch of 2 PCI_Express ports, which is connected to the control FPGAs of 16 test modules 5 ₁ , ..., 5 _K , and the switch of 3 network ports , connected to an external network port of 4 users, to control FPGAs of 16 test modules 5 ₁ , ..., 5 _K and to a switch of 7 monitoring ports, which is connected to blocks 25 for monitoring the status of test modules 5 ₁ , ..., 5 _K , and a switch of 6 ports monitoring and control JTAG is connected to block 17 of the logic analyzer of the control FPGA 16 test modules 5 ₁ , ..., 5 _K and to block 30 of the integrated logic state analyzer, which is connected to the programmable generator 23 of the operating frequency and connected to the control and data exchange bus 29, which the contacting device 27 and the control FPGA 16 test modules 5 ₁ , ..., 5 _K are connected, In addition, the contacting device 27 of test modules 5 ₁ , ..., 5 _K is connected to a programmable exchange frequency generator 24, to a temperature stabilization control unit 21 and cooling fan rotation speed control unit, to a test module status monitoring unit 25, and to a controllable power supply unit 26 and with a configuration bus 28 with a control FPGA 16, which is connected to a temperature stabilization control unit 21 and a cooling fan rotation speed control unit, with a power control unit 22, with a memory 20 of data and test results, with a non-volatile memory 15 subroutines for setting test parameters, with reference frequency generator 10, with a programmable operating frequency generator 23, with a programmable operating frequency generator 24, a monitoring unit 25, with a configuration control unit 12, with a non-volatile test program memory controller 14, with a manual control console 8 and with a status display unit 9, which connected to the manual control console 8, which is connected to the configuration control unit 12, connected to the configuration memory unit 13, in addition, the condition monitoring unit 25 is connected to the temperature stabilization control unit 21 and the cooling fan rotation speed control unit and to the controlled power supply unit 26, which is connected to the power control unit 22, Moreover, the controller 14 of the non-volatile memory is connected to port 11 for connecting the non-volatile memory of test programs, and the operating frequency generator 23 is connected to the logic analyzer block 17, which, together with the signature analyzer block 18 and the hardware generation of test actions block 19, is connected inside the control FPGA 16 to the control bus 29 and data exchange.