RU2801875C1 - Method for packet data transmission by noise-like phase key signals - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: at the beginning of the transmission of each data packet, a clock signal is transmitted, which is formed by quadrature modulation of the carrier frequency signal by two binary pseudo-random sequences, synchronizing (SP) and informational (IP). The SP is an M-sequence, and the IP is formed from the M-sequence by adding one constant element. When transmitting data, the SP is extended by one element and an additional sequence (DS) is formed by cyclically shifting the original SP and adding one constant element. At each repetition period of the IP, two modulated sequences (MP1 and MP2) are formed by cyclically shifting the M-sequence from which the IP is formed by the number of elements determined by two transmitted information symbols, and adding one constant element. The carrier frequency signal is quadrature modulated by two binary sequences, one of which is formed by adding modulo two SP and MP1, and the second by adding modulo two DP and MP2.

EFFECT: increased data transfer rate.

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Description

The invention relates to the field of radio engineering and can be used in systems of noise-protected packet data transmission.

The main task that has to be solved in the design of such systems is to reduce the time of data transmission while simultaneously ensuring high reliability of their reception under the influence of both natural interference and interference from electronic countermeasures.

Among the known methods for improving the noise immunity of communication systems, the frequency hopping (FH) method and the direct sequence (DS) method are most widely used [1]. In the domestic literature, the signals generated by the DS method are called noise-like (broadband) phase-shift keyed signals (NPS). The methods of their formation and reception are well researched. They are the subject of a large number of scientific publications, for example [2], and patents [3].

Most of the known communication systems have a low information transfer rate, since they use binary alphabets of signals [4]. In some patents [5], an increase in the information transfer rate is achieved through the use of large volume signal alphabets, however, this reduces the noise immunity of the system, including due to the incomplete use of the signal power for information transmission.

The aim of the invention is to increase the data transfer rate while ensuring high noise immunity. The result achieved by using the invention is the reduction of data transmission time.

The closest in terms of the number of matching features to the claimed method is the method of generating noise-like phase-shift keyed signals, described in [6].

According to this method, the following operations are performed in the transmitter:

- Form the signals of the carrier and clock frequencies.

- Binary quasi-orthogonal PRS, synchronizing and informational, are formed from the clock frequency signal, moreover, the synchronizing PRS is an M-sequence, and the informational PRS is also an M-sequence, but shortened or extended by one element.

- Periodically with a period equal to the product of the number of elements of the synchronizing SRP, the number of elements of the information SRP and the duration of the clock period, the phasing of the synchronizing SRP with the information SRP is carried out, that is, the SRP generators are set to the initial fixed states.

- At each repetition period of the information SRP, a modulated SRP is formed by cyclic shifting of the information SRP with an unchanged length by the number of elements determined by the transmitted information symbol, and additional modulo two addition with one more bit of information. The resulting sequence, as well as the information PSP, is shortened or lengthened by one element.

- The modulo two SRP and the synchronizing SRP delayed by an integer number of clock cycles are summed, and the result is majority summed with the synchronizing SRP and the information SRP. Under the majority addition of logical signals is understood the operation of calculating the majority function "two out of three".

- The received binary sequence is manipulated in phase with the carrier frequency signal.

- The synchronizing PSP and the information PSP are summed modulo two, and the resulting binary sequence performs an additional phase shift of the phase-shift keyed signal by zero or ninety degrees.

The disadvantage of the prototype method is the inefficient use of the power of the transmitted signal. Only half of this power is used for data transmission, so it is possible to increase the data rate by using the entire signal power.

To solve the problem posed in the invention in the method of packet data transmission with noise-like phase-shift keying signals, which consists in the fact that carrier and clock signals are generated, binary quasi-orthogonal pseudo-random sequences, synchronizing (SP) and informational (IP) are formed from the clock signal, and the SP is M - sequence, and the IP is formed from the M - sequence by adding one constant element, at each repetition period of the IP, a modulated sequence is formed by cyclically shifting M - the sequence from which the IP is formed, by the number of elements determined by the next transmitted information symbol, and adding one constant element, according to the invention, at the beginning of the transmission of each data packet, the SP and the IP are phased between each other, and also a clock signal is transmitted, for the formation of which the carrier frequency signal is shifted in phase by ninety degrees, the elements of the SP are manipulated in phase and summed with the carrier frequency signal manipulated in phase SP elements, the duration of the clock signal is chosen as a multiple of the SP repetition period, and when transmitting data, the SP is extended by one constant element and an additional sequence (DP) is formed by cyclic shifting the non-extended SP by a fixed number of elements and adding one constant element, as well as at each SP repetition period an additional modulated sequence is formed by cyclic shift M - the sequence from which the IP is formed, by the number of elements determined by the next transmitted information symbol, and by adding one constant element, one of the carrier frequency signals is manipulated in phase by a sequence of sums modulo two elements of the modulated sequence and SP , and the second signal of the carrier frequency is manipulated in phase by a sequence of modulo two elements of the additional modulated sequence and DP and both phase-shift keyed signals are summed.

The method of packet data transmission by noise-like phase-shift keying signals consists in sequentially performing the following operations:

- Form a clock signal and two carrier signals, shifted between themselves in phase by ninety degrees.

- From the clock signal form two binary quasi-orthogonal pseudo-random sequences, synchronizing (SP) and informational (IP). SP is M-sequence, and IP is formed from M-sequence by adding one constant element.

- At the beginning of the transmission of each data packet, the SP and IP are phased between themselves and a clock signal is transmitted.

- To form a clock signal, one of the carrier frequency signals is manipulated in phase by the elements of the SP, and the second by the elements of the IP, and both phase-shift keyed signals are summed.

- The duration of the clock signal is chosen as a multiple of the repetition period of the IP.

- When transmitting data, the SP is extended by one constant element and an additional sequence (DS) is formed by cyclically shifting the non-extended SP by a fixed number of elements and adding one constant element.

- At each repetition period of the IP, two modulated sequences (MP1 and MP2) are formed, by cyclic shift M - the sequence from which the IP is formed by the number of elements determined by two transmitted information symbols and the addition of one constant element.

- One of the carrier signals is manipulated in phase by a sequence of sums modulo two of the elements MP1 and SP, and the second sequence of modulo two sums MP2 and DP.

- Summarize both phase-shift keyed signals.

Due to the transmission of two information symbols in one IP repetition period, the information transmission rate is almost doubled. More precisely, if the number of IP elements is N=2 ⁿ , then the bit width of the information symbol does not exceed n. The maximum data transfer rate by the prototype method is equal to (bps), where T(c) is the duration of the IP repetition period. The maximum data transfer rate by the claimed method is equal to (bps).

For example, when = 9 the increase in transfer rate is

Consider the mathematical representation of the clock signal:

Where is the signal amplitude;

– carrier frequency;

– SP;

- IP.

As can be seen, the clock signal is the sum of two carrier signals shifted in phase by ninety degrees, one of which is manipulated in phase by a periodically repeating SP, and the second by a periodically repeating IP.

In the receiving device, the simultaneous search for SP and IP can be implemented. In this case, if we use a detection algorithm based on comparing the maximum values of the cross-correlation functions of the received signal with the SP and IP with the threshold of the sum of squares, the detection noise immunity will be slightly lower than the detection noise immunity when transmitting one SP.

After the detection of the clock signal and automatic tuning of the PSP clock frequency, the receiving device switches to the mode of searching for the end of the transmission of the clock signal.

Let's consider the algorithm of this search. At the beginning of the transmission of the clock signal, the SP and the IP are phased with each other. This means that the generators (shapers) of the SP and IP are set to certain initial states. For example, if the generators are based on shift registers with modulo two adders in the feedback loop, the initial states are the binary codes written in the registers. If the shapers are made on the basis of counters and read-only memories, the initial states are the zero states of the counters. Let's consider this method of formation. If the number of SP elements is N-1, then the SP shaper counter counts clock pulses modulo the number N-1. The number of IP elements is N, so the counter of the IP shaper counts clock pulses modulo the number N.

At the beginning of the formation of the clock signal, both counters are in the zero state, that is, at the outputs of their bits, there are binary codes for the number zero. In the future, each time when the counter of the information PSP generator is set to zero (Fig.2a), the number, the binary code of which is set at the outputs of bits of the counter of the synchronizing PSP generator, is increased by one (Fig.2b). If the duration of the clock signal isK SP repetition periods, then the end of the clock signal corresponds to the moment when the number code zero is set at the outputs of the digits of the counter of the SP shaper, and the number code is set at the outputs of the bits of the counter of the SP shaperK.That's why the sign can be determined by the end of the clock signal in the receiving device.

In the data transmission mode, the generated signal has the form

Where - DP;

- MP1;

- MP2.

It can be shown that the signals And are quasi-orthogonal, so the optimal non-coherent two-channel reception of such signals includes pre-multiplication of the quadrature envelopes of the input signal in one channel by , and in the second, , that is, on the SP and DP reduced to a bipolar form. After that, in each channel, the correlation of the quadrature envelopes with each of the signals of the form (i = 1…Q), where – modulated sequence corresponding to i – one of the Q possible transmitted information symbols, as well as the sum of their squares. The maximum of the Q values of the sum of squares and the corresponding modulated sequence are selected, by which the transmitted information symbol is determined.

Note that for large Q, that is, a large number of different transmitted information symbols, the noise immunity of incoherent reception differs slightly from the noise immunity of coherent information reception.

An example of a technical implementation of a device for generating a transmitted signal is shown in Fig. 1.

The device contains:

1 – generator of clock frequency signals (FSFC);

2 – counter modulo N-1 ;

3 – counter modulo N ;

4 - frequency divider by N ;

5, 6, 10, 11 - Read Only Memory (ROM);

7, 9 – modulo N-1 adder;

8 - parallel register;

12, 13 - scheme 2OR;

14, 15 - modulo two adder;

16, 17 - switch;

18 - frequency divider by K ;

19, 20 - level converter (PU);

21 - phase shifter;

22 – carrier frequency signal generator (FSLF);

23 - D-trigger;

24, 25 - multiplier;

26 - adder.

The device works as follows. The clock signal generated by the FSTC 1 is supplied to the clock inputs of the modulo N-1 2 counter , the modulo N 3 counter and the frequency divider by N 4 ( N is the number of IP elements). The transmission permission signal (RP) comes from the data transmission device (DDU) to the reset inputs of counters 2, 3 and D-trigger 23, as well as the inputs of the initial setting of the frequency divider for N 4 and the frequency divider for 18.

In the absence of the RP signal, counters 2, 3 and D-flip-flop 23 are in the zero state, and frequency dividers 4, 18 are in the initial state. Upon arrival of the RP signal, counters 2, 3 and frequency divider 4 start to work. Frequency divider 4 generates pulses with a duration equal to one period of the clock frequency and a duty cycle equal to N. These pulses are fed to the clock inputs of the parallel register 8 and the frequency divider to 18. Upon arrival th pulse at the output of the frequency divider 18 there is a pulse that goes to the clock input of the D-flip-flop 23 and sets it to the state of a logical unit.

The output signal (RD) of the D-flip-flop 23 is fed to the UPD and allows data transmission. The clock pulses (TI) for reading data from the UPD are the output pulses of the frequency divider 4. The transmitted information symbols in the form of two multi-bit binary numbers come from the output of the UPD to the input of the parallel register 8, where they are recorded by the output pulses of the frequency divider 4.

The formation of pseudo-random sequences occurs as follows. At the outputs of counters 2 and 3 with a frequency of clock pulses, periodic sequences of multi-bit binary numbers are formed And respectively. The output signals of the counter modulo N-1 2 are fed to the address inputs of the ROM 5, which contains the values of the elements of the joint venture. At the output of the ROM 5 is formed periodically repeating joint venture.

Similarly, the output signals of the counter 3 are fed to the address inputs of the ROM 6. The ROM 6 contains three-digit numbers. In one of the digits, the values of the elements of the IP are recorded, in the other, the values of the elements of the SP supplemented with one constant element, and in the third, the values of the elements of the DP. At the output of the ROM 6 periodically repeating sequences are formed: IP, supplemented by one element of the joint venture and DP.

The clock signal is formed during the first IP repetition periods. At this time, the D-flip-flop 23 is in a logic zero state. Its output signal is fed to the control inputs of the switches 16 and 17. In this case, the switch 16 connects to the input of the level converter 19 a periodically repeating SP from the output of ROM 5, and the switch 17 connects to the input of the level converter 20 a periodically repeating IP from one of the outputs of the ROM 6.

In level converters 19 and 20, the signals are converted to a bipolar form and fed to the inputs of multipliers 24 and 25, respectively. The second input of the multiplier 25 receives a carrier frequency signal from the output of the FSLF 22, and the second input of the multiplier 24 receives a carrier frequency signal shifted in phase by ninety degrees in the phase shifter 21. At the output of the multiplier 25, a carrier frequency signal is generated, manipulated in phase by the elements of a periodically repeating IP , and at the output of the multiplier 24 - a signal of the carrier frequency, shifted in phase by ninety degrees and manipulated in phase by the elements of a periodically repeating SP. Both signals are summed in the adder 26, forming a clock signal.

In the data transfer mode, the D-flip-flop 23 goes into the state of a logical unit and the switch 16 connects the output signal of the adder modulo two 14 to the input of the level converter 19, and the switch 17 connects the output signal of the adder modulo two 15 to the input of the level converter 20.

The binary codes of the next two transmitted information symbols are recorded in the parallel register 8 and fed to the inputs of the adders modulo N-1 7 and 9, the second inputs of which receive a multi-bit signal from the output of the counter 3. At the outputs of the adders modulo N-1 7 and 9, sequences of numbers representing cyclic shifts of the sequence . Binary representations of shift values coincide with binary codes of information symbols.

The output signals of the adders modulo N-1 7 and 9 are supplied to the address inputs of the ROM 10 and 11, respectively. ROMs 10 and 11 contain elements of M - the sequence from which the IP is formed. At the outputs of the ROM 10 and 11, sequences are formed that are cyclic shifts of M - the sequence from which the IP is formed. Binary representations of the magnitude of the shifts coincide with the binary codes of information symbols.

In circuits 2OR 12 and 13, one constant element is added to these sequences, equal to a logical unit, at the moment the pulse arrives from the output of the frequency divider to N 4. At the outputs of circuits 2OR 12 and 13, modulated sequences MP1 and MP2 are formed, which are fed to the inputs of the adders modulo two are 14 and 15, respectively.

The second input of the adder modulo two 14 receives the SP extended by one constant element from the output of the ROM 6, and the second input of the adder modulo two 15 - DP. At the output of the adder modulo two 14, a sequence of sums modulo two elements MP1 and SP is formed, and at the output of the adder modulo two 15 - elements MP2 and DP. In level converters 19 and 20, the sequences are converted to a bipolar form and fed to the inputs of multipliers 24 and 25, respectively.

At the output of multiplier 25, a carrier frequency signal is generated, manipulated in phase by the modulo sum of two elements MP2 and DP, and at the output of multiplier 24, a carrier frequency signal, phase-shifted by ninety degrees and manipulated in phase by the modulo sum of two elements MP1 and SP.

SOURCES OF INFORMATION

1. Sklyar B. Digital communication. Theoretical foundations and practical application. Ed. 2nd, corrected: Per. from English. - M .: Williams Publishing House, 2004. - 1104 pp., pp. 733-819.

2. Borisov V. I. et al. Noise immunity of radio communication systems with the expansion of the spectrum of signals by modulation of the carrier pseudo-random sequence - M .: Radio and communication, 2003. - 641 p.

3. Patent RU 2646 353 C1. Transmitter of increased structural and energy secrecy. Published on 03/02/2018. Bull. No. 7.

4. Patent RU 2127 486 C1. Method and device for transmitting messages by broadband signals. Published 03/10/1999.

5. Patent RU 2279 183 C2. A method for transmitting information in a communication system with broadband signals. Published on 06/27/2006. Bull. No. 18.

6. Patent RU 2731 681 C1. Method for generating noise-like phase-shift keyed signals. Published on 07.09.2020. Bull. No. 25.

Claims (1)

A method for packet data transmission by noise-like phase-shift keyed signals, which consists in the fact that signals of the carrier and clock frequencies are formed, binary quasi-orthogonal pseudo-random sequences, synchronizing (SP) and informational (IP) are formed from the clock signal, moreover, the SP is an M-sequence, and the IP is formed from the M-sequence by adding one constant element, at each IP repetition period, a modulated sequence is formed by cyclically shifting the M-sequence from which the IP is formed by the number of elements determined by the next transmitted information symbol, and adding one constant element, characterized in that in At the beginning of the transmission of each data packet, the SP and the IP are phased between each other, and a sync signal is transmitted, for the formation of which the carrier frequency signal is shifted in phase by ninety degrees, the elements of the SP are manipulated in phase and summed with the carrier frequency signal, manipulated in phase by the elements of the IP, the duration of the sync signal a multiple of the IP repetition period is chosen, and when transmitting data, the SP is extended by one element and an additional sequence (DP) is formed by cyclically shifting the non-extended SP by a fixed number of elements and adding one constant element, and also at each IP repetition period, an additional modulated sequence is formed by cyclic shift of the M-sequence, from which the IP is formed, by the number of elements determined by the next transmitted information symbol, and the addition of one constant element, one of the carrier frequency signals is manipulated in phase by a sequence of sums modulo two elements of the modulated sequence and SP, and the second carrier frequency signal manipulating in phase a sequence of sums modulo two elements of the additional modulated sequence and DP and summing both phase-shift keyed signals.

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