RU2779892C1 - Series multiplex inverter control device - Google Patents

Abstract

FIELD: control devices.

SUBSTANCE: present invention relates to a control device for a series multiplex inverter capable of outputting voltage through inverters, and in particular relates to loss equalization control.The high level control unit (5) generates an L* level command based on the cmd command value. The switching load distribution control unit (6) stores information about the period of the output state of each cell and assigns a control signal so that: in the case of a scheme according to which the cell changes from level level ±1 is set to level 0; and in the case of a scheme in which a cell changes from level 0 to level ±1, the cell having the longest period of the output state with level 0 is set to level ±1.

EFFECT: improving the distribution of the switching load level in each cell in the control device of the serial multiplex inverter.

13 cl, 27 dwg

Description

Technical field

[0001] The present invention relates to a control device for a series multiplex inverter capable of outputting voltage through inverters, and in particular relates to loss equalization control.

State of the art

[0002] The following discusses a system in which an input three-phase alternating (AC) voltage is converted to a direct (DC) voltage using a rectifier (AC-DC converter), and the DC voltage is output through the inverter as an AC voltage, having the desired frequency and desired amplitude.

[0003] In such a system, a series multiplex inverter in which several single-phase inverters are connected can be used to output a high voltage or a voltage with few harmonics. A series multiplex inverter is also called a cascaded H-bridge inverter or the like.

[0004] FIG. 1 shows an example of the main circuit configuration of a series multiplex inverter. The configuration in Fig. 1 includes N single phase inverters connected in series in each phase and is capable of outputting phase voltage at 2N+1 levels. In the present description, this configuration is referred to as an N-stage series multiplex inverter. In FIG. 1 alternating current is converted to direct current using a three-phase rectifier, and isolated gate bipolar transistors (IGBTs - Isolated Gate Bipolar Transistors) form a single-phase inverter.

[0005] In the series multiplex inverter, each single-phase inverter (hereinafter referred to as a cell) may be switched independently, and the switching times may be combined alternately. Thus, it is possible to form a device having a high switching frequency as a whole while suppressing the switching frequency of each cell.

[0006] FIG. 27 shows a switching example of a serial multiplex inverter having a four-stage cell configuration. The switching time of each cell is different from the switching time of other cells, which does not cause phase voltage imbalance, while the phase voltage maintains a sinusoidal symmetrical waveform. The switching frequency of the phase voltage is equal to the sum of the cell switching frequencies.

[0007] In a series multiplex inverter, a phase voltage waveform may be expressed by various cell waveform combination schemes. This high degree of freedom allows for a variety of control methods. However, since the cell voltages cannot be uniquely determined from the phase voltage, the cell voltages may be output in an unbalanced manner depending on the selected control method.

[0008] An imbalance between cell voltages means an imbalance in switching losses among cells and causes an increase in power consumption for cooling and a reduction in component life. To prevent degradation of system efficiency and shortening of service life, it is necessary to apply control to optimally distribute the load of each cell. Hereinafter, the load associated with the imbalance between the cell output voltages is called the switching load of each cell, or simply the switching load.

[0009] Were studied practical ways to control the distribution of switching loads, and were presented in two main directions.

[0010] The first direction is an improvement of the Pulse Width Modulation (PWM) method with phase placement (Phase Disposition, PD) disclosed in Patent Document 1. The PD method is performed by performing triangular wave comparison using carrier signals shifted in the level region and having the same phase. In the PD method, the line-to-line voltage is not shifted by two steps, which provides the preferred voltage applied to the motor. However, there is a problem of switching load imbalance between cells. In order to solve this problem, Patent Document 1 achieves the same phase voltage waveform as the PD method with a balanced switching load by distributing the command voltage for cell carrier signals.

[0011] The second direction is an improvement of the phase shift PWM (Phase Shift, PS) method disclosed in Patent Document 2. The PS method is implemented by performing triangular wave comparison using carrier signals having phase shifts. In the PS method, the switching load of each cell can be distributed without additional special control, but the line-to-line voltage is likely to shift by two steps, and there is a problem with the voltage applied to the motor.

[0012] To solve this problem, Patent Document 2 compensates for the disadvantage of a two-step phase-to-phase voltage shift while maintaining the benefit of a distributed switching load by performing a carrier signal shift operation in accordance with a voltage command.

[0013] As described above with respect to PWM with comparison of triangular waves, the traditional approach is to apply the method of switching load distribution in the control system in which distribution of the switching load is difficult, or to overcome the disadvantage in the control system in which distribution of the switching load simple.

[0014] In addition, switching load distribution other than PWM with triangular wave comparison is also studied. In Patent Document 3 relating to the output of a fixed pulse train having a predetermined phase, switching load distribution is performed by exchanging a voltage command for each cell in each PWM half cycle while maintaining the phase output voltage.

[0015] Patent Documents 1 and 2 are based on performing PWM with triangular wave comparison. For example, no methods of distributing the switching load of each cell have been studied for cases where the modulation is performed using Direct Torque Control (DTC), which sets the optimal output level to follow the target torque, or the modulation is performed using the fixed sequence method. pulses that outputs the table level synchronously with the phase of the fundamental wave.

[0016] In addition, in Patent Document 1, in order to achieve a strict distribution of the switching load of each cell, it is required to store the carrier allocation scheme for each cell in a table, and creating the table increases the cost.

[0017] Patent Document 2 presents the cell voltage distribution obtained by the PS method. In the PS method, when the command voltage slope near the zero-crossing is close to or greater than the carrier signal slope, there is a problem that the command voltage near the zero-crossing is likely to constantly cross the carrier signal of the same cell. and thereby cause a small imbalance in the switching load.

[0018] With regard to Patent Document 3, it is required to predetermine the output voltage for each cell before switching load sharing control. In addition, it is based on the exchange of voltage commands in a PWM half cycle, and it is not possible to perform a control method that is not based on a PWM cycle, such as a control method such as comparator control that determines switching by comparing between a target value to be evaluated and a threshold value. .

[0019] In view of the above, there is a problem of distribution of the switching load between cells in the control device for the series multiplex inverter.

Prior Art Documents

Patent Documents

[0020] Patent Document 1: Japanese Patent No. 3316801.

Patent Document 2: Japanese Patent Application Publication No. 2006-109688.

Patent Document 3: Japanese Patent Application Publication No. 2006-320103.

Brief summary of the invention

[0021] The present invention has been made in view of the known problems described above. According to one aspect of the present invention, a control apparatus for a series multiplex inverter, in which each of the phases includes cells connected in series, includes: a high-level control section configured to generate a level command based on a command value; and a switching load distribution control section, configured to: store ON-output duration information for each of the cells and OFF-output duration information for each of the cells; for the shift circuit from on to off in the cells, turning off the control signal for one of the cells, in which the duration of the on output state is the longest of the cells; and for the shift circuit from off to on in the cells, turning on the control signal for one of the cells, in which the duration of the off output state is the longest of the cells; wherein each of the cells is defined as enabled (ON) when each of the cells in terms of output level is equal to level +1 or level -1; and each of the cells is determined to be OFF when the output level of each of the cells is zero.

[0022] According to one aspect of the present invention, the control device is configured such that the switching load sharing control section is configured to: perform a circuit determination operation based on a layer command and an output layer, wherein the circuit determination operation is to select one of circuit A, circuit B and circuit C, wherein circuit A must cause an off-to-on shift in the cells, circuit B must cause an on-to-off shift in the cells, and circuit C must not cause a level shift; performing a counter calculation operation for processing information about the duration of the on output state and information about the duration of the off state of the output state based on the selected scheme; and performing a control signal generating operation to generate a control signal based on the output state on duration information and the output state off duration information.

[0023] According to another aspect of the present invention, the control device is configured such that the switching load sharing control section is configured to: perform a schema determination operation based on a level command and an output level, wherein the scheme determination operation is to select one of circuit A, circuit B and circuit C, wherein circuit A must cause an off-to-on shift in the cells, circuit B must cause an on-to-off shift in the cells, and circuit C must not cause a level shift; performing a counter calculation operation for processing information about the duration of the on output state and information about the duration of the off state of the output state based on the selected scheme; repeating the counter calculation operation when the level instruction and the output level differ from each other by two or more levels; and performing a control signal generating operation to generate a control signal based on the output state on duration information and the output state off duration information.

[0024] In accordance with one aspect of the present invention, the control device is configured such that a counter calculation operation is performed by: providing an ON-counter as information about the duration of the output state being on, and an OFF-counter in as information about the duration of the off output state for each of the cells, wherein the value of the on counter indicates the duration of the output state, and the value of the off counter indicates the duration of the output state; for circuit A, setting to zero the off counter of one of the cells whose off counter is the largest of the cells, setting to 1 the on counter of one of the cells whose off counter is the largest of all cells, increasing the on counter of each of the cells, the on counter which has a positive value, and increasing the off counter of each of the cells, the off counter of which has a positive value; for circuit B, setting to zero the on counter of one of the cells whose on counter is the largest of the cells, setting to 1 the off counter of one of the cells whose on counter is the largest of all cells, increasing the on counter of each of the cells whose on counter has a positive value, and incrementing the off counter of each of the cells whose off counter has a positive value; and for circuit C, incrementing the on counter of each of the cells whose on counter is positive and incrementing the off counter of each of the cells whose off counter is positive; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose on counter is positive, and generating a control signal to turn off each of the cells whose on counter is zero.

[0025] In accordance with another aspect of the present invention, the controller is configured such that the calculation operation of the counter is performed by: providing a counter for each of the cells, wherein the absolute value of the counter indicates the duration of the output state, wherein the counter indicates the on output state, when the counter is positive, and the counter indicates an off output state when the counter is negative; for circuit A, setting to 1 the counter of one of the cells whose counter is the smallest of the cells, incrementing the counter of each of the cells whose counter is positive, and decrementing the counter of each of the cells whose counter is negative; for circuit B, setting to -1 the counter of one of the cells whose counter is the largest of the cells, incrementing the counter of each of the cells whose counter is positive, and decrementing the counter of each of the cells whose counter is negative; and for circuit C, incrementing the counter of each of the cells whose counter is positive and decrementing the counter of each of the cells whose counter is negative; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose counter is positive and generating a control signal to turn off each of the cells whose counter is negative.

[0026] According to another aspect of the present invention, the control device is configured such that a counter calculation operation is performed by: providing an on counter as output state on duration information and an off counter as output state off duration information for each of cells, wherein the value of the on counter indicates the duration of the output state, and the value of the off counter indicates the duration of the output state; for circuit A, setting to zero the off counter of one of the cells whose off counter is the largest of the cells, setting to 1 the on counter of one of the cells whose off counter is the largest of all cells, and incrementing the on counter of each of the cells, counter inclusion of which has a positive value; for circuit B, setting to zero the on counter of one of the cells whose on counter is the largest of the cells, setting to 1 the off counter of one of the cells whose on counter is the largest of all cells, and incrementing the off counter of each of the cells whose off counter is has a positive value; and for circuit C, no operation is performed; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose on counter is positive, and generating a control signal to turn off each of the cells whose on counter is zero.

[0027] In accordance with another aspect of the present invention, the control device is configured such that a counter calculation operation is performed by: providing a counter for each of the cells, wherein the absolute value of the counter indicates the duration of the output state, wherein the counter indicates the on output state, when the counter is positive and the counter indicates an off output state when the counter is negative; for circuit A, setting to 1 the counter of one of the cells whose counter is the smallest of the cells, and incrementing the counter of each of the cells whose counter is positive; for circuit B, setting to -1 the counter of one of the cells whose counter is the largest of the cells, and decrementing the counter of each of the cells whose counter is negative; and for circuit C, no operation is performed; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose counter is positive, and generating a control signal to turn off each of the cells whose counter is negative.

[0028] According to another aspect of the present invention, the control device is configured such that: a counter calculation operation is performed by: providing an on counter as output state on duration information and an off counter as output state off duration information, when In this case, the on counter is an array in which each of the cells in the on state is arranged in descending order of the duration of the on output state, and the off counter is an array in which each of the cells in the off state is arranged in descending order of duration off output state; for circuit A, moving one of the cells located in the off counter, whose off duration is the longest of the cells, to the position next to the last of the cells in the on counter, and shifting one column of the remaining cells located in the off counter, to the direction of increasing the duration of the off output state; for circuit B, moving one of the cells located in the on counter, whose on duration of the output state is the longest of the cells, to the position next to the last of the cells in the off counter, and shifting one column of the remaining cells located in the on counter, to the direction of increasing the duration of the on output state; and for circuit C, no operation is performed; and a control signal generating operation is performed by generating a control signal to turn on each of the cells located in the on counter, and generating a control signal to turn off each of the cells not located in the on counter.

[0029] According to another aspect of the present invention, the control device is configured such that a counter calculation operation is performed by: providing a counter as output state on duration information and output state off duration information, wherein the counter is an array, including an off-state region (OFF-region) and an on-state region (ON-region), wherein each of the cells in the off state is located in descending order of the duration of the off output state in the off state, and each of the cells, being in the on state, is located in descending order of the duration of the on output state in the area of the on state; for circuit A, moving one of the cells located in the off state region whose off state duration is the longest of the cells to the closing position in the on state region, shifting one column of the remaining cells in the direction in which the output state duration is increased, and shifting the boundary between the off state area and the on state area in the direction of decreasing the off state area by one and increasing the on state area by one; for circuit B, shifting the boundary between the off state region and the on state region in the direction of increasing the off state region by one and decreasing the on state region by one; and for circuit C, no operation is performed; and a control signal generating operation is performed by generating a control signal to turn on each of the cells located in the on state region and generating a control signal to turn off each of the cells not located in the on state region.

[0030] According to another aspect of the present invention, the control device is configured such that a counter calculation operation is performed by: providing a counter as output on duration information and output off duration information, where the counter is an array, including an off state region and an on state region, wherein each of the cells in the off state is arranged in descending order of the duration of the off output state in the off state, and each of the cells in the on state is arranged in descending order of duration the on output state in the on state area; for scheme A, shifting the boundary between the off state region and the on state region in the direction of increasing the on state region by one and decreasing the off state region by one; for circuit B, moving one of the cells located in the on state area whose on state output state duration is the longest of the cells to the closing position in the off state region, shifting one column of the remaining cells in the direction in which the output state duration increases, and shifting the boundary between the off state area and the on state area in the direction of decreasing the on state area by one and increasing the off state area by one; and for circuit C, no operation is performed; and a control signal generating operation is performed by generating a control signal to turn on each of the cells located in the on state region, and generating a control signal to turn off each of the cells not located in the on state region.

[0031] In accordance with another aspect of the present invention, the control device is configured such that a counter calculation operation is performed by: providing a counter as output on duration information and output off duration information, wherein the counter is an array including an off state region and an on state region, wherein each of the cells in the off state is located in descending order of the duration of the off output state in the off state, and each of the cells in the on state is arranged in descending order of the duration of the on output state in the on state area; for circuit A, when the priority change switch is set to zero, moving one of the cells located in the OFF state, whose output OFF state duration is the longest of the cells, to the close position in the ON state, when the priority change switch is set to 1, moving one of the cells located in the off state region whose off state duration is the second longest of the cells to the closing position in the on state region, and shifting the remaining cells in the direction in which the output state duration is increased, and shifting the boundary between the off state state and the area of the on state in the direction of decreasing the area of the off state by one and increasing the area of the on state by one; for circuit B, shifting the boundary between the off state region and the on state region in the direction of increasing the off state region by one and decreasing the on state region by one; and for circuit C, no operation is performed; and a control signal generating operation is performed by generating a control signal to turn on each of the cells located in the on state region and generating a control signal to turn off each of the cells not located in the on state region.

[0032] According to another aspect of the present invention, the control device is configured such that a counter calculation operation is performed by: providing a counter as output state on duration information and output state off duration information, wherein the counter is an array, including an off state region and an on state region, wherein each of the cells in the off state is arranged in descending order of the duration of the off output state in the off state, and each of the cells in the on state is arranged in descending order of duration the on output state in the on state area; for scheme A, shifting the boundary between the off state region and the on state region in the direction of increasing the on state region by one and decreasing the off state region by one; for circuit B, when the priority change switch is set to zero, moving one of the cells located in the ON state whose output state ON duration is the longest of the cells to the close position in the OFF state, when the priority change switch is set to 1, moving one of the cells located in the on state region, whose on output state duration is the second longest of the cells, to the closing position in the off state region, and shift one column of the remaining cells in the direction in which the output state duration is increased, and shift the boundary between the off state area and the on state area in the direction of decreasing the on state area by one and increasing the off state area by one; and for circuit C, no operation is performed; and a control signal generating operation is performed by generating a control signal to turn on each of the cells located in the on state region and generating a control signal to turn off each of the cells not located in the on state region.

[0033] In accordance with another aspect of the present invention, the control device is configured such that the switching load sharing control section is configured such that, under a predetermined condition for a circuit causing an on-to-off shift in the cells, turn off the control signal for one of cells whose output on duration is not the longest of the cells, and for the circuit causing the off-to-on shift in cells, turn on the control signal for one of the cells whose off-duration of the output state is not the longest of the cells.

[0034] According to the present invention, it is possible to distribute the switching load among the cells in the control device of the serial multiplex inverter.

Brief description of the drawings

[0035] FIG. 1 is a schematic diagram showing an example of a main circuit configuration of a series multiplex inverter.

Fig. 2 is a block diagram showing the configuration of the system according to the present invention.

Fig. 3 is a block diagram showing a high-level control section.

Fig. 4 is a schematic diagram showing the definition of each cell.

Fig. 5 is an explanatory diagram showing cell voltage state shifts.

Fig. 6 is a flowchart showing a process performed by the switching load sharing control section according to the first to seventh embodiments.

Fig. 7 is a flowchart showing a counter calculation process according to the first embodiment.

Fig. 8 is a graphical representation showing an example of a counter calculation process according to the first embodiment.

Fig. 9 is a flowchart showing a control signal generation process according to the first to fourth embodiments.

10 is a flowchart showing a counter calculation process according to the second embodiment.

Fig. 11 is a graphical representation showing an example of a counter calculation process according to the second embodiment.

Fig. 12 is a flowchart showing a counter calculation process according to the third embodiment.

Fig. 13 is a graphical representation showing an example of a counter calculation process according to the third embodiment.

Fig. 14 is a flowchart showing a counter calculation process according to the fourth embodiment.

Fig. 15 is a graphical representation showing an example of a counter calculation process according to the fourth embodiment.

Fig. 16 is a flowchart showing a counter calculation process according to the fifth embodiment.

Fig. 17 is a graphical representation showing an example of a counter calculation process according to the fifth embodiment.

Fig. 18 is a flowchart showing a control signal generation process according to the fifth embodiment.

Fig. 19 is an explanatory diagram showing the concept of a counter according to the sixth embodiment.

Fig. 20 is a flowchart showing a counter calculation process according to the sixth embodiment.

Fig. 21 is a graphical representation showing an example of a counter calculation process according to the sixth embodiment.

Fig. 22 is a flowchart showing a control signal generation process according to the sixth and seventh embodiments.

Fig. 23 is a graphical representation showing a switching example in which cell voltages do not change between cycles.

Fig. 24 is a flowchart showing a counter calculation process according to the seventh embodiment.

Fig. 25 is a graphical representation showing a behavior example of a counter calculation process according to the seventh embodiment.

Fig. 26 is a flowchart showing a switching load sharing control process according to the eighth embodiment.

Fig. 27 is a diagram showing an example of the relationship between phase voltage and cell voltages in a series multiplex inverter.

Embodiments of the invention

[0036] The present invention is for controlling a serial multiplex inverter. Fig. 1 is a schematic diagram showing the main circuit configuration of a typical series multiplex inverter. Fig. 1 simply shows an example of a serial multiplex inverter, and the present invention can be applied to a serial multiplex inverter configured differently. Next, with reference to FIG. 1, the serial multiplex inverter is assumed to have N cell stages.

[0037] FIG. The serial multiplex inverter 1 includes an input power supply 1, a transformer 2, and an electric power conversion unit 3. In block 3 of the conversion of electrical power Ν (N≥2) cells U ₁ -U _N , V ₁ -V _N , W ₁ -W _N are connected in series in each phase.

[0038] Each cell U ₁ -U _N , V ₁ -V _N , W ₁ -W _N includes a rectifier circuit 13 in which diodes are bridged; a DC coupling section 14 including a capacitor C; and an inverter section 15 in which the switching elements are bridged.

[0039] The rectifier circuit 13 side of each cell U ₁ -U _N , V ₁ -V _N , W1 - W _N is connected to the transformer 2, and the inverter section 15 side is connected in series in each phase. Cells U ₁ , V ₁ , W _{1 of} each phase are connected to each other. In addition, the cell U _N , V _N , W _N of each phase is connected to a load (motor, load LR, etc.). In FIG. 1, the phase voltage of the U-phase is denoted by V _U , and the phase-to-phase voltage between the U-phase and the V-phase is denoted by V _UV .

[0040] In FIG. 2 is a diagram of a system configuration according to the present invention. Fig. 2 shows a system that controls the serial multiplex inverter (power conversion section 3) based on a command value from a control panel or the like to control the current and frequency in a load 4 such as a motor.

[0041] The command value cmd and the measured electric current idet are input to the high level control section 5, which outputs the L* level command based on the control of FIG. 3 as described below. The L* level command is input to the switching load sharing control section 6, which outputs a control signal g in consideration of switching load distribution between cells. Based on the control signal g, switching of the serial multiplex inverter (electrical power conversion section 3) is performed. As the cmd command value, a command value such as an electric current command or a speed command is input according to the configuration of the high level control section 5.

[0042] The present system has a typical configuration using communication load sharing control, which is not limited to FIG. 2. For example, the measured electric current may not be input to the high level control section 5; information about the position of the load (motor) 4 can be returned to the high-level control section 5; the command value may include a plurality of command values such as a d-axis current command and a speed command; and a separate control may be added as a step following the switching load sharing control section 6 to generate a control signal without degrading the effect of switching load sharing.

[0043] FIG. 3 shows a configuration example of the high level control section 5 shown in FIG. 2. In FIG. 3 shows an electric current control circuit without a position sensor. The two-phase to three-phase signal conversion part 7 performs UVW/dq conversion to convert the measured electric current idet. The subtraction part 8 calculates the difference between the command value cmd and the measured electric current idet after UVW/dq conversion. The ACR (automatic current controller) 9 performs PI control or the like based on the difference calculated by the subtraction part 8 and outputs the dq-axis voltage command Vdq*.

[0044] Then, the intermediate voltage superposition part 11 performs dq/UVW conversion and superposition of the intermediate voltage on the dq-axis voltage command Vdq* to generate the UVW-axis voltage command Vuvw*. The PWM modulation part 12 generates an L* level command based on a comparison between the UVW axis voltage command Vuvw* and carrier signals, and outputs the L* level command.

[0045] The phase estimation part 10 calculates the estimated phase θest for the coordinate transformation based on the measured dq-axis electric current idet and the dq-axis voltage command Vdq*. For example, the calculated phase calculation is performed by a combination of the angular velocity estimation based on the model parameters and phase locked loop (Phase Locked Loop, PLL).

[0046] The configuration in FIG. 3 is just an example, and the control can be arbitrarily configured as long as the L* level command is transmitted to the switching load sharing control section 6. That is, the high-level control section 5 may be configured to perform speed control, position control, or electric current control with a sensor. In addition, the sensorless current control may be configured differently without applying an intermediate voltage, or may be configured to set the L* level command in a manner other than triangular wave comparison.

[0047] There is a control method that directly receives a control signal from PWM with triangular wave comparison. However, it is assumed here that only the phase voltage level is determined by comparing the triangular waves. If the configuration of the triangular wave comparison PWM itself cannot be changed, the control signal can be received and then converted to an L* level command based on the circuit configuration.

[0048] The following first to eighth embodiments are described with a control signal determination mechanism for one phase of the series multiplex inverter. However, the present invention is directed to systems that are not limited to a single phase. When used in actual control, the control according to each of the first to eighth embodiments is performed for all phases according to the circuit configuration to determine all control signals.

[0049] In addition, in the series multiplex inverter, a buffer period (dead time) is provided in the control signal to prevent the single-phase inverter of each cell from short circuiting. Although its description is omitted in the present description, the control is actually provided using the dead time appropriately provided in the subsequent step of the switching load sharing control section 6.

[0050] To describe the operation of the embodiment, a single-phase inverter cell is defined as follows. In FIG. 4 shows the cell definition. The transformer 2 and the rectifier circuit 13 are the mechanisms for properly isolating the input power supply 1 and generating a DC voltage in the series multiplex inverter shown in FIG. 1. Since they are not directly related to the purpose of the present invention, their configuration is described in a simplified form. Each switching element in this control can be considered as an ideal switch. Accordingly, ideal switches g1 to g4 are assumed. Regarding the relationship between the operation of the ideal switches g1-g4 and the cell voltage level vcell [level] can be expressed by the mathematical expression (1), considering the polarity of the capacitor, the connection point of the line leading to the neutral point, and the connection point of the line leading to the load.

[0051]

[0052] In the present description, the designation "giX" represents the control signal in the i-th cell, where X(1≤X≤4, X is a natural number) denotes one of the ideal switches g1 to g4 in FIG. 4. For example, g82 represents the control signal corresponding to the ideal switch g2 in FIG. 4 in the eighth cell of the corresponding phase.

[0053] Then, if there is no request for a two-step cell voltage shift, it can be assumed that the cell voltage level vcell is shifted to the states shown in FIG. 5. As shown in FIG. 5, the voltage level of the cell vcell is shifted from the zero level to the +1 level or the -1 level. In the present description, when the cell voltage level vcell is at the zero level, the cell is said to be off, and when the cell voltage level is at ±1, the cell is said to be on.

[0054] In the following description of the first to eighth embodiments, expressions such as on counter and off counter are used, where "on" and "off" in this terminology correspond to "ON" and "OFF" in FIG. 5. The following describes in detail the serial multiplex inverter control device according to the first to eighth embodiments of the present invention.

[0055] <First Embodiment> Next, the policy of the switching load distribution method of each cell is described. The switching load of each cell is not balanced under conditions where a particular cell does not switch for a long time, or under conditions where a particular cell frequently switches in a short time.

[0056] Accordingly, the switching load can be distributed by control so that no cell remains unswitched for a long time, and no cell is switched for a short time. For example, this means that. when cell A is assigned and level-shifted to shift the phase voltage level, there should not be any cell (called cell B) that continues to have the same output state as cell A for a longer period of time.

[0057] If cell B is not assigned, the switching frequency of cell B is relatively low among all cells, so that the switching frequency of cell A is relatively increased since cell A is selected, even if cell A has the longest output state duration. Therefore, to shift the level of the phase voltage, the cell with the longest duration of the output state is assigned and shifted in level. This makes it possible to distribute the switching load of each cell.

[0058] By executing the flowchart of FIG. 6, in the switching load distribution control section 6, the switching can be distributed among the cells of the series multiplex inverter. The following describes the flowchart of the algorithm in FIG. 6. In the block diagram of FIG. 6, the level command L* is input and the control signal g is output. Fig. 6 shows a general block diagram of the operation of the switching load sharing control section 6, wherein the configuration of FIG. 6 is common to the first to seventh embodiments. Operations (3) and (4) are configured differently in each embodiment. In the first embodiment, operation (3) of calculating the counter in FIG. 6 corresponds to FIG. 7 and operation (4) of generating the control signal in FIG. 6 corresponds to FIG. 9.

(1) Enter L* level command,

(2) Perform a schema determination operation to determine the counter operation scheme by observing the changes of the L* level instruction with respect to the output level Lout,

(3) Perform a counter calculation operation to equalize the duration of the output state; while performing another operation depending on the scheme defined by (2),

(4) Perform a control signal generation operation to generate a control signal with reference to the counter value, and

(5) Output control signal.

[0059] Using operations (1)-(5), the switching load of each cell can be distributed.

[0060] The following is a description of operation (2) of defining a schema. To shift the phase voltage level, it is necessary to designate the cell as the cell to be shifted in level, given that the cell can only output +1, 0, -1 levels. For example, when shifting the phase voltage from +2 level to +3 level, if the cell outputting the +1 level is designated as the cell whose level is to be shifted, the cell output cannot be set to +2 level, and the phase voltage cannot be raised to level +3. In this case, the cell assignment is invalid. Thus, cell assignment must be done with care.

[0061] Through the schema determination operation (2), the following three types of branching take place to assign a corresponding one of the cells.

(A) Level shift with cell shift off to on,

(B) Level shift with cell shift from on to off, and

(C) No level shift.

By branching along these three types, invalid cell assignment can be prevented. In step 2-1 in FIG. 6, it is determined whether the instruction level L* is equal to the output level Lout. When the command level L* is not equal to the output level Lout, the process proceeds to step 2-2 in FIG. 6. When the instruction level L* is equal to the output level Lout, the process proceeds to (3)-C in FIG. 6. Thus, it can be determined whether (C) "no level shift" is satisfied. The output level Lout is the current output level of the phase voltage, which is updated by the operation (4) of generating a control signal.

[0062] At step 2-2 in FIG. 6 compare the absolute value of the command level L* and the absolute value of the output level Lout. When the absolute value of the command level L* is greater, the process proceeds to (3)-A. When the absolute value of the L* level command is less, the process proceeds to (3)-B. For (3)-A and (3)-B, it is enough to check whether the phase voltage should shift from zero level or shift to zero level, so the fanout is determined by comparing the magnitude of the absolute value of the command level L* and the absolute value of the output level Lout.

[0063] The following is a description of the operation (3) calculation of the counter. An on counter and an off counter are prepared as counters. Each counter has N columns corresponding to the number of steps of N cells, where the column numbers correspond to the cells. The on counter indicates the duration when the corresponding cell is in the on output state, and the off counter indicates the duration when the corresponding cell is in the off output state.

[0064] The value of each counter indicates the duration of the output state, and as the value increases, the duration of the output state increases. The value of the counter is an integer 0 or more, and when no output is performed, the value of the counter is 0. For example, when the second cell is in the on output state, a positive value is stored in the second column of the enable counter, and a zero is stored in the second column of the counter shutdown.

[0065] The following discusses switching load sharing using meters based on the rules described above. Fig. 7 shows a flowchart of operation (3) of calculating a counter according to the first embodiment. This flowchart corresponds to part (3) in FIG. 6, and there are three types of patterns A, B, and C depending on the result of branching by the pattern determination operation (2). In this flowchart, counter processing and counter incrementing are performed in accordance with the selected level shifting scheme. The counter operation is performed in cases A, B and C as follows.

[0066] <Case (3)-A (OFF->ON)> In step 1-3A-1, the maximum Coff of the off counters is selected. This operation selects the cell with the longest off state duration.

[0067] In step 1-3A-2, the on-count of the selected cell is set to zero. In addition, the on counter of the selected cell in the column corresponding to the selected off counter is set to 1. This operation shifts the level of the selected cell. In addition, by setting the cell on counter Con to 1, the duration of that cell's output state will always be the shortest of the cells in the on output state.

[0068] From 1-3A-3 to 1-3A-7, the value of each positive counter is incremented. A counter whose value is zero is kept unchanged. This is an operation to increase the value of the counter of each cell, indicating the duration of the exit state. For 1-3A-4 and 1-3A-5, a sign function has been introduced, indicating that it increases with a positive value, and does not change with a zero value. The sign function "sign" is determined by the mathematical expression (2). In the present description, each "sign ()" refers to a sign function defined by the mathematical expression (2).

[0069]

[0070] Specifically, in step 1-3A-3, index i is set to 1. In step 1-3A-4, when Con[i] of the on counter of index i is positive, Con[i] of the on counter is incremented, and when Con[ i] of the on counter is zero, Con[i] of the on counter is unchanged. In step 1-3A-5, when index i off counter Coff[i] is positive, off counter Coff[i] is incremented, and when off counter Coff[i] is zero, off counter Coff[i] is not changed. In 1-3A-6, index i is set to i+1. In 1-3A-7, it is determined if index i is less than or equal to N. When index i is less than or equal to N, the process returns to 1-3A-4, and when index i is greater than N, operation (3)-A ends.

[0071] <Case (3)-B (ON->OFF)> In step 1-3B-1, the maximum of the on counters Con is selected. This operation selects the cell with the longest on output state duration.

[0072] In step 1-3B-2 Con of the selected cell on counter is set to zero. In addition, the Coff of the selected cell's off counter in the column corresponding to the selected ON counter is set to 1. This operation shifts the level of the selected cell. Also, by setting Coff of the cell off counter to 1, the duration of that cell's output state will always be the shortest of the cells in the off output state.

[0073] From 1-3B-3 to 1-3B-7, the positive value of each counter is incremented, as in case (3)-A. A counter whose counter value is zero is kept unchanged. This is an operation to increase the value of the counter of each cell, indicating the duration of the exit state.

[0074] <Case (3)-C (no level shift)> In steps 1-3C-1 to 1-3C-5, each counter whose value is positive is incremented. Each counter whose value is zero is kept unchanged. This is an operation to increase the value of the counter of each cell, indicating the duration of the exit state.

[0075] FIG. 8 shows an example of operation (3) of calculating a counter according to the first embodiment, in which four stages of cells are assumed. As described above, when the level is shifted, the level shift is expressed by assigning counters. In either case, A, B, and C each counter is incremented to reflect the duration of the exit state.

[0076] The first shift of the L* level command is an ON->OFF shift, which is performed by operation (3)-B. The cell 2 with the maximum on counter Con is selected, so that Con[2] of cell 2's on counter is set to zero and Coff[2] of the off counter is set to 2.

[0077] Then, the second shift of the L* level command is an OFF->ON shift, which is performed by operation (3)-A. Location 4 is selected, which has the maximum off counter Coff, Coff[4] of the off counter of slot 4 is set to zero, and Con[4] of the on counter is set to 2.

[0078] The third L* command shift is an ON->OFF shift, which is performed by operation (3)-B. The cell 3 having the maximum value Con of the on counter is selected, so that Cop[3] of the cell 3 on counter is set to zero and Coff[3] of the off counter is set to 2. In the first embodiment, the increment is performed immediately after the assignment, so that the counter starts counting from 2 after the level shift. It should be noted that the relationship is constantly maintained, in which, as the value of the counter increases, the duration of the output state of the cell increases.

[0079] The following is a description of the operation (4) of generating a control signal. Fig. 9 shows a flowchart of an operation for generating a control signal according to the first embodiment. This flow chart corresponds to (4) in FIG. 6. N is the number of cell stages, Loutz is the previous output level, Conz is the previous value of the on counter, K is a logical value that determines the zero level mode, giX is the switching element X in the single-phase inverter of the i-th stage cell (1≤i≤N , 1≤Х≤4, i and Х are natural numbers).

[0080] First, the output level Lout is updated based on the L* level command. The update is carried out as follows. When shifting the level, one counter is changed by (3), so that the output level Lout approaches the level instruction L* by one step. When there is no level shift, the Lout output level does not change. In step 1-4-1, the update is expressed by adding the output of the difference sign function between the L* level command and the Lout output level to the Lout output level.

[0081] Then, the level of each cell is determined as follows. When the cell enable counter Con is positive, the cell is enabled (1-4-3). Thus, the cell is set to a level of ±1, and the positive/negative sign of the level is set to the same as that of the output level Lout (1-4-6). When the Con of the cell on counter is zero, the cell is turned off (1-4-3). Thus, the cell is set to the zero level. This assigns the voltage level of each cell according to the counter value.

[0082] Specifically, in step 1-4-2, index i is set to 1. In step 1-4-3, it is determined whether or not the value Con of the on counter is greater than zero. When the enable counter Con is greater than zero, the process proceeds to 1-4-4. When the enable counter Con is not greater than zero, the process proceeds to 1-4-7.

[0083] In step 1-4-4, it is determined whether the previous value Conz of the on counter is less than or equal to zero. When the previous value of Conz on counter is less than or equal to zero, the process moves to 1-4-5. When the previous value of the Conz counter is greater than zero, the process jumps to 1-4-6. In step 1-4-5, the logical value K is toggled.

[0084] In step 1-4-6, it is determined whether the output level Lout is greater than zero. When the output level Lout is greater than zero, the process jumps to 1-4-8. When the output level Lout is less than or equal to zero, the process jumps to 1-4-9.

[0085] In step 1-4-7, when the logical value of K is 1, the process proceeds to 1-4-10, and when the logical value of k is zero, the process proceeds to 1-4-11.

[0086] The control signal of each cell is defined as follows. For clarification, the cell of interest is called cell i. In FIG. 4 shows the relationship between the number of the control signal and its position in the circuit.

[0087] When cell i is to output level +1, it is set in step 1-4-8 so that gi1=1, gi2=0, gi3=0, gi4=1. When cell i outputs level -1, it is set in step 1-4-9 so that gi1=0, gi2=1, gi3=1, gi4=0.

[0088] When cell i is to output a zero level, branching occurs in step 1-4-7 in accordance with the logical value K defining the zero level mode. In the case of K=1, it is set in step 1-4-10, so gi1=1, gi2=0, gi3=1, gi4=0. In the case of K=0, it is set in step 1-4-11 so that g1=0, gi2=1, gi3=0, gi4=1.

[0089] Through this operation, the control signal is set in accordance with the assigned cell voltage level. In the case of level zero, the fanout is done using the boolean value K, which is the control for distributing the load among the elements in the cell. If the control is carried out only by one of the two types of zero-level control signal assignment modes, then at the moment of return, the impact is only on a specific element, which accelerates the wear of the element. To avoid this, the modes are switched every time the zero level is reached.

[0090] In the present description, the logical value K switches at the time when the cell switches from OFF to ON (1-4-4, 1-4-5). This switch may be performed at a different point in time. For example, the switching of the logic value K may be performed at the time of switching from on to off, or may be performed in each period of the main wave. However, if the logic value K switches while cell i continues to output a zero level, all elements switch simultaneously, resulting in a voltage error and/or an increase in switching frequency. Therefore, a switch of the logical value K is performed to avoid this phenomenon.

[0091] Above, cell i is chosen for the purpose of explanation. However, it is necessary to perform these operations on all cells. In step 1-4-12, i is set to i=i+1. In step 1-4-13, when i is less than or equal to N, the process returns to 1-4-3, and when i is greater than N, the process continues to 1-4-14. At the end of (4) (in step 1-4-14), in order to use the previous value Conz of the on counter to switch the logic value K, the current value Con of the on counter is substituted into the previous value Conz of the on counter.

[0092] Through the calculation (4) described above, the control signal can be output in accordance with the counter controlled to share the switching load.

[0093] The foregoing describes FIG. 6 and operation details (3) and (4) in FIG. 6. In view of the above explanation, it can be understood that the control signal g, by which the switching load of each cell is distributed, can be output in accordance with the L* level command set in (1) through the configuration in FIG. 6.

[0094] Thus, with the switching load sharing control of FIG. 6 in the system of FIG. 2, you can control the serial multiplex inverter by distributing the switching load of each cell.

[0095] An important point of the first variant is that the duration of the output state of each cell is expressed by performing a counter increment operation, and the counter is reset in accordance with the phase voltage level shift scheme. The specific calculation method is not limited to the method shown in FIG. 7 and 9.

[0096] As described above, according to the first embodiment, it is possible to optimally distribute the switching load among cells by controlling to preferentially shift the level of the cell having the maximum output state duration by using counters that register output state durations.

[0097] By using separate controls for assigning the voltage level and for generating control signals by which the switching load is distributed, the switching load of each cell can be distributed independently of the way the voltage level is generated.

[0098] In addition, unlike Patent Documents 1-3, there are advantages in that a table is not required, a higher level of distribution is possible than triangular wave comparison based on the PS method, and there is no need to predetermine cell voltages for switching load distribution control.

[0099] <Second Embodiment> In the second embodiment, the switching load is distributed among the cells according to FIG. 6, as in the first version. However, the counter calculation operation (3) is implemented differently than in the first embodiment.

[0100] In the first embodiment, each counter has an integer value greater than or equal to zero, and in the second embodiment, each counter has a value controlled to be negative as well. This serves to reduce the number of counters and reduce the number of registers needed.

[0101] The counter calculation operation (3) according to the second embodiment will be described below. The absolute value of each counter indicates the duration of the output state. When each counter is positive, it indicates an on output state, and when the counter is negative, it indicates an off output state.

[0102] FIG. 10 shows a flowchart of a counter calculation operation according to the second embodiment. Like FIG. 7, this flowchart corresponds to (3) in FIG. 6, in which there are three types of circuits selected depending on the result of branching in (2). The counter operation is performed for cases A, B and C as follows.

[0103] <Case (3)-A (OFF->ON)> In step 2-3A-1, a cell whose counter has a negative value whose absolute value is the largest is selected, that is, a cell which has a minimum counter value is selected. This operation selects the cell with the longest off state duration. In step 2-3A-2, the counter value of the selected cell is set to 1.

[0104] In step 2-3A-3, index i is set to 1. In step 2-3A-4, the counter value is incremented when the counter value is positive. The counter value is decremented when the counter value is negative. This is an operation to increase the absolute value of the counter of each cell, indicating the duration of the output state. Increments and decrements are expressed by summing the counter value and the result of entering the counter value into the sign function. 2-3A-5 and 2-3A-6 are the same as 1-3A-6 and 1-3A-7.

[0105] <Case (3)-B (ON->OFF)> In step 2-3B-1, the cell whose counter has a positive value whose absolute value is the largest is selected, that is, the cell which has the maximum counter value is selected. This operation selects the cell with the longest on output state duration. In step 2-3B-2, the counter value of the selected cell is set to -1.

[0106] In step 2-3B-3 - 2-3B-6, the counter value is incremented when the counter value is positive, and the counter value is decremented when the counter value is negative. This is the operation of incrementing the absolute value of each cell's counter, indicating the duration of the exit state.

[0107] <Case (3)-C (no level shift)> In steps 2-3C-1 to -3C-4, the counter value is incremented when the counter value is positive, and the counter value is decremented when the counter value is negative. This is the operation of incrementing the absolute value of each cell's counter, indicating the duration of the exit state.

[0108] FIG. 11 shows an example of operation (3) of calculating a counter according to the second embodiment. Like the case in FIG. 8, at three level shift times, operations (3)-B, (3)-A, and (3)-B are performed, with cells as destinations being cell 3, cell 4, and cell 2, respectively.

[0109] The first shift of the L* level command indicates the ON->OFF command according to which operation (3)-B is performed. Cell 3 is selected with counter C having a maximum value of 6, and counter C[3] is set to -2. The counters of other cells are incremented or decremented according to the sign of the counter value.

[0110] The second shift of the L* level command indicates an OFF >ON command according to which operation (3)-A is performed. Cell 4 is selected with counter C having a minimum value of -5, and counter C[4] is set to 2. The counters of other cells are incremented or decremented according to the sign of the counter value.

[0111] The last shift of the L* level command indicates the ON->OFF command according to which operation (3)-B is performed. Cell 2 is selected with counter C having a maximum value of 7, and counter C[2] is set to -2. The counters of other cells are incremented or decremented according to the sign of the counter value.

[0112] By reducing the number of counters to half compared with the first embodiment, the relative ratio between the on-off durations of the output state and the relative ratio between the off-state durations of the output are maintained.

[0113] In the second embodiment, only the counter calculation operation (3) is modified, and (4) is performed by the configuration of FIG. 9. However, since the on counter Con does not exist, the on counter Con is read as counter C. In addition, the previous value of the on counter Conz is read as Cz.

[0114] It is for 1-4-3 and 1-4-4 that reading is relevant. As for 1-4-3, the reading is not a problem, because in the first case, when the On counter is positive, the cell is on, and in the second case, when the C counter is positive, the cell is on. That is, when the value of counter C is positive, a control signal is generated to turn on the cell, and when the value of counter C is negative, a control signal is generated to turn off the cell.

[0115] Also, with regard to 1-4-4, the indication does not change the branch value and does not cause problems, because when the previous value Conz of the on counter is zero, it means the OFF state in the first embodiment, and when the previous value of the counter Cz is negative, this means an OFF state in the second embodiment.

[0116] With the modifications described above, it is possible to realize the control of a serial multiplex inverter in which a switching load is distributed with fewer registers than in the first embodiment. As in the first embodiment, the details of the calculation method of the second embodiment are not limited to FIG. 10 and 9.

[0117] As described above, according to the second embodiment, it is possible to optimally distribute the switching load among the cells by controlling to preferentially shift the level of the cell having the maximum output state duration by using counters that register the output state duration by positive and negative values. In addition, this can be implemented with fewer registers than the first embodiment, as well as the third and fifth embodiments described below.

[0118] In addition, unlike Patent Documents 1-3, there are advantages in that a table is not required, a higher level of distribution is possible than triangular wave comparison based on the PS method, and there is no need to predetermine cell voltages for switching control load sharing.

[0119] <Third Embodiment> In the first and second embodiments, the duration of the output state of the cell is expressed by increasing (or decreasing) in each branch.

[0120] For example, consider circuit X and circuit Y, where circuit X is a circuit in which the phase voltage shifts from +1 to +2 at time t1 [s], and where circuit Υ is a circuit in which the same level shift (+1->+2) consists of no level shift during the period from t1 [s] to t1+0.1 [s] and a level shift from level +1 to level +2 at time t1 +0.1[s].

[0121] In the configurations of the first and second embodiments, the increment (or decrement) is performed continuously so that the value of the counter immediately before the counter assignment operation is greater in the case of schema Y than in the case of schema X.

[0122] However, for cell assignment, the relative relationship between counter values does not differ between circuit X and circuit Y, and circuit X and circuit Υ have the same offset +1->+2, so that the same cell must be level-shifted as in scheme X, and in scheme Υ. In view of this, it is clear that the assignment of a cell for switching load distribution in the circuit Υ can be achieved without increasing any counter value at time t1 [s].

[0123] That is, the key point in switching load sharing control is the relative relationship of whether a cell has a longer or shorter output state duration than other cells, while the absolute value of the counter (or time) itself does not matter.

[0124] In view of the above, in the third embodiment, the control is performed such that the duration of the output state of each cell is processed only in terms of relative relationship. In the first and second embodiments, the counters are continuously incremented, which requires counter overflow control. However, this need not be taken into account in the third embodiment.

[0125] Modifications from the first embodiment to the third embodiment are only in operation (3) of calculating the counter. Next, the counter calculation operation (3) according to the third embodiment will be described.

[0126] There are two types of counters, an on counter and an off counter.

As the counter value increases, the duration of the output state increases relative to other cells. To express only the relative ratio of the duration of the output state, the counters are incremented only when there is a level shift, and do not increment when there is no level shift.

[0127] FIG. 12 shows a flowchart of a counter calculation operation according to the third embodiment. Like FIG. 7, this flowchart corresponds to (3) in FIG. 6, where there are three types of flowcharts selected depending on the result of branching in (2). The counter operation is performed for cases A, B and C as follows.

[0128] <Case (3)-A (OFF->ON)> In step 3-3A-1, the maximum Coff of the off counters is selected. This operation selects the cell with the longest off state duration.

[0129] In step 3-3A-2, Coff of the selected cell off counter is set to zero. In addition, the Con of the on counter of the selected cell in the column corresponding to the selected Coff of the off counter is set to 1. This operation shifts the level of the selected cell. Also, by setting the cell on counter Con to 1, the duration of that cell's output state will always be the shortest of the cells in the on output state.

[0130] In steps 3-3A-3 to 3-3A-6, the positive value Con of each on counter is incremented. Each enable counter whose counter value is zero is kept unchanged. This is an operation to increase the absolute value for the value of the counter of each cell, indicating the duration of the output state. Unlike the first embodiment, in the third embodiment, only the Con of the on counters are incremented, while the Coffs of the off counters remain unchanged.

[0131] <Case (3)-B (ON->OFF)> In step 3-3B-1, the maximum is selected from Con of the on counters. This operation selects the cell with the longest on output state duration.

[0132] In step 3-3B-2, Con of the selected cell on counter is set to zero. In addition, the Coff of the selected cell's off counter in the column corresponding to the selected on counter's Con is set to 1. This operation shifts the level of the selected cell. In addition, by setting Coff of the cell off counter to 1, the duration of that cell's output state will always be the shortest of the cells in the off output state.

[0133] In steps 3-3B-3 to 3-3B-6, the Coff value of each off counter that is positive is incremented. Each shutdown counter whose counter value is zero is kept unchanged. This is an operation to increase the absolute value for the value of the counter of each cell, indicating the duration of the output state. Unlike the first embodiment, in the third embodiment, only the Coffs of the off counters are incremented, while the Con of the on counters remain unchanged.

[0134] <Case (3)-C (no level shift)> In the third embodiment, no operation is performed in step (3)-C. This is to prevent unnecessary increment of counter values.

[0135] FIG. 13 shows an example of operation (3) of calculating a counter according to the third embodiment. While the maximum counter value is 7 in FIG. 8 (first embodiment), the maximum value of the counter is 4 in FIG. 13, where the relative relationship between output on durations and output off durations can be maintained without unnecessarily incrementing the counters. Like the case in FIG. 8, processes (3)-B, (3)-A, and (3)-B are executed at three level shift times, with assignment being made to cell 3, cell 4, and cell 3, respectively.

[0136] The first shift of the L* level command is an ON->OFF shift, which is performed by operation (3)-B. Location 2 is selected whose counter Con[2] has a maximum value of 4, so that counter Con[2] is set to zero and counter Coff[2] is set to 2. In addition, of the shutdown counters Coff, the value of counter Coff[4] , which is positive, increases.

[0137] The second shift of the L* level command indicates the OFF->ON command according to which operation (3)-A is performed. Cell 4 is selected whose counter Coff has a maximum value of 3, so that Coff[4] of the counter is set to zero and Con[4] of the counter is set to 2. In addition, of the enable counters Con, Con[1] and Con[3] , which are positive, increase.

[0138] The last shift of the L* level command indicates the ON->OFF command according to which operation (3)-B is performed. Location 3 is selected whose counter Con[3] has a maximum value of 4, so that counter Con[3] is set to zero and counter Coff[3] is set to 2. In addition, of the shutdown counters Coff, the value of counter Coff[2] , which is positive, increases.

[0139] Since the increase is also performed at the level shift, the counter value immediately after the level shift starts from 2.

[0140] In the third embodiment, only the counter calculation operation (3) is modified, and (4) is performed by the configuration of FIG. 9. With the modifications described above, switching load sharing control can be implemented without the need to consider overflow. As in the first embodiment, the details of the calculation method are not limited to FIG. 12 and 9.

[0141] As described above, according to the third embodiment, the switching load of each cell can be optimally distributed by controlling for the preferential level shift of the cell having the maximum output state duration by using counters that register the output state durations in a relative ratio. It also prevents overflows due to constantly incrementing counters.

[0142] In addition, unlike Patent Documents 1-3, there are advantages in that a table is not required, a higher level of distribution is possible than triangular wave comparison based on the PS method, and there is no need to predetermine cell voltages for switching load distribution control.

[0143] <Fourth Embodiment> The third embodiment uses an on counter and an off counter. The number of counters can be halved by using negative counter values as in the second embodiment.

[0144] Like the second embodiment, each counter is considered to indicate an ON state when it is positive, and indicate an OFF state when it is negative. In addition, similarly to the third embodiment, an unnecessary increase in counter values is eliminated. Fig. 14 shows a flowchart of the counter calculation operation according to the fourth embodiment. Like FIG. 7, this flowchart corresponds to (3) in FIG. 6, and there are three types of flowcharts selected depending on the branching result in (2). The calculation operation of the counter is performed in cases A, B and C as follows.

[0145] <Case (3)-A (OFF->ON)> In step 4-3A-1, a cell whose counter has a negative value whose absolute value is the largest is selected, that is, a cell which has a minimum counter value is selected. This operation selects the cell with the longest off state duration.

[0146] In step 4-3A-2, the selected cell counter value is set to 1.

[0147] In steps 4-3A-3 to 4-3A-6, the counter value is incremented when the counter value is positive. When the counter value is less than or equal to zero, the counter value is kept unchanged. This is the operation of incrementing the absolute value of the counter value of each cell indicating the duration of the output state.

[0148] The increase is expressed by adding the result of comparing whether the counter value is positive. The value of the counter is not a boolean value, but the result of the comparison is usually output as a boolean value and converted to an integer value, etc., as appropriate. and is added, with the description of the transformation omitted.

[0149] <Case (3)-B (ON -> OFF)> In step 4-33-1, a cell whose counter has a positive value whose absolute value is the largest is selected, that is, the cell which has the maximum counter value is selected. This operation selects the cell with the longest on output state duration.

[0150] In step 4-3B-2, the counter value of the selected cell is set to -1.

[0151] In step 4-3B-3-4-3B-6, the counter value is maintained unchanged,

when the counter value is positive, and the counter value is decremented when the counter value is negative. This is the operation of incrementing the absolute value of the counter value of each cell indicating the duration of the output state.

[0152] <Case (3)-C (No Level Shift)> In the fourth embodiment, in step (3)-C, no operation is performed. This is to prevent unnecessary increment of counter values.

[0153] FIG. 15 shows an example of the behavior of operation (3) of count calculation according to the fourth embodiment. As in the third embodiment, the counter having the maximum absolute value is ±4 in FIG. 15, while the maximum counter value is 7 in FIG. 8. Without unnecessarily incrementing counter values, it is possible to maintain a relative relationship between the durations of the on output state and the duration of the off state of the output state.

[0154] Similar to the case in FIG. 8, at three level shift times, operations (3)-B, (3)-A, and (3)-B are performed, with cells as destinations being cell 3, cell 4, and cell 2, respectively.

[0155] The first shift of the L* level command indicates the ON->OFF command according to which operation (3)-B is performed. Cell 2 is selected with counter C[2] having a maximum value of 4, and counter C[2] is set to -2. Of counters C, counter C[4], which is negative, is decremented.

[0156] The second shift of the L* level command indicates the OFF->ON command according to which operation (3)-A is performed. Cell 4 is selected with counter C[4] having a minimum value of -3, and counter C[4] is set to 2. Of counters C., counters C[1] and C[3], which are positive, are incremented.

[0157] The last shift of the L* level command indicates the ON->OFF command according to which operation (3)-B is performed. Cell 3 is selected with counter C[3] having a maximum value of 4, and counter C[3] is set to -2. Of counters C, counter C[2], which is negative, is decremented.

[0158] Since the increase or decrease is also performed at the level shift, the counter value immediately after the level shift starts from ±2.

[0159] In the fourth embodiment, only the counter calculation operation (3) is modified, and (4) is performed by the configuration of FIG. 9 (second option).

[0160] With the modifications described above, switching load sharing control can be implemented without the need to consider overflow. As in the first embodiment, the details of the calculation method are not limited to FIG. 14 and 9.

[0161] As described above, according to the fourth embodiment, it is possible to optimally distribute the switching load among the cells by controlling to preferentially shift the level of the cell having the maximum output state duration by using counters that register output state durations by positive and negative values in a relative relationship. .

[0162] In addition, this can be implemented with fewer registers than in the first embodiment and the third and fifth embodiments described below. It also prevents overflows due to constantly incrementing counters.

[0163] In addition, unlike Patent Documents 1-3, there are advantages in that a table is not required, a higher level of distribution is possible than triangular wave comparison based on the PS method, and there is no need to predetermine cell voltages for switching load distribution control.

[0164] <Fifth Embodiment> Although the constant increase of counter values causes an overflow problem in the first and second embodiments, the counter values increase only at the level shift in the third and fourth embodiments, which serves to minimize the absolute values for the counter values.

[0165] The focus of the third and fourth embodiments is "the relative duration of the output state in all cells". That is, to perform the switching load sharing control, it is sufficient that the durations of the output states can be ranked among the cells. In the third and fourth embodiments, the durations of output states among cells are ranked according to the relative relationship between counter values. The ranking can be done in another way.

[0166] In the fifth embodiment, switching load balancing is performed in which storage positions in the array are considered as indicating ordinal ranks.

[0167] Next, the counter calculation operation (3) according to the fifth embodiment will be described. There are two types of counters: the on counter and the off counter. Each counter value specifies a cell number, and as the index value of the column that stores the cell number decreases, the duration of the output state increases relative to other cells. To represent the relative relationship of output state duration, the values in the array are swapped when the level is shifted.

[0168] The on counter and the off counter each should have N columns for the number of N steps of cells. However, since the number of valid columns varies depending on the output level, zero is stored in invalid columns. For example, when the output level is +2, there are two on counter cells, the cell numbers are stored in the first and second columns of the on counter, and zero is stored in the third to Nth columns.

[0169] Since the stored values are cell numbers and no increment operation is performed, the name "counter" may be inappropriate. However, for convenience, it is referred to as a "counter" due to its correspondence to the first to fourth embodiments.

[0170] FIG. 16 shows a flowchart of the counter calculation operation according to the fifth embodiment. Like FIG. 7, this flowchart corresponds to (3) in FIG. 6, in which there are three types of flowcharts selected depending on the branching result in (2). The counter operation is performed for cases A, B and C as follows.

[0171] <Case (3)-A (OFF->ON)> In step 5-3A-1, the value in the first column of the off counter is temporarily stored as G. This means that the cell with the longest off duration is selected.

[0172] In step 5-3A-2, index i is set to i=1. In step 5-3A-3, it is determined whether the index i=1. When i=1, the process proceeds to step 5-3A-5, otherwise the process proceeds to 5-3A-4.

[0173] In step 5-3A-5, it is determined whether Con[i]=0 of the on counter. When Con[i]=0, the process proceeds to step 5-3A-6, otherwise the process proceeds to 5-3A-7.

[0174] In step 5-3A-4, it is determined whether Con[i]=0 and Con[i-l]>0. When both conditions are satisfied, the process proceeds to step 5-3A-6, and when at least one of them is not satisfied, the process proceeds to 5-3A-7. In step 5-3A-6, G is assigned to Con[i] of the on counter.

[0175] That is, in steps 5-3A-3 to 5-3A-6, G is substituted in the closing position in the on counter. "Closing position" corresponds to an index that is one greater than the maximum index with a non-zero value. When all columns are null, G is substituted in the first column. This operation causes a level shift with the selected cell having the shortest on duration.

[0176] In step 5-3A-7, it is determined whether i=N. When i=N, the process proceeds to step 5-3A-9, otherwise the process proceeds to step 5-3A-8. In step 5-3A-9, Coff[i] is set to Coff[i]=0, and in step 5-3A-8, Coff[i] is set to Cofffi]=Coff[i+1]. This is an operation to shift the counter values by one column to fill in response to the on event of the cell with the longest off duration. That is, in steps 5-3A-7 to 5-3A-9, each turn-off counter in the second and subsequent columns is shifted to an index one less. The value of zero is substituted in the Nth column.

[0177] In step 5-3A-10, index i is set to i=i+1. In step 5-3A-11, it is determined whether index i is less than or equal to N. When index i is less than or equal to N, the process returns to 5-3A-3, and when index i is greater than N, operation (3)-A ends.

[0178] <Case (3)-B (ON->OFF)> In step 5-3B-1, the value in the first column of the on counter is temporarily stored as G. This means that the cell with the longest on duration is selected.

[0179] That is, in steps 5-3B-3 to 5-3B-6, G is substituted in the closing position in the off counter. This operation causes a level shift with the selected cell having the shortest off duration.

[0180] In steps 5-3B-7 through 5-3B-9, each turn-on counter in the second and subsequent columns is shifted to an index one less. The value of zero is substituted in the Nth column. This is an operation to shift the counter values by one column to fill in response to the off event of the cell with the longest on time.

[0181] <Case (3)-C (no level shift)> In the fifth embodiment, no operation is performed in step (3)-C. In the configuration of the fifth embodiment, it is sufficient to maintain ranging at the time of layer shift, so that no operation is required at the time when there is no layer shift.

[0182] FIG. 17 shows an example of operation (3) of count calculation according to the fifth embodiment. The first through fourth embodiments are shown in a timing diagram format to represent incrementing counter values, but for clarity, the behavior of the fifth embodiment is shown as an array because the fifth embodiment does not have an increment operation. Fig. 17 also shows the level shift behavior.

[0183] Similar to the case in FIG. 8, three times the level shift

operations (3)-B, (3)-A and (3)-B are performed, while cell 3, cell 2 and cell 4 are shifted in level, respectively.

[0184] The first shift of the L* level command is +3->+2 (ON->OFF) shift, which is performed by operation (3)-B. Selects location 3 in the first column Con of the on counter and moves to the close position in Coff of the off counter. In addition, the second and subsequent columns Con of the inclusion counter are shifted one column to fill.

[0185] The second shift of the L* level command is +2->+3 shift

(OFF->ON), which is carried out by operation (3)-A. Selects location 2 in the first column Coff of the off counter and moves it to the close position of the counter in Con of the on counter. In addition, the second and subsequent Coff columns of the off counter are shifted one column to fill.

[0186] The third shift of the L* level command is +3->+2 (ON->OFF) shift, which is performed by operation (3)-B. That is, cell 4 in the first column Con of the on counter is selected and moved to the close position in Coff of the off counter. In addition, the second and subsequent columns Con of the inclusion counter are shifted one column to fill.

[0187] It should be noted that the relationship remains that when the index in the array decreases, the duration of the exit state increases, and when the index increases, the duration of the exit state decreases.

[0188] Next, operation (4) of generating a control signal according to the fifth embodiment will be described. In the fifth embodiment, the value of the counter values is different from the values in the first to fourth embodiments, which requires modification of the control signal generating operation mechanism.

[0189] FIG. 18 is a flowchart of operation (4) of generating a control signal according to the fifth embodiment. This flow chart corresponds to (4) in FIG. 6. Symbol definition is the same as in FIG. 9.

[0190] First, what is changed from FIG. 9 is a method for assigning cell levels, while it is not necessary to modify the operation associated with assigning the control signal and the output level Lout after the cell levels have been assigned. That is, steps 5-4-1 to 5-4-2 and 5-4-5 to 5-4-14 are based on the same concept as 1-4-1-1 to 1-4- 2 and 1-4-. 5 to 1-4-14, and their description is omitted.

[0191] In step 5-4-3, branching occurs depending on whether cell i is included. This can be done by checking if the value i exists in the enable counter. When i exists, cell i is enabled. That is, a control signal is generated to turn on cells located in the on counter, and a control signal is generated to turn off cells not located in the on counter.

[0192] Step 5-4-4 is a branch point for inversion K, which denotes the zero level mode, where the case where cell i switches from off to on is to be found. Accordingly, branching occurs depending on whether the value i exists in the previous value Conz of the on counter.

[0193] With the modifications described above, the control signals can be assigned according to the setting of the counters also in the fifth embodiment.

[0194] Meanwhile, in the fifth embodiment, the maximum value of the counter is equal to the number of cell stages N, and there is no possibility that each counter becomes unnecessarily large as in the first embodiment. Therefore, using Fig. 16 and 18 of the fifth embodiment in the configuration of FIG. 6, switching load sharing control can be performed to solve the overflow problem in the first embodiment.

[0195] In addition, as in the previous embodiments, the details of the calculation method are not limited to FIG. 16 and 18.

[0196] As described above, according to the fifth embodiment, the switching load of each cell can be optimally allocated by controlling to preferentially shift the level of the cell having the maximum output state duration by using an array that includes storage positions indicating the output state duration. In addition, you can prevent overflow due to constantly incrementing counters.

[0197] In addition, unlike Patent Documents 1-3, there are advantages in that no table is required, a higher level of distribution is possible than triangular wave comparison based on the PS method, and there is no need to predetermine cell voltages for managing the distribution of communication load.

[0198] <Sixth Embodiment> In the second and fourth embodiments, by using negative counter values, the number of counters can be reduced compared to the first and third embodiments. The number of counters can also be reduced in the fifth embodiment by using negative counter values. However, embodiments handling negative counter values are omitted because operation can be further simplified by reducing the number of counters in another way.

[0199] In the sixth embodiment, the number of counters is reduced and operation is simplified compared to the fifth embodiment by changing the reference position of the counter based on output level information.

[0200] The following describes the counter calculation operation (3) according to the sixth embodiment. The counter is configured to have N columns corresponding to the number of N steps of cells, with each counter value indicating a cell number. The cells in the output level Lout columns from the rightmost column are considered to be cells in the on state, and the remaining cells are cells that are in the off state. In each of the ON and OFF regions, the left of the two arbitrary cells has a longer output state duration than the right of the two arbitrary cells.

[0201] FIG. 19 summarizes the concept of the counter. When L=+3, cell 2 is stored in the off state region, and cell 3, cell 4, and cell 1 are stored in the on state region. When L=+2, cells 2 and 3 are stored in the off state region, and cells 4 and 1 are stored in the on state region. Even with the same values of the counter, it changes depending on the output level Lout, regardless of whether cell 3 is on or off.

[0202] FIG. 20 shows a flowchart of a counter calculation operation according to the sixth embodiment. Like FIG. 7, this flowchart corresponds to (3) in FIG. 6, where there are three types of flowcharts selected depending on the result of branching in (2). The counter operation is performed for cases A, B and C as follows.

[0203] <Case (3)-A (OFF->ON)> In step 6-3A-1, the value in the first column of the counter is temporarily stored as G. This means that the cell with the longest off duration has been selected.

[0204] In step 6-3A-2, i is set to i=1. In step 6-3A-3, it is determined whether i=N. When i=N, the process goes to step 6-3A-5, otherwise the process goes to step 6-3A-4.

[0205] In step 6-3A-5, G is assigned to the last column (Nth column) C[N] of the counter. In this case, the level is shifted for the selected cell that has the shortest on duration.

[0206] In step 6-3A-4, C[i] is set to C[i]=C[i+1], and each of the counters in the second and subsequent columns moves to the next lower index. This is an operation to move the value of the counter with the longest off duration (in the first column) to the on state and accordingly shift the counter values by one column to fill.

[0207] In step 6-3A-6, index i is incremented. In step 6-3A-7, it is determined whether index i is less than or equal to N. When index i is less than or equal to N, the process returns to step 6-3A-3, and when i is greater than N, operation (3)-A ends.

[0208] <Case (3)-B (ON->OFF)> In the sixth embodiment, no operation is performed in step (3)-B. The counter calculation operation (3)-B is not required because when the output level Lout is updated by the control signal generation operation (4), the off state area is expanded, and the cell With maximum output state duration in the on state area is automatically shifted to the off state.

[0209] <Case (3)-C (no level shift)> In the sixth embodiment, no operation is performed in step (3)-C. The sixth option is based on the configuration of the fifth option, and in the configuration of the sixth option, it is sufficient to maintain the ranking at the time of the level shift, and it is not necessary to perform the operation at the time of no level shift.

[0210] FIG. 21 shows a behavior example of operation (3) of count calculation according to the sixth embodiment. This is shown as an array, as in the fifth embodiment. Fig. 21 shows the operation behavior when the level shifts. Like the case in FIG. 8, at three level-shift times, operations (3)-B, (3)-A, and (3)-B are performed, with cell 3, cell 2, and cell 4 being level-shifted, respectively. The output level Lout is made to follow the command of the L* level by the operation (4) of generating a control signal.

[0211] The first shift of the L* level command is +3->+2 (ON->OFF) shift, which is performed by operation (3)-B. When performing operation (3)-B, the array of counters does not change. However, the boundary between the on state region and the off state region is shifted so that cell 3 belongs to the off state region.

[0211] The first shift of the L* level command is +3->+2 (ON->OFF) shift, which is performed by operation (3)-B. During operation (3)-B, the array of counters does not change. However, the boundary between the on state region and the off state region is shifted so that cell 3 belongs to the off state region.

[0212] The second shift of the L* level command is +2->+3 (OFF ->ON) shift, which is performed by operation (3)-A. Cell 2, which has the maximum duration of the off state, moves to the closing position. In addition, the boundary between the on state region and the off state region is shifted.

[0213] The last shift of the L* level command is +3->+2 (ON->OFF) shift, which is performed by operation (3)-B. During operation (3)-B, the array of counters does not change. However, the boundary between the on state region and the off state region is shifted so that cell 4 belongs to the off state region.

[0214] In each of the on and off areas of the array, the relationship is constantly maintained, and as the index decreases, the duration of the output state increases, and as the index increases, the duration of the output state decreases. In addition, except for the cell having the longest output state duration, no cell is shifted in level as a result of changes in the on state region and the off state region.

[0215] Next, the control signal generating operation (4) according to the sixth embodiment will be described below. Like the fifth embodiment, the cell numbers are stored in the counter, but the introduction of on and off regions requires modifications to the operation (4) of generating the control signal.

[0216] FIG. 22 shows a flowchart of a control signal generation operation according to the sixth and seventh embodiments. This flow chart corresponds to (4) in FIG. 6. Symbol definition is the same as in FIG. 9. However, unlike the first through fourth embodiments shown in FIG. 9, the on counter Con does not exist in the sixth and seventh embodiments, but instead, there is a counter C. In addition, the correction counter Ccmp and the previous value Ccmpz of the correction counter are used as new symbols.

[0217] Steps 6-4-1, 6-4-4 and 6-4-7 to 6-4-16 are based on the same concept as 5-4-1, 5-4-2 and from 5 -4-5 to 5-14 of the fifth embodiment, and their description is omitted.

[0218] Steps 6-4-2 and 6-4-3 are operations for generating a value equivalent to the on counter of the fifth embodiment. A temporary correction counter Ccmp is created separately from the counter values to be stored, and the contents of counter C are temporarily copied to the correction counter Ccmp. Then, the columns corresponding to the off state area (columns 1 to (Lout-N) th) are set to zero. By this operation, only the number of each cell to be turned on remains in the correction counter Ccmp, and the output level of the cell can be assigned.

[0219] In step 6-4-2, the assignment of the array is performed, which is not an assignment of the starting address of the array, as in the C (C) language descriptions, but is carried out by appropriately copying the contents of the array.

[0220] Steps 6-4-5 and 6-4-6 are operations for assigning a cell level, and are performed in the same manner as 5-4-3, 5-4-4, because in operations 6-4-2 and 6-4-3, the correction counter Ccmp corresponds to the on counter according to the fifth embodiment. That is, when the value of i exists in the counter, cell i is enabled. Thus, the control signal of each cell located in the on state region can be turned on, and the control signal of each cell not located in the on state region can be turned off.

[0221] With the modifications described above, the control signals can be assigned according to the setting of the counters also in the sixth embodiment.

[0222] The counter may be configured to have an on state region on the left side and an off state region on the right side, or may be configured such that the left of two arbitrary cell numbers has a shorter output state duration than the right of two arbitrary cell numbers. This setting is optional, but, for example, in a configuration in which the on state area is provided on the left side and the off state area is provided on the right side, operation (3)-A is omitted, and when (3)-B, the value in the first column is substituted to the last column. It should be noted that the configuration of the counter calculation operation must be changed in this way.

[0223] In addition, depending on the combination of the method of setting the on state area and the off state region and the method of processing the output state duration amount, the on state region and the off state region may be discontinuous with respect to each other, instead of a continuous array region, so that it may be necessary to additional operation.

[0224] The fifth embodiment uses 2N counters, but it is sufficient that the sixth embodiment uses N counters. Compared with the fifth embodiment, operation (3)-B is omitted, and as can be seen from comparison (3)-A in FIG. 16 and (3)-A in FIG. 20 the number of operations is also reduced in (3)-A.

[0225] Thus, using FIG. 20 and 22 of the sixth embodiment in the configuration of FIG. 6, it is possible to realize the switching load sharing control in which the number of counters is halved compared with the fifth embodiment and the calculation operation is simplified. As in the previous embodiments, the details of the calculation method are not limited to FIG. 20 and 22.

[0226] As described above, according to the sixth embodiment, the switching load of each cell can be optimally allocated by controlling to preferentially shift the level of the cell having the maximum output state duration by using an array that includes storage positions indicating the output state duration.

[0227] In addition, overflow due to constantly incrementing counters can be prevented. In addition, it can be implemented with fewer registers than the first, third, and fifth embodiments. In addition, the process can be simplified compared to the first to fifth embodiments.

[0228] In addition, unlike Patent Documents 1-3, there are advantages in that a table is not required, a higher level of distribution is possible than triangular wave comparison based on the PS method, and there is no need to predetermine cell voltages for switching load distribution control.

[0229] <Seventh Embodiment> In the first to sixth embodiments, the flowchart is designed to continuously select the cell having the longest output state duration with higher priority and shift the level of the selected cell. However, a problem may occur when the number of switching operations is very small for one cycle of the output voltage (one cycle of the main wave), and the switching is performed in synchronism with the output voltage.

[0230] FIG. 23 shows an example of a switch causing a problem. Fig. 23 shows an example of four cell stages in which the phase voltage is level-shifted four times per quarter cycle and the synchronous output is sinusoidal. In this situation, the cells switch in order of increasing duration of the output state, while comparing the voltages of the cells, it can be seen that each cell is responsible for the same part of each main wave in two cycles. If the waveform continues steadily, the voltage of each cell should be responsible for the same part in each cycle. That is, the output time of each cell is fixed in each cycle.

[0231] When the element is turned on, the electric current flows along the path through the capacitor and the DC voltage fluctuates in accordance with the polarity of the electric current. If the number of switching operations is large, or if the switching is performed at random times, the polarity during the on period is not fixed and the DC voltage is likely to be maintained at an average. However, when the cell output state time is fixed in accordance with one fundamental wave cycle, the turn-on time and cell current polarity are fixed. Accordingly, the fluctuation of the DC voltage in each cycle has the same polarity, thereby causing the problem that the DC voltage becomes zero or continues to rise.

[0232] In order to avoid this problem, the seventh embodiment is configured to deliberately deviate from the optimal designation of the cell to be shifted, and thereby prevent the DC voltage problem from occurring. If a deviation from the optimal assignment is carried out, for example, by random selection of a cell, a problem may arise in which the degree of distribution of the switching load is locally degraded and the losses cannot be balanced.

[0233] Thus, control is considered below, which accordingly deviates from the optimal point by making modifications to the embodiments of the present invention described above. Next, the case where a simple modification of the sixth embodiment is made will be explained.

[0234] First, the counter calculation operation (3) is described next. Fig. 24 shows a flowchart of a counter calculation operation according to the seventh embodiment. Like FIG. 7, this flowchart corresponds to (3) in FIG. 6, and there are three types of flowcharts selected depending on the branching result in (2).

[0235] As shown in FIG. 24, variable Ρ is added to 7-3A-1. Ρ is a priority change switch and is a boolean value.

[0236] In step 7-3A-1, it is determined whether the priority change switch Ρ is equal to zero. When the priority change switch P=0, in 7-3A-2, the value in the first column of the counter is changed to G, as in the sixth embodiment. When the priority change switch P=1, in 7-3A-3, the value in the second column is substituted into G. This allows not only the operation of selecting the cell with the longest off duration, but also the operation of selecting the cell having the second longest off duration to be performed.

[0237] The priority change switch Ρ is generally set to zero, so that the cell having the longest output state duration is selected to perform optimal switching load sharing. When the switch causes a problem, the priority change switch Ρ switches to 1 accordingly. For example, the priority change switch Ρ may switch between 1 and 0 every half cycle of the main wave. However, it should be noted that for the transition to the ±N level, which is the maximum level of the N-stage configuration, an incorrect cell assignment occurs unless the priority change switch Ρ is set to zero.

[0238] In step 7-3A-4, index i is set to i=1, and in step 7-3A-5, index i is set to i=2. In step 7-3A-5, the loop starts from the second column because the second column has priority and the element of the first column must not be shifted.

[0239] In steps 7-3A-6 to 7-3A-10, similarly to 6-3A-3 to 6-3A-7 of the sixth embodiment, the assigned cell is moved to the last column, and the other cells are shifted one column to fill . The above-mentioned method of operation of the counter deviates from the optimal one.

[0240] FIG. 25 shows an example of a counter calculation operation according to the seventh embodiment. Since the seventh embodiment is based on the sixth embodiment, the operation is almost the same as in FIG. 21. However, since Ρ=1 is set, the second level shift is done by selecting and including cell 3 in the second column. In the sixth embodiment, cell 3, cell 2, and cell 4 have a level offset, and in the seventh embodiment, cell 3, cell 3, and cell 4 have a level offset. Also, in the seventh embodiment, the relative relationship between the durations of the exit state is not broken, but is maintained.

[0241] The foregoing describes the counter calculation operation (3) according to the seventh embodiment. The operation (4) of generating a control signal may be used as shown in FIG. 22 so that with the help of FIG. 24 and 22 in FIG. 6, it is possible to perform switching load distribution control deviating from the optimum.

[0242] Although the method is performed by selecting the cell having the second longest output state duration in the OFF->ON case, the method can be implemented by selecting the second cell in the ON->OFF case. In addition, in case of a deviation, the cell having the third or next longest exit state duration may be selected.

[0243] In addition, although the deviation method was discussed based on the sixth embodiment, the method can be based on the first to fifth embodiments, since the essence of this control is to intentionally select a cell deviating from the optimum. As in the previous embodiments, the details of the calculation method are not limited to FIG. 24.

[0244] As described above, according to the seventh embodiment, high-level switching load sharing between cells can be achieved by controlling for preferential level shifting of the cell having the maximum output state duration by using an array including storage positions indicating the output state duration. In addition, overflow can be prevented by continuously incrementing the counters.

[0245] In addition, the embodiment can be implemented with fewer registers than the first, third, and fifth embodiments. In addition, the process can be simplified compared to the first to fifth embodiments. In addition, DC voltage anomaly can be prevented when the number of switching operations in one cycle of the main wave is small.

[0246] In addition, unlike Patent Documents 1-3, there are advantages in that a table is not required, a higher level of distribution is possible than triangular wave comparison based on the PS method, and there is no need to predetermine cell voltages for switching load distribution control.

[0247] <Eighth Embodiment> The first to seventh embodiments described above are based on the case where the output level is shifted by 1 or remains unchanged in each cycle in which switching load sharing control is performed. However, this cycle-based control cannot follow the situation where the L* level instruction is shifted by 2 or more in one cycle.

[0248] For controlling a serial multiplexed inverter, it is preferable to avoid two-step voltage shifting because this increases the surge voltage on a load such as a motor and thereby causes a risk of dielectric breakdown. However, this problem of dielectric breakdown can be avoided by taking measures such as using an LC filter prepared with sufficient allowance for overvoltage.

[0249] In addition, as for the triangular wave comparison PWM for a multi-stage series multiplexing inverter, when the maximum voltage level is used in a state where the fundamental wave frequency and the carrier frequency are close to each other, it is inevitable that the voltage shifts by two or more steps. at a time. If the control signal is output without such a two-step shift, the voltage rises with a delay, which causes a voltage error.

[0250] Therefore, if there is no dielectric breakdown problem, it is desirable to output a voltage offset of two or more steps without delay due to such a voltage error. In the eighth embodiment, a configuration study is conducted to achieve a two-stage shift.

[0251] FIG. 26 shows a flowchart of switching load sharing control according to the eighth embodiment. Like FIG. 6, this flowchart shows the overall control flow of switching load sharing. The L* level command is input and the control signal g is output. Operations (3) and (4) are performed in the same way as in the first to seventh embodiments. With regard to FIG. 6, the changes are that operations 8-1 and 8-2 are added after operation (3) of calculating the counter.

[0252] In step 8-1, the output level Lout approaches the command level L* by one step. In step S8-2, it is confirmed whether the output level Lout and the command level L* are equal to each other. When the output level Lout and the instruction level L* are equal to each other, the process proceeds to the operation of generating the control signal (4), otherwise, operation 2-2 and operation (3) of counter calculation are performed again. In this loop, the calculation operation of the counter is repeated until the output level Lout becomes equal to the level instruction L*.

[0253] The counter calculation operation (3) and the control signal generation operation (4) may be implemented by any of the first to seventh embodiments. The operation (4) of generating the control signal includes the operation Lout=Lout+sign(L* - Lout) at the beginning. This can be omitted since it has already been done in step S8-1. However, there is no problem even if this operation is not skipped, because the control signal generation operation (4) starts in a state where the output level Lout and the command level L* are equal to each other, and no special effect occurs even with this operation.

[0254] The foregoing describes the configuration of the eighth embodiment that can perform switching load sharing control capable of following the L* layer command in one control cycle according to FIG. 26. As in the previous embodiments, the details of the calculation method according to the eighth embodiment are not limited to FIG. 26.

[0255] As described above, according to the eighth embodiment, high-level switching load sharing among cells can be achieved by controlling to preferentially shift the level of the cell having the maximum output state duration by using an array including storage positions indicating the output state duration.

[0256] In addition, when used in combination with the sixth embodiment, overflow due to constantly incrementing counters can be prevented. Moreover, it can be implemented with fewer registers than the first, third, and fifth embodiments. In addition, the process can be simplified compared to the first to fifth embodiments.

[0257] In addition, when used in combination with the seventh option

implementation, it is possible to prevent an anomaly in the DC voltage when the number of switching operations in one cycle of the main wave is small. In addition, a two-step voltage shift can be followed without delay.

[0258] In addition, unlike Patent Documents 1-3, there are advantages in that a table is not required, a higher level of distribution is possible than triangular wave comparison based on the PS method, and there is no need to predetermine cell voltages for managing the distribution of communication load.

[0259] While the present invention has been described in detail above with reference to specific embodiments, those skilled in the art will appreciate that various modifications may be made within the scope of the present invention. Naturally, such modifications are within the scope of the claims.

Claims (94)

1. A control device for a serial multiplexed inverter, in which each of the phases includes series-connected cells, each of which contains switching elements and is configured to output level +1, zero level and level -1 as output levels by controlling the switching elements , while the control device contains: a high level control section configured to create a level command based on the command value; and switching load distribution control section configured to: storing information about the duration of the on output state of each of the cells and information about the duration of the off output state of each of the cells; for the shift circuit from on to off in the cells, turning off the control signal for one of the cells, in which the duration of the on output state is the longest of the cells; and for the shift circuit from off to on in the cells, turning on the control signal for one of the cells, in which the duration of the off output state is the longest of the cells; wherein each of the cells is determined to be on when the output level of each of the cells is +1 or -1; and each of the cells is defined as off when the output level of each of the cells is zero. 2. The device according to claim 1, in which the switching load distribution control section is configured to: executing a circuit determination operation based on a level command and an output level, wherein the circuit determination operation is to select one of circuit A, circuit B, and circuit C, circuit A must cause a shift from off to on in cells, circuit B must cause a shift from on to off in the cells, and circuit C must not cause a level shift; performing a counter calculation operation for processing information about the duration of the on output state and information about the duration of the off state of the output state based on the selection of the circuit determination operation; and performing a control signal generating operation for generating a control signal based on the output state on duration information and the output state off duration information. 3. The device according to claim 1, in which the switching load distribution control section is configured to: executing a circuit determination operation based on a level command and an output level, wherein the circuit determination operation is to select one of circuit A, circuit B, and circuit C, circuit A must cause an off-to-on transition in cells, circuit B must cause a shift from on to off in the cells, and circuit C must not cause a level shift; performing a counter calculation operation for processing information about the duration of the on output state and information about the duration of the off state of the output state based on the selection of the circuit determination operation; repeating the counter calculation operation when the level instruction and the output level differ from each other by two or more levels; and performing a control signal generating operation for generating a control signal based on the output state on duration information and the output state off duration information. 4. The device according to claim 2 or 3, in which: the operation of calculating the counter is carried out: by providing an on counter having a value as output state on duration information and an off counter having a value as output state off duration information for each of the cells; for circuit A, by setting to zero the value of the off counter of one of the cells whose off counter value is the largest of all cells, setting to 1 the value of the on counter of one of the cells whose off counter value is the largest of all cells, incrementing the counter turning on each of the cells whose on counter has a positive value, and incrementing the value of the off counter of each of the cells whose off counter has a positive value; for circuit B, by setting to zero the value of the on counter of one of the cells whose on counter is the largest of all cells, setting to 1 the value of the off counter of one of the cells whose on counter value is the largest of the cells, incrementing the value of the on counter of each of the cells whose on counter has a positive value, and increasing the value of the off counter of each of the cells whose off counter has a positive value; and for circuit C, by increasing the value of the on counter of each of the cells whose on counter is positive, and increasing the value of the off counter of each of the cells whose off counter is positive; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose ON counter value is positive, and generating a control signal to turn off each of the cells whose ON counter value is zero. 5. The device according to claim 2 or 3, in which: the operation of calculating the counter is carried out: by providing a counter having a value for each of the cells, wherein the counter indicates an on output state when the counter is positive and the counter indicates an off output state when the counter is negative; for circuit A, by setting to 1 the counter value of one of the cells whose counter value is the smallest of all cells, incrementing the counter value of each of the cells whose counter is positive, and decrementing the counter value of each of the cells whose counter is negative; for schema B, by setting to -1 the counter value of one of the cells whose counter value is the largest of all cells, incrementing the counter value of each cell whose counter value is positive, and decrementing the counter value of each cell whose counter value is negative meaning; and for circuit C, by incrementing the counter value of each of the cells whose counter is positive and decrementing the counter value of each of the cells whose counter is negative; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose counter value is positive, and generating a control signal to turn off each of the cells whose counter value is negative. 6. The device according to claim 2 or 3, in which: the operation of calculating the counter is carried out: by providing an on counter having a value as output state on duration information and an off counter having a value as output state off duration information for each of the cells; for circuit A, by setting to zero the value of the off counter of one of the cells whose off counter value is the largest of all cells, setting to 1 the value of the on counter of one of the cells whose off counter value is the largest of all cells, and increasing the value an on counter of each of the cells whose on counter has a positive value; for circuit B, by setting to zero the value of the on-counter of one of the cells whose on-counter value is the largest of all cells, setting to 1 the value of the off-counter of one of the cells whose on-counter value is the largest of all cells, and increasing the value an off counter of each of the cells whose off counter has a positive value; and for scheme C, without performing operations; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose ON counter value is positive, and generating a control signal to turn off each of the cells whose ON counter value is zero. 7. The device according to claim 2 or 3, in which: the operation of calculating the counter is carried out: by providing a counter having a value for each of the cells, wherein the counter indicates an on output state when the counter is positive and the counter indicates an off output state when the counter is negative; for circuit A, by setting to 1 the counter value of one of the cells whose counter value is the smallest of all cells, and incrementing the counter value of each of the cells whose counter is positive; for circuit B, by setting to -1 the counter value of one of the cells whose counter value is the largest of all cells, and decrementing the counter value of each of the cells whose counter value is negative; and for scheme C, without performing operations; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose counter value is positive, and generating a control signal to turn off each of the cells whose counter value is negative. 8. The device according to claim 2 or 3, in which: each of the cells has a cell number; the operation of calculating the counter is carried out: by providing an on counter as information on the duration of the on output state and an off counter as information on the duration of the off state of the output state, wherein the on counter is an array in which the cell number of each of the cells that are in the on state is arranged in descending order of duration the on output state, and the off counter is an array in which the cell number of each of the cells that are in the off state is arranged in descending order of the duration of the off state; for circuit A, by moving one of the cell numbers located in the off counter, corresponding to one of the cells whose off duration of the output state is the longest of the cells, to a position after the last of the cell numbers in the on counter, and shifting one column of the remaining numbers of cells located in the off counter, in the direction of increasing the duration of the off output state; for circuit B, by moving one of the cell numbers located in the on counter, corresponding to one of the cells whose on duration of the output state is the longest of the cells, to a position after the last of the cell numbers in the off counter, and shifting one column of the remaining numbers of cells located in the on counter, in the direction of increasing the duration of the on output state; and for scheme C, without performing operations; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose number is located in the on counter, and generating a control signal to turn off each of the cells whose number is not located in the on counter. 9. The device according to claim 2 or 3, in which: each of the cells has a cell number; the operation of calculating the counter is carried out: by providing a counter as output on duration information and output off duration information, wherein the counter is an array having columns equal to the number of cells, and including an off state area and an on state area, wherein the cell number of each of the cells that are in the off state is located in the off state area in descending order of the duration of the off output state from the first of the columns, and the cell number of each of the cells that are in the on state is located in the on state area in descending order of the duration of the on output state from one of the columns following the last column of the off state area; for circuit A, by moving one of the cell numbers located in the off-state area corresponding to one of the cells whose off-state duration is the longest of the cells, to the closing position in the on-state area, shifting by one column of the remaining cell numbers in a direction in which the duration of the output state is increased, and shifting the boundary between the off state region and the on state region in the direction of decreasing the off state region by one and increasing the on state region by one; for circuit B, by shifting the boundary between the off state region and the on state region in the direction of increasing the off state region by one and decreasing the on state region by one; and for scheme C, without performing operations; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose number is located in the on state region, and generating a control signal to turn off each of the cells whose number is not located in the on state region. 10. The device according to claim 2 or 3, in which: each of the cells has a cell number; the operation of calculating the counter is carried out: by providing a counter as output on duration information and output off duration information, wherein the counter is an array having columns equal to the number of cells, and including an on state area and an off state area, wherein the cell number of each of the cells that are in the on state is located in the on state area in descending order of the duration of the on output state from the first of the columns, and the cell number of each of the cells that are in the off state is located in the off state area in descending order of the duration of the off output state from one of the columns following the last column of the enabled state area; for circuit A, by shifting the boundary between the off state region and the on state region in the direction of increasing the on state region by one and decreasing the off state region by one; for circuit B, by moving one of the cell numbers located in the on state region, corresponding to one of the cells whose output state on duration is the longest of the cells, to the closing position in the off state region, shifting by one column of the remaining cell numbers in a direction in which the duration of the output state increases, and shifting the boundary between the off state region and the on state region in the direction of decreasing the on state region by one and increasing the off state region by one; and for scheme C, without performing operations; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose number is located in the on state region, and generating a control signal to turn off each of the cells whose number is not located in the on state region. 11. The device according to claim 2 or 3, in which: each of the cells has a cell number; the operation of calculating the counter is carried out: by providing a counter as output on duration information and output off duration information, wherein the counter is an array having columns equal to the number of cells, and including an off state area and an on state area, wherein the cell number of each of the cells that are in the off state is located in the off state area in descending order of the duration of the off output state from the first of the columns, and the cell number of each of the cells that are in the on state is located in the on state area in descending order of the duration of the on output state from one of the columns following the last column of the off state area; for scheme A, when the priority change switch (P) is set to zero, by moving one of the cell numbers located in the OFF state corresponding to one of the cells whose output OFF state duration is the longest of the cells, to the closing position in the ON state region, when the priority change switch (P) is set to 1, by moving one of the cell numbers located in the OFF state corresponding to one of the cells whose output OFF state duration is the second longest of the cells to the close position in the ON state region, and by shifting the remaining cell numbers in a direction in which the duration of the output state is increased, and shifting the boundary between the off state region and the on state region in the direction of decreasing the off state region by one and increasing the on state region by one; for circuit B, by shifting the boundary between the off state region and the on state region in the direction of increasing the off state region by one and decreasing the on state region by one; and for scheme C, without performing operations; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose number is located in the on state region, and generating a control signal to turn off each of the cells whose number is not located in the on state region. 12. The device according to claim 2 or 3, in which: each of the cells has a cell number; the operation of calculating the counter is carried out: by providing a counter as output on duration information and output off duration information, wherein the counter is an array having columns equal to the number of cells, and including an on state area and an off state area, wherein the cell number of each of the cells that are in the on state is located in the on state area in descending order of the duration of the on output state from the first of the columns, and the cell number of each of the cells that are in the off state is located in the off state area in descending order of the duration of the off output state from one of the columns following the last column of the enabled state area; for circuit A, by shifting the boundary between the off state region and the on state region in the direction of increasing the on state region by one and decreasing the off state region by one; for scheme B, when the priority change switch (P) is set to zero, by moving one of the cell numbers located in the on state region corresponding to one of the cells whose output state on duration is the longest of the cells, to the closing position in the off state region, when the priority change switch (P) is set to 1, by moving one of the cell numbers located in the on state region corresponding to one of the cells whose output state on duration is the second longest of the cells to the closing position in the off state region, and by shifting one column of the remaining cell numbers in the direction of increasing the duration of the output state and shifting the boundary between the off state region and the on state region in the direction of decreasing the on state region by one and increasing the off state by one; and for scheme C, without performing operations; and a control signal generating operation is performed by generating a control signal to turn on each of the cells whose number is located in the on state region, and generating a control signal to turn off each of the cells whose number is not located in the on state region. 13. The control device according to any one of paragraphs. 1-8, wherein the switching load sharing control section is configured to, under predetermined conditions, turning off the control signal for one of the cells, whose duration of the on output state is not the longest of the cells, for the circuit that causes the transition from on to off in the cells, turning on a control signal for one of the cells whose off-duration of the output state is not the longest of the cells, for a circuit that causes an off-to-on transition in the cells.

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