RU2755017C1 - Voltage-to-frequency converter and method for calibration thereof - Google Patents

Abstract

FIELD: microelectronics.

SUBSTANCE: technical result is achieved by means of an apparatus calibrating the main sources of errors: static zero shift of the integrator amplifier, dynamic zero shift of the integrator associated with the asymmetry of charge release by the chopper keys, inaccurate equality of the absolute values of the positive and negative reference voltages, as well as the mismatch of the return resistors, causing the skewing of the conversion coefficients for positive and negative input voltage, wherein the VFC comprises: an integrator amplifier with static and dynamic calibration inputs, a base inverter amplifier with a static calibration input, 3 calibration DACs, and a logic block controlling the process of calibration.

EFFECT: increase in the precision of the voltage-to-frequency converter (VFC) due to the calibration of second-order errors of the VFC.

6 cl, 6 dwg, 1 tbl

Description

The invention relates to microelectronics and can be used in signal processing systems and converting analog information into digital.

Known circuits of voltage-to-frequency converters (VFC) based on voltage integrators. So the circuit according to the RF patent [1] contains an integrator, a switch, a comparator, a reference voltage source and a return pulse shaper. The advantage of this scheme is the uniformity of the output pulses, and the disadvantage is the unipolarity and the accuracy of the conversion, limited by the error of the components.

Closest to the claimed is PNCh 1316PP1U [2]. Its structural diagram is shown in Fig. 1. VFC contains an integrator 1 based on a chopper of a stabilized operational amplifier 2 with a grounded non-inverting input, an integration capacitor 3 and an input resistor 4, two return resistors 5 and 6 connected to the sources of positive 7 and negative 8 of the reference voltage, two return keys 9 and 10 , two comparators 11 and 12. The negative reference voltage REFB is formed from the positive reference voltage REFT using the inverting amplifier 13. Logic unit 14, based on the signals of the comparators, forms the output signals FT (15) and FB (16) and control signals for the return keys 17, as well as chopper clock signal 18. This structure provides an important advantage of the VFO - its bipolar transfer characteristic.

PNCh 1316PP1U works as follows. The input voltage is fed to the input of the integrator 1. At a constant input voltage, a linearly varying voltage is formed at the output of the integrator: increasing with a negative input voltage and decreasing with a positive one. When the output voltage of the integrator reaches the level of a positive or negative reference voltage, the corresponding comparator 11 or 12 switches and starts the formation in the logic block 14 of one of the two return pulses of the exact duration, which, by controlling the corresponding return key 9 or 10, supplies the current from the corresponding source to the summation point reference voltage. Thus, the output voltage of the integrator returns to the region between the positive and negative reference voltage and the integration continues. Process frequency integration - return is proportional to the input voltage. The duration of the pulses at the output of the comparators also depends on the input voltage, the logic unit 14 generates pulses of constant duration and synchronized with the clock signal: at the FT output (15) with a positive input voltage and at the FB (16) output with a negative one.

The pulse frequency is determined by the formula:

• F _out - output frequency

• V _in - input voltage

• V _ref - reference voltage

• R _rev - resistance of the return resistor

• R _in - input resistor resistance

• T _rev - return pulse duration

It is important that the output frequency is determined by the ratio of voltages and resistances, as well as the duration of the return pulse. The output frequency is independent of the capacitance of the integration capacitor and the offset of the comparator. Modern circuitry solutions allow for accurate reference voltages, accurate resistor ratios, and accurate time intervals.

FIG. 2 shows the timing diagram of the VFC operation. At the beginning of the diagram, in the region O, the input voltage Vin = 0B, the integrator output is in its initial state and does not change, there are no pulses at the FT, FB outputs. In region 1, the input voltage is Vin = + 0.2V, and there is a decreasing voltage at the integrator output. When the comparator threshold is reached, pulses of the integrator return to the zone between the threshold levels and pulses at the FT output are formed. In area 2, the input voltage is Vin = -2.0V, at the output of the integrator, the voltage rises with a higher steepness. Now pulses with a higher frequency are generated at the FB output. In region 3, the input voltage is Vin = + 3.2V, and the voltage at the integrator output decreases with an even greater steepness. Pulses with an even higher frequency at the FT output.

The main source of errors of the considered PNF is the zero offset of the integrator's operational amplifier. Chopper stabilization of the amplifier allows a first approximation to solve this problem. The formation of a negative reference voltage by inverting a positive one also allows, in the first approximation, to avoid the mismatch of two different reference sources. Therefore, another important advantage of the VFC is its high conversion accuracy.

At the same time, the PNC has a number of disadvantages. A number of second-order errors limit the possibility of further improving the conversion accuracy. These include:

At high input voltages (high output frequencies), the chopper stabilization modulates the output frequency, so we can speak of high accuracy only in the sense of averaging over a large number of chopper periods.

Another source of error is the inaccurate equality of the absolute values of the positive and negative reference voltages. The negative voltage is generated from the positive by the inverting amplifier. Its zero offset and feedback resistor mismatch cause the reference voltages to skew. As a consequence, the VFC has different conversion factors for the positive and negative input voltages, which are specified independently of each other. Return resistor mismatch contributes further to this misalignment. In other words, the bipolar transfer characteristic, being highly linear, has a slight kink at zero.

Another source of errors is the asymmetry of charge surges by the chopper keys, which generates a dynamic error.

Known technical solution for the patent of the Russian Federation [3] "CMOS amplifier with chopper stabilization and method of calibration." FIG. 3 shows its diagram. The amplifier has one input and two output cross switches, performing simultaneous switching of differential inputs and outputs of the first stage. The Isp / Isn pair of differential current inputs inject a calibrating current into the first stage, which dominates the amplifier's zero offset, regardless of the chopper state. A pair of differential current inputs Idp / Idn introduce a calibration current into the second stage circuit after the output cross switches. The first pair is used to calibrate the classic static amplifier zero offset with the chopper stopped. The second pair is used for dynamic calibration when the chopper is running and actually calibrates the dynamic error of asymmetric charge ejection by the chopper keys. Moreover, the second dynamic calibration is performed after applying the static one, when the static displacement is already close to zero. Differential current DACs, in particular, can be a source of the calibrating influence.

An object of the present invention is to improve the accuracy of the VLF by calibrating the second order VLF errors.

This goal is achieved by the fact that in a VFC containing an integrator consisting of a chopper - a stabilized amplifier with a grounded non-inverting input, the output of which is the output of the integrator, a capacitor connected between the inverting input and the output of the amplifier, an input resistor connected between the inverting input of the amplifier and the input of the VFO , two return resistors of the integrator, connected by the first leads to the sources of positive and negative reference voltages, and the second leads through two return switches of the integrator to the inverting input of the amplifier, two comparators comparing the output voltage of the integrator with the positive and negative reference voltage, a logic block connected to outputs of the comparators and generating signals of the positive and negative frequency outputs of the VFO, control signals of the return keys and the clock signal of the chopper - stabilization, the amplifier has inputs for static calibration of the zero offset with the chopper off - stabilization, etc. dynamic zero offset calibration with chopper stabilization turned on, the integrator contains a switch that connects the inverting input of the amplifier with an input resistor or non-inverting input or is in an open state and a zero switch connecting the inverting input with the output of the amplifier, the PNC contains two digital-to-analog converters DAC1 and DAC2 , the outputs of which are connected to the inputs of the respectively static and dynamic calibration of the zero offset of the amplifier, the logic block contains a calibration automaton and generates control signals for the switch, zeroing key, DAC1 and DAC2.

In a particular case, the set goal is achieved by the fact that the PNC contains a converter of a positive reference voltage to a negative one based on an inverting amplifier having a zero offset calibration input, DAC3, connected by the input to the logic unit, and by the output to the zero offset calibration input of the negative reference voltage source, and the logic block generates control signals for DAC3.

In a particular case, the set goal is achieved by the fact that the inputs of the calibration of the zero offset of the amplifiers and the outputs of the DAC are current.

In a particular case, the goal is achieved by the fact that the PNC contains resistive dividers of positive and negative reference voltages and switches that connect the reference inputs of the comparators to the nominal or reduced resistive dividers of the positive and negative reference voltages.

This goal is also achieved by using the VFC calibration method, in which they sequentially calibrate: the static zero offset of the VFC when the amplifier inputs are closed by the switch and the chopper is turned off - stabilization by loading into DAC1 a code that minimizes the VFC zero offset, the dynamic zero offset of the VFC when the amplifier inputs are closed and the chopper is turned on. - stabilization by loading into DAC2 a code that minimizes the PNC zero offset, a negative reference voltage with an open switch and two turned on return keys by loading into DAC3 a code that minimizes the PNC zero offset, while the DAC codes that minimize the PNC zero offset are calculated by sequential approximation, determining the direction changing the codes at each iteration according to the signals of the comparators.

In a particular case, the set goal is achieved by using the VFC calibration method, in which the following are calibrated in series: the static zero offset of the VFC when the amplifier inputs are closed by the switch and the chopper is turned off; a switch with an input resistor, an external grounding of the PNC input and an enabled chopper - stabilization by loading a code into DAC2 that minimizes the PNC zero offset, negative reference voltage with an open switch and two enabled return keys by loading into DAC3 a code that minimizes the PNC zero offset, while calculating the DAC codes , minimizing the offset of the PNC zero, are carried out by successive approximation, determining the direction of changing the codes at each iteration according to the signals of the comparators.

In a particular case, the goal is achieved by using the VFC calibration method, in which the reference inputs of the comparators are connected to the reference sources through resistive dividers that reduce the reference voltages of the comparators.

The essence of the invention is illustrated by drawings:

FIG. 1 - block diagram of PNCh 1316PP1U;

FIG. 2 - timing diagrams of PNCh 1316PP1U operation;

FIG. 3 is a block diagram of an amplifier with chopper stabilization and zero offset calibration inputs;

FIG. 4 is a block diagram of the inventive PNCh;

FIG. 5 is a block diagram of the inventive PNC with resistive dividers that reduce the reference voltages of the comparators;

FIG. 6 - timing diagrams of calibration.

The declared PNCh contains the following additional blocks in comparison with the prototype. In accordance with clause 1 of the Formula (Fig. 4), differential current signals of static and dynamic calibration, respectively, are supplied to the inputs of static 19 and dynamic 20 zero offset calibration of the CMOS amplifier with chopper stabilization known from [3]. Switch 21 connects the inverting input of the amplifier to an input resistor or non-inverting input, or is in an open state. The integrator zeroing key 22 on the signal from the logic unit 14 zeroes the integrator. DAC1 (23) for static offset calibration and DAC2 (24) for dynamic offset calibration generate corresponding differential calibration currents. In accordance with clause 2 of the Formula, DAC3 (25) forms the differential current for calibrating the zero offset of the negative reference voltage source. To speed up the calibration process and increase the accuracy, it is advisable to reduce the threshold levels at the reference inputs of the comparators 11, 12. For this purpose, and in accordance with clause 4 of the Formula, resistive dividers and switches 26, 27 of the comparator threshold levels are introduced into the PNC (Fig. 5).

The claimed PNCh works as follows. In the initial state before calibration, the switch 21 connects the inverting input of the amplifier with the input resistor, and DAC1, DAC2, DAC3 generate zero calibrating currents. In this state, the operation of the claimed PNC completely coincides with the operation of the PNC 1316PP1U described earlier.

Calibration is performed in 3 steps in accordance with clause 5 of the Formula. The calibration process is illustrated by the timing diagram in FIG. 6. Designation of diagram signals:

• ct, cb - outputs of comparators 11 and 12, respectively

• sar - internal successive approximation register. The register contains 1 in the bit of the code processed at the current iteration of the successive approximation. At the beginning of each calibration step, the register contains a hexadecimal 200 (one in the most significant digit). At each next iteration, the unit is shifted towards the least significant bits

• dac_s, dac_d, dac_r - codes of DAC1, DAC2, DAC3, respectively. At the beginning of each step, the corresponding DAC contains a hexadecimal 200, (the middle of the DAC scale). At each subsequent iteration, the DAC code decreases when switching the comparator 11 or increases when switching the comparator 12. At the first step (1 in Fig. 6), the static zero offset of the VFC is calibrated. To do this, the switch 21 closes the inputs of the amplifier and stops the clock signal of the chopper 18. The calibration is carried out by the method of successive approximation with the number of iterations equal to the digit capacity of the DAC - in a particular implementation - 10.

Before the first iteration, a zero calibration signal is set at the DAC1 output, corresponding to the middle of the bipolar calibration range. At the beginning of each iteration, the integrator is zeroed with the zeroing switch 22 for a time sufficient to discharge the integration capacitor with acceptable accuracy. Once zeroed, the integrator begins to integrate the static zero offset of the amplifier. Due to the small bias, the output of the integrator will have a slowly and linearly varying voltage. When the output voltage of the integrator reaches one of the two, depending on the polarity of the bias, the reference levels, the corresponding comparator switches, and the transition to the next iteration occurs. In this iteration, DAC1 changes the calibration signal in a direction that decreases the absolute offset value, depending on which comparator is switched. At each subsequent iteration, the step of changing the calibration signal is halved.

At any iteration, a condition may arise where the current calibration signal compensates for the offset very accurately, the integrator output voltage changes extremely slowly, and the time it takes to reach the reference level is unacceptably long. To avoid such conditions, a timeout is introduced so that if for the next iteration during the timeout none of the comparators has switched, the successive approximation procedure is interrupted. This means that the calibration has reached acceptable accuracy. Increasing the timeout time increases the accuracy of the calibration, but at the cost of time. Regardless of whether the calibration was completed at the last iteration or was interrupted by a timeout, at the end of the calibration the calibration signal at the output of DAC1 compensates for the static offset and remains in this state for the duration of subsequent calibration steps and further normal operation.

Static Offset Calibration reduces the output frequency modulation by the chopper frequency when the input signal is large and the output frequency is high.

At the second step (2 in Fig. 6), the dynamic zero offset of the VFC caused by the asymmetry of the charge ejection by the chopper keys is calibrated. The amplifier inputs are still closed by switch 21, but the chopper is activated, restoring the chopper clock signal 18. The successive approximation procedure is similar to the previous step, but with respect to DAC2.

FIG. 6, the second step is interrupted ahead of schedule by timeout at the 8th iteration. In the diagram, the interval from 1900 to 3600 ns is collapsed and marked with a vertical line to make room for important diagram details. This interval refers to a long iteration of 8 that has exceeded the timeout. Code 244 for this iteration is the final code for DAC2.

At the third step (3 in Fig. 6), a negative reference voltage is calibrated, the source of errors of which is the offset of the zero of the inverting amplifier 13 and the mismatch of its feedback resistors. For this, the switch 21 is transferred to the open state, both return keys 9 and 10 are closed, and the chopper is left in the active state. In this configuration, the integrator 1 effectively integrates the imbalance of the currents flowing through the return resistors 5 and 6, and which must be reduced to zero. Meeting this requirement means that the mismatch of return resistors 5 and 6 is also calibrated. The successive approximation procedure is similar to the previous steps, but with regard to DAC3. Resources for this step of the calibration are introduced in clause 2 of the Formula.

There are effective circuitry solutions for influencing the zero offset of the amplifier using calibrating currents [3]. Therefore, the calibration DACs have current outputs in accordance with clause 3 of the Formula. However, this does not exclude other bias calibration circuitry.

To speed up and improve the accuracy of the calibration, it is advisable to reduce the absolute value of the threshold levels of the comparators during the calibration in accordance with p. 4 and 7 Formulas. In a specific implementation, the threshold levels during normal operation are ± 1250 mV, and when calibrated, ± 10 mV. It is important that the exact magnitude and symmetry of these levels are not of fundamental importance.

The above calibration method assumes that the operating conditions of the VFC input are different during normal operation and during calibration. So during calibration, the inputs of the integrator amplifier are closed by a switch and isolated from the VFC input. Parasitic influences (leakage, noise, voltage drop) from the VFC input side are not involved in the calibration process and are not eliminated. Calibration accuracy, including input spurious effects, can be improved by externally grounding the VFC input. The most effective way to do this is with dynamic calibration, in accordance with clause 6 of the Formula. This requires, however, an additional switch and a corresponding switching signal outside the VFC.

This technical solution made it possible to significantly improve the main parameters of the PNC in comparison with the prototype 1316PP1U:

The lack of calibration of the negative support in the prototype does not allow obtaining high values of the parameters in the bipolar range; therefore, such parameters are not given in the prototype specification. The table contains only reference values of the prototype parameters in the bipolar range. For the proposed PNC, it becomes possible to specify high guaranteed values of parameters in the bipolar range.

Literature

1.Russian patent 2015132723.

2. PNCh 1316PP1U specification https://ic.rnilandr.ru/upload/iblock/5e5/5e54e76dd92dbb5d706d114ac696b52e.pdf

3.Russian patent 2019137419.

Claims (6)

1. A voltage-to-frequency converter (VFC) containing an integrator consisting of a chopper-stabilized amplifier with a grounded non-inverting input, the output of which is the output of the integrator, a capacitor connected between the inverting input and the output of the amplifier, an input resistor connected between the inverting input of the amplifier and the input VFC, two integrator return resistors, connected by the first leads to the sources of positive and negative reference voltages, and the second leads through two integrator return keys to the inverting input of the amplifier, two comparators comparing the integrator output voltage with positive and negative reference voltages, a logic block connected to the outputs of the comparators and generating signals of the positive and negative frequency outputs of the PNC, control signals for the return keys and the clock signal of the chopper stabilization, characterized in that the amplifier has inputs for static zero offset calibration with the chopper off. stabilization and dynamic calibration of zero offset with the included chopper stabilization, the integrator contains a switch that connects the inverting input of the amplifier with an input resistor or non-inverting input or is in an open state, and a zeroing switch connecting the inverting input with the output of the amplifier, the PNC contains two digital-to-analog converters DAC1 and DAC2, the outputs of which are connected to the inputs of the static and dynamic calibration of the amplifier zero offset, respectively, the logic block contains a calibration automaton and generates control signals for the switch, zeroing key, DAC1 and DAC2. 2. PNC according to claim 1, characterized in that the PNC contains a positive-to-negative reference voltage converter based on an inverting amplifier having a zero offset calibration input, DAC3, connected to the input to the logic unit, and the output to the zero offset calibration input of the negative reference source voltage, and the logic block generates control signals for DAC3. 3. PNCh according to PP. 1, 2, characterized in that the inputs of the calibration of the zero offset of the amplifiers and the outputs of the DAC are current. 4. PNCh according to PP. 1-3, characterized in that the PNC contains resistive dividers of positive and negative reference voltages and switches that connect the reference inputs of the comparators to the rated or reduced resistive dividers of the positive and negative reference voltages. 5. Method of PNC calibration according to PP. 1-4, characterized in that they are sequentially calibrated: the static zero offset of the PNC when the amplifier inputs are closed by the switch and the chopper stabilization is turned off by loading into DAC1 a code that minimizes the PNF zero offset, the dynamic zero offset of the PNC when the amplifier inputs are closed by the switch and the chopper stabilization is enabled by loading in DAC2 of the code that minimizes the PNC zero offset, a negative reference voltage with an open switch and two turned on return keys by loading into DAC3 a code that minimizes the PNC zero offset, while the DAC codes that minimize the PNC zero offset are calculated by successive approximation, determining the direction of changing the codes to each iteration over the signals of the comparators. 6. Method of PNC calibration according to PP. 1-5, characterized in that they are sequentially calibrated: the static zero offset of the PNC when the amplifier inputs are closed by the switch and the chopper stabilization is turned off by loading into the DAC1 a code that minimizes the PNF zero offset, the dynamic zero offset of the PNC when the inverting input of the amplifier is connected by the switch to the input resistor, external grounding of the PNC input and the included chopper stabilization by loading into DAC2 a code that minimizes the PNC zero offset, negative reference voltage with an open switch and two enabled return keys by loading into DAC3 a code that minimizes the PNC zero offset, while calculating the DAC codes that minimize the PNC zero offset , is carried out by successive approximation, determining the direction of changing the codes at each iteration according to the signals of the comparators.

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