RU2739861C1 - Manufacturing method of transistor with independent contact to substrate - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to the field of microelectronics and can be used in manufacture of transistors on the insulating silicon plate (ISP) with a wide field of application. Method of making a transistor with independent contact to substrate includes formation on the silicon plate on the insulator areas of drain, source, gate, consisting of two layers of polysilicon, wherein according to the invention independent contact to the substrate is performed by creating a heavily doped silicon region outside the active region of the transistor, which is connected to the transistor by means of an additional doped silicon region.

EFFECT: invention provides wider field of use of a transistor with two layers of polysilicon, high reliability of the design, exclusion of parasitic capacitance of the gate of the transistor on the ISP with independent contact to the footstep.

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Description

The invention relates to the field of microelectronics and can be used in the manufacture of transistors on a silicon wafer insulator (SOI) with a wide range of applications.

Patent RU 2477904 C1 H01L 29/78 03/20/13 describes a method of manufacturing a SOI transistor with a contact to the substrate.

The structure of this transistor includes areas of shallow-gap insulation, a pocket area of a retrograde profile of the distribution of type 2 impurities with a depth throughout the entire thickness of the silicon layer on an insulator, a region of a polysilicon gate doped with ions of an impurity of type 2, areas lightly doped with type I impurities (lightly doped area), a spacer, a drain area formed on one side of the gate by highly doped type 1 impurity ions with a depth throughout the entire thickness of the silicon layer on the insulator, the source region formed on the other side of the gate by highly doped type 1 impurity ions with a depth of a fraction of the thickness of the silicon layer on the insulator and the area of contact to the pocket formed by an impurity of the type 2, electrically connected to the source by means of silicide, the region of the highly doped contact to the pocket is located under the source region and has a width equal to the width of the source, while the electrical connection by the silicide of the source and contact regions to the pocket is carried out in a groove formed in the region These are the source with a depth equal to or greater than the depth of the source region and a width equal to the width of the source. In such a transistor, the contact is dependent, since it is aligned with the source. A transistor of this design cannot be used in pass-through keys.

A known method of creating a contact to the substrate, described in patents US No. 2005173764 A1, class. H01L 21/425 publ. 11.08.2005 and US No. 6353245 B1, class. H01L 27/01, publ. 05.03.2002.

The contact to the substrate is formed due to the additional region of the silicon island doped with the same impurity as the pocket, which has a diffusion contact to the pocket and an exit to the planar surface of the source-drain of the MOS transistor. The contact area is connected to the source of the transistor by a silicide formed on the planar surface of the source and contact. The disadvantage of this design is that this contact is also dependent and a transistor with this type of contact to the substrate is also impossible to use in pass-through switches.

US Pat. No. 6,316,808 B1 dated 11/13/2001 describes a method of creating a SOI transistor with polysilicon t-shaped on the active region, where the source, drain and contact to the substrate are separated from each other by polysilicon. The polysilicon layer between the source and drain is the gate of the transistor. In this case, the contact is independent. The disadvantage of this design is the presence of a large parasitic gate capacitance in relation to the active one.

In US patent No. 6960810 B2 from 01.11.2005 describes a method of manufacturing a transistor with two layers of polysilicon, in which the contact to the substrate is aligned with the source, selected for the prototype. Such a transistor has less parasitic resistance. The disadvantage is that the method does not allow you to create an independent contact to the substrate, a transistor manufactured by this method cannot be used in pass-through switches.

The objective of the invention is to create a SOI transistor with an independent contact to the substrate, which can be used in through-switches and series circuits.

The technical result of the proposed method is to expand the scope of the transistor with two layers of polysilicon, increase the reliability of the design, eliminate the parasitic capacitance of the gate of the SOI transistor with an independent contact to the substrate.

The technical result is achieved by the fact that in the manufacture of a transistor with an independent contact to the substrate, including the formation of drain, source, and gate regions on the insulator on the silicon wafer, consisting of two layers of polysilicon, independent contact to the substrate is performed by creating a heavily doped silicon region outside the active region transistor, which is connected to the transistor through an additional doped silicon region.

The invention is illustrated by the following figures.

Figure 1 shows a fragment of the topology of a part of a transistor with a gate consisting of two polysilicon layers and an independent contact to the substrate, where: 1 - areas of heavily doped silicon (source, drain of the transistor); 2 - a gate consisting of two layers of polysilicon; 3 - heavily doped silicon region (independent contact to the substrate).

Figures 2-7, 9 show the main stages of the implementation of the method for manufacturing a transistor with an independent contact to the substrate in section A, where:

1 - areas of heavily doped silicon (source, drain of the transistor);

3 - heavily doped silicon region (independent contact to the substrate);

4 - silicon layer (bottom layer of the plate);

5 - a layer of buried silicon oxide;

6 - region of undoped silicon;

7 - region of lightly doped silicon, including the region of doped silicon (pocket), contact to the substrate and an additional region of doped silicon connecting them;

8 - a layer of a gate dielectric (silicon oxide);

9 - the first layer of polysilicon;

10 - layer of silicon nitride;

11 - heavily doped silicon region (protection area);

12 - a layer of silicon oxide;

13 - the second layer of polysilicon;

16 - additional area of doped silicon. Figure 8 shows the structure of an n-channel transistor in section B, where:

14 - low-doped silicon region (LDD region);

15 - wall silicon oxide (spacers).

The manufacturing process of a transistor with independent contacts to the substrate is implemented as follows.

On the SOI plate, consisting of the silicon lower layer 4 of the silicon-on-insulator (SOI) wafer, buried silicon oxide 5, undoped silicon 6 by the method of ion implantation, a region of lightly doped silicon 7 is formed. Then, a layer of the gate dielectric 8 is formed by thermal oxidation. Further by deposition followed by photolithography , implantation of an impurity and etching through a mask form the first layer of polysilicon 9 and silicon nitride 10 (Fig. 2).

Then protected areas 11 are created by ion implantation (Fig. 3).

Further, after the deposition of a layer of silicon oxide 12 and subsequent reactive etching on the mask of silicon oxide and silicon, a silicon region (silicon island) is formed, including a region of lightly doped silicon 7 and a protection region 11 (Fig. 4).

After the formation of a silicon island, insulation is created by low-temperature deposition of silicon oxide 12, etching along the mask of the inverse active and the contact area to the substrate with further chemical-mechanical polishing followed by removal of silicon nitride (Fig. 5).

Next, the second layer of polysilicon 13 is deposited (Fig. 6) and the gate 2 is further formed by etching over a mask (Fig. 7).

Then, LDD regions 14 are formed by the method of ion implantation of impurities from a photocopy (PC) of N +, P + and spacers 15 by the method of silicon oxide deposition and the process of maskless etching (Fig. 7).

Then, the heavily doped regions of the source, drain 1 (Fig. 8) and contact to the substrate 3 are formed by ion implantation over a mask (Fig. 9). Contact 3 to the substrate is independent and is connected to the active region of the transistor through an additional region of doped silicon 16 (Fig. 9).

The process is then completed in the standard way of forming a self-aligned silicide, insulation, contacts and metals.

Thus, it is possible to obtain a transistor with an independent contact to the substrate, which significantly expands their field of application (through switches, serial connection).

Claims (1)

A method of manufacturing a transistor with independent contacts to a substrate, including the formation on a silicon wafer on an insulator of drain, source and gate regions, consisting of two polysilicon layers, characterized in that an independent contact to the substrate is performed by creating highly doped silicon regions outside the active region of the transistor, which is connected to the transistor through an additional region of doped silicon.

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