RU2729509C1 - Device for unpacking data - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to computer engineering and is intended for use in information processing systems, as well as in compression and decompression units without losses in systems for rational use of storage and transmission devices, processing of physical experiment data. Device comprises an input data register RD, a multiple-output priority unit FU, a group of N data switches with k digits, group of N registers by k digits with synchronous input R of setting to zero state, output buffer BQ, element NOR, N groups of k elements 2AND, register of common mask RM1, D-trigger with synchronous input R of setting to zero state, switch of KM mask, register of current mask RM2.

EFFECT: reduced bit depth of input data and ease of implementation with simultaneous increase of information capacity without loss of information due to reduction of required amount of memory for storage of sequence of groups of input data of binary symbols and corresponding symbols masks.

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Description

AREA OF TECHNOLOGY

The invention relates to the field of computer technology and is intended for use in information processing systems, and can also be applied in blocks of compression and decompression of data without loss in systems for the rational use of storage and data transmission devices, processing data of physical experiments.

PRIOR ART

There is a known method of lossless data recovery compression (RU No. 2403677 C1, IPC Н03М 7/30, declared 02/09/2009, published 11/10/2010, Bull. No. 31), which uses data compression, previously compressed. In the compressed data stream, count the number of zeros n ₀ and the number of ones n ₁ , select an algorithm for assigning non-repeating digital codes to all possible permutations with repetitions of zeros and n ₁ ones and finding the corresponding permutation, which is assigned a digital code N _c , count the total number of codes n _c , the values d ₁ = n ₀ + n ₁ -n _c and d ₂ = (n ₀ + n ₁ ) / 2 are determined, and the reverse operations are performed to restore the data stream.

Known encoding device (RU No. 153302 U1, IPC Н03М 7/30, declared on June 17, 2014, published on July 10, 2015, Bulletin No. 19) containing an input register, a discharge analyzer, a key control unit, a key block, a ROM, a multiplexer block, an output register, as well as a clock generator, a frequency divider, a counter and an output register with the following connections: the output of the input register 1-n is connected to the inputs of the bit analyzer and to the key control unit, the outputs 1-n ^{2 of the} analyzer are connected to the information inputs of the key unit, and outputs 1-n ² - with the control inputs of this block, the outputs of which 1-n ^{2 are} connected to the ROM inputs, and the outputs 1-2n of the ROM are connected to the information inputs of the multiplexer unit, the outputs of which 1-n are the outputs of the device marker; outputs 3-8 of the input register are connected to the output register, the outputs of which are the outputs of the information bits of the device; the output of the clock generator through the counter is connected to the control inputs of the multiplexer unit, and through a frequency divider - to the control inputs: through the output 1 of the input register, through the output 2 with the key control unit, and through the output 3 with the output register.

The disadvantage of these devices is their circuit complexity, which complicates their use.

Known device for packing data (RU No. 2701711 C1, IPC Н03М 7/30, declared 01/09/2019, published 09/30/2019, bull. No. 28), containing N input characters ID1, ID2, ..., IDN by k bits connected to the input data register 2, mask generator 3, containing a group of N OR elements, mask switch 4, mask register 5, multi-output priority block 6, containing w stages, data switch block 7, containing w switches 7 ₁ , 7 ₂ , ..., 7w, mask-data switch 8, output buffer 9, OR-NOT element 10, synchronous D-flip-flop 11, external input C of synchronization 12, external input R of synchronous setting to zero 13, external outputs Q of device 14, containing w symbols of k bits , as well as an internal data bus DD of N symbols by k bits, an internal N-bit bus of a mask of symbols M, a group of w internal buses of pointers of the most significant symbols U1, U2, ..., Uw (where w is the number of output symbols), an internal bus of the residual mask MS and the null character flag (zero flag) FZ ...

The disadvantage of this device is the lack of tools for recovering compressed data.

The closest device for the same purpose to the claimed invention in terms of a set of features is, taken as a prototype, a device for data decompression (RU No. 2697618 C1, IPC N03M 7/30, announced on 10/30/2018, published on 08/15/2019, bull. No. 23), containing the input data bus 1 connected to the input data register 2, a multi-output block of priority 3, which contains w groups of outputs of pointers of high-order symbols S1, S2, ..., Sw, N bits each (where w is the number of input characters), a group of N data switches 4 ₁ , 4 ₂ , ..., 4 _N , a group of N registers 5 ₁ , 5 ₂ , ..., 5 _N with a synchronous input R set to zero, output buffer 6, the outputs of which contain N output symbols Q1, Q2,… QN by k bits and which are external outputs of the device 13, OR-NOT element 7, N groups 8 ₁ , 8 ₂ , ..., 8 _N by k elements 2I, mask register 9, D-flip-flop 10 with a synchronous input R setting to zero,

and also containing an external input C of synchronization 11, an external input R of synchronous setting to zero, an internal data bus D of w symbols by k bits each, an internal MS priority bus, which is a group of second outputs of a multi-output block of priority 3, an internal N-bit first mask bus symbols M, the internal N-bit second bus of the mask of symbols QM, which is the group of outputs of the mask register 9, and the zero flag FZ,

moreover, the external input C of synchronization 11 and the external input R of synchronous zeroing 12 are connected, respectively, to the inputs of synchronization C and inputs R of synchronous zeroing of the input data register 2, N groups of registers 5, output buffer 6, mask register 9 and D- trigger 10,

moreover, the outputs of the input register 2 are the corresponding w * k bits of the internal data bus D, which are connected to the information inputs of each data switch of a group of N data switches 4 ₁ , 4 ₂ , ..., 4 _N , the control inputs of the sample of which are connected to the corresponding similar bits w groups of outputs S ₁ , S2, ..., Sw multi-output block of priority 3,

while the outputs of a group of N data switches 4 ₁ , 4 ₂ , ..., 4 _{N are} connected to the corresponding information inputs D of the same registers of a group of N registers 5 ₁ , 5 ₂ , ..., 5 _N , which outputs QB1, QB2, ..., QBN of all N registers 5 ₁ , 5 ₂ , ..., 5 _{N are} connected in groups with the corresponding first inputs of elements 2I of the same N groups 8 ₁ , 8 ₂ , ..., 8 _N , the outputs of which are connected to the corresponding groups of information inputs IQ1, IQ2, ... , IQN of the output buffer 6, and the second inputs of elements 2I of N groups 8 ₁ , 8 ₂ , ..., 8 _N are interconnected in groups and connected to the corresponding bits of the same name of the internal N-bit second bus of the QM mask,

in addition, the output of the OR-NOT element 7 is a zero flag FZ and is connected to the information D-input of the D-flip-flop 10, the output of which is connected to the CE input of the enable of the mask register 9 and is connected to the input of the CE of the enable of the output buffer 6,

moreover, the input data bus 1 contains a group of input data bits ID of w symbols by k bits and a group of input N bits of the symbol mask IM, while the second group of outputs of the input register 2 is N bits of the internal first bus of the mask of symbols M, which is connected to the inputs of the multi-output unit priority 3 and connected to the inputs of the CE of the same group of registers 5 ₁ , 5 ₂ ,…, 5 _N.

The disadvantages of this device are the hardware costs for storing the current mask for each packed group of symbols and transmitting N bits of the current mask at each clock cycle.

OBJECT OF THE INVENTION

The objective of the invention is to develop hardware for use in information processing systems, compression and decompression units without loss in systems for the rational use of storage and data transmission devices.

The technical result of the invention is to reduce the bit width of the input data and simplicity of implementation with a simultaneous increase in information capacity without loss of information by reducing the required amount of memory for storing a sequence of groups of input data of binary symbols and corresponding masks of symbols.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result in the implementation of the invention is achieved by the fact that in the device for unpacking data containing the input data bus IMD 1 connected to the input data register RD 2, the multi-output block FU of priority 3, which contains w groups of outputs of the pointers of the most significant symbols U1, U2, ..., Uw N bits each (where w is the number of input characters), a group of N switches KD data 4 ₁ , 4 ₂ , ..., 4 _N , a group of N registers 5 ₁ , 5 ₂ , ..., 5 _N with a synchronous input R setting to zero , output buffer BQ 6, the outputs of which contain N output symbols Q1, Q2, ..., QN in k bits and which are external outputs of the device 13, OR-NOT element 7, N groups 8 ₁ , 8 ₂ , ..., 8 _N by k elements 2I, register RM1 of the general mask 9, D-flip-flop 10 with a synchronous input R set to zero,

and also containing an external input C of synchronization 11, an external input R of synchronous zeroing 12, an internal data-mask bus MD of w symbols of k bits each, an internal priority bus (residual mask) MS, which is a group of second outputs of a multi-output block of priority 3 , the internal N-bit bus of the general mask of symbols QM, which is the group of outputs of the register RM1 of the general mask 9, and the zero flag (flag of zero symbols) FZ,

moreover, the external input C of synchronization 11 and the external input R of synchronous zeroing 12 are connected, respectively, to the inputs of synchronization C and inputs R of synchronous zeroing of the input register RD of data 2, N groups of registers 5 ₁ , 5 ₂ , ..., 5 _N , output buffer BQ 6, register RM1 of the general mask 9 and D-flip-flop 10,

moreover, the outputs of the input register 2 are the corresponding w * k bits of the internal data-mask bus MD, which are connected to the information inputs of each data switch KD of a group of N data switches 4 ₁ , 4 ₂ , ..., 4 _N , the control inputs of which are connected to the corresponding with the same name bits w of groups of outputs U1, U2, ..., Uw of a multi-output unit FU of priority 3,

while the outputs of a group of N switches KD data 4 ₁ , 4 ₂ , ..., 4 _{N are} connected to the corresponding information inputs D of the same-name registers of a group of N registers 5 ₁ , 5 ₂ , ..., 5 _N , whose outputs QB1, QB2, ... , QBN of all N registers 5 ₁ , 5 ₂ , ..., 5 _{N are} connected in groups with the corresponding first inputs of elements 2I of the same N groups 8 ₁ , 8 ₂ , ..., 8 _N , the outputs of which are connected with the corresponding groups of information inputs IQ1, IQ2, ..., IQN of the output buffer BQ 6, and the second inputs of elements 2I of N groups 8 ₁ , 8 ₂ , ..., 8 _N are interconnected in groups and connected to the corresponding bits of the same name of the internal N bit bus of the general mask of symbols QM,

in addition, the output of the OR-NOT element 7 is a zero FZ flag and is connected to the information D-input of the D-flip-flop 10, the output of which is connected to the CE input for enabling the operation of the register RM1 of the general mask 9 and is connected to the CE input for enabling the output buffer VO 6,

In addition, the switch KM of the mask 14 and the register RM2 of the current mask 15 are introduced, in which the synchronization input C is connected to the external input C of synchronization 11, and the input R of the synchronous setting to the zero state is connected to the external input 12 of the synchronous setting to the zero state, and also the internal N bit line of the current mask of characters M,

moreover, the internal data-mask bus MD is also connected to the information inputs of the general mask register 9 and to the first group of information inputs of the switch KM of the mask 14, in which the second group of information inputs is connected to the internal priority bus (residual mask) MS, and the third control input of the switch selection KM mask 14 is connected to the output of the D-flip-flop 10,

the group of outputs of the switch KM mask 14 is connected to the inputs of the OR-NOT element 7 and to the information inputs of the register RM2 of the current mask 15, the group of outputs of which is connected to the group of inputs of the multi-output block of priority 3 and is the internal bus of the current mask of symbols M, the bits of which are connected to CE inputs of the same name groups of registers 5 ₁ , 5 ₂ ,…, 5 _N.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a diagram of the proposed device for unpacking data. FIG. 2 shows the format of the data before packing. FIG. 3 shows the data formats at the input to the device. FIG. 4 shows the format of the output data. FIG. 5 shows a clockwise time diagram of the proposed device operation with the number of symbols before packing N = 16 in k = 4 bits, the width of the mask N = 16, the width of the input IMD data-mask bus L = 16, containing w = 4 symbols of k = 4 bits, or N = 16 mask bits.

In the device of FIG. 1-5 and the following designations are adopted in the text:

С - synchronization input,

CE - work permit entry,

BQ - output buffer,

D - information input of the trigger,

DD - data before packing (compression) - N characters by k bits,

dd - input characters, containing k bits each,

IMD is the input mask data bus with a width of L ≥ max (N, w * k), where w is the number of symbols in k bits, N bits of the mask,

ID - a set of w input characters k-bit each,

IM - input mask of N bit width,

MD - internal data-mask bus - w symbols, k-bit each or N mask bits,

FU - multi-output priority block containing w stages,

FZ - flag of zero characters (flag of zero),

IQ1, IQ2, ..., IQN - N groups of input symbols of the output buffer 6,

k - character length,

KD - data switch,

KM - mask switch,

L is the bit width of the input data, where L ≥ max (N, w * k),

M - internal N-bit bus of the current character mask,

MS - internal bus priority (residual mask),

N - the number of output characters by k bits

TCE - trigger output,

Q1, Q2, ..., ON - N output symbols by k bits after unpacking (restoring),

QB1, QB2, ..., QBN - N characters from the outputs of the register group 5 ₁ , 5 ₂ , ..., 5 _N ,

QM - internal N-bit bus of the common character mask,

R - input of synchronous setting to zero state,

RD - input data register,

RG - register,

RM1 - general mask register,

RM2 - register of the current mask,

S1, S2, ..., Sw - a group of w internal buses of the character mask in the priority block,

U1, U2, ..., Uw - w groups of N-bit pointers of the most significant unit in the code "1 of N",

V is the number of non-zero characters in the input ID,

w is the number of characters in the input IMD data,

Z - the maximum number of groups in the input sequence of non-zero symbols, and Z =] N / w [(greater integer) when the number of non-zero symbols V is greater than (N-w + 1),

1 - external input bus of data-mask IMD,

2 - input data register RD,

3 - multi-output priority block FU,

4 ₁ , 4 ₂ ,…, 4 _N - a group of N data switches, k-bit each,

5 ₁ , 5 ₂ , ..., 5 _N - a group of N registers of k bits each with a synchronous input R setting to zero,

6 - output buffer BQ,

7 - element OR NOT,

8 ₁ , 8 ₂ , ..., 8 _N - N groups of k elements 2I,

9 - register of the general mask RM1,

10 - D-flip-flop with synchronous input R setting to zero state,

11 - external input С synchronization,

12 - external input R of synchronous setting to zero state,

13 - external outputs Q1, Q2, ..., QN,

14 - KM mask switch,

15 - register of the current mask RM2.

The device for unpacking data contains an input data IMD bus 1 connected to the input data register RD 2, a multi-output block FU of priority 3, which contains w groups of outputs of pointers of high-order symbols U1, US2, ..., Uw in N bits (where w is the number of input characters), a group of N switches KD data 4 ₁ , 4 ₂ , ..., 4 _N , a group of N registers with a synchronous input R set to zero, an output buffer BQ 6, the outputs of which contain N output symbols Q1, Q2, ..., QN by k bits and which are external outputs of the device 13, the OR-NOT element 7, N groups 8 ₁ , 8 ₂ , ..., 8 _N by k elements 2I, register RM1 of the general mask 9, D-flip-flop 10 with a synchronous input R setting to zero , switch KM mask 14 and register RM2 of the current mask 15.

In addition, the device contains an external synchronization input C 11, an external input R synchronously zeroing 12, an internal data-mask bus MD of w symbols by k bits, an internal priority bus (residual mask) MS, which is a group of second outputs of a multi-output priority block 3, the internal N-bit line of the QM common symbol mask, which is the group of outputs of the register RM1 of the common mask 9, the zero flag FZ and the internal N-bit line of the current M symbol mask.

Input register RD data 2, N group of registers 5 ₁ , 5 ₂ , ..., 5 _N , output buffer BQ 6, register RM1 of general mask 9, D-flip-flop 10 and register RM2 of current mask 15 contain synchronization input C and input synchronous setting to zero state R.

External input C of synchronization 11 and external input R of synchronous setting to zero state 12 are connected, respectively, to the inputs of synchronization C and inputs R of synchronous setting to zero state of the input register RD data 2, N groups of registers 5 ₁ , 5 ₂ , ..., 5 _N , output buffer BQ 6, register RM1 of general mask 9, D-flip-flop 10 and register RM2 of the current mask 15.

The input IMD bus of the data-mask 1 contains L bits (L ≥ max (N, w * k) where w is the number of symbols by k bits, N bits of the mask). The input bus 1 sequentially receives masks of non-zero symbols IM and data sets ID.

Input data register 2 is for temporary storage of IM non-zero character masks and ID data sets. In this case, the outputs of the input data register 2 are the internal data-mask bus MD.

Output BQ buffer 9 contains N * k and is designed to store the output sequences of unpacked character values.

The register RM1 of the common mask 9 is intended for storing the common mask during the decompression time and is used to select all non-zero symbols and transfer them to the inputs of the output buffer BQ 6.

Register RM2 of the current mask 15 is designed to select the current non-zero characters and enable their loading into the group of registers 5 ₁ , 5 ₂ ,…, 5 _N.

D-flip-flop 10 is designed to control writing to the output buffer biv register RM1 of the general mask 9. The TCE output of the D-flip-flop 10 set to the single state TCE = 1 allows loading the unpacked data into the output buffer BQ 6 and determines the transfer of the general mask through the switch KM mask 14 and enables the loading of the mask into the register RM1 of the general mask 9.

The switch KM mask 14 transmits the general or current masks.

Multi-output unit FU of priority 3 generates unitary codes "1 of N" at the outputs of each of w groups, which correspond to the value of the code on the internal bus of the current mask M. Unitary codes "1 of N" are formed in priority order of priorities. Switches KD data 4 ₁ , 4 ₂ , ..., 4 _N are designed to extract from w symbols by k bits from the internal bus of the MD data mask one of the symbols allowed in accordance with the unitary code "1 of N" set at the outputs w of groups of N bit high unit pointers U1, U2,…, Uw.

Outputs of a group of N data switches 4 ₁ , 4 ₂ , ..., 4 _{N are} connected to the corresponding information inputs D of the same-name registers of a group of N registers 5 ₁ , 5 ₂ , ..., 5 _N , in which the control inputs of the CE permission to work are connected to the same-name bits internal N-bit bus of the current mask of M.

A group of N registers 5 ₁ , 5 ₂ , ..., 5 _{N is} intended for recording at each clock cycle up to w nonzero symbols of k bits of input data ID, in accordance with the code set on the internal N-bit first bus of the M symbol mask.

The outputs QB1, QB2, ..., QBN of all N registers 5 ₁ , 5 ₂ , ..., 5 _{N are} connected in groups with the corresponding first inputs of elements 2I of the same N groups 8 ₁ , 8 ₂ , ..., 8 _N , the outputs of which are connected to the corresponding groups information inputs IQ1, IQ2, ..., IQN of the output buffer VO 6, which is designed to store the recovered values after unpacking the data.

The second inputs of elements 2I from N groups 8 ₁ , 8 ₂ , ..., 8 _N in groups are interconnected and connected to the corresponding bits of the same name of the internal N-bit common mask of symbols QM, which is the outputs of the mask register 9, which has a group of information D-inputs connected to N bits of the internal bus of the current mask of symbols M. The bits of the general mask of symbols QM allow the transmission of nonzero symbols after restoration from the outputs QB1, QB2, ..., QBN of all N registers 5 ₁ , 5 ₂ , ..., 5 _N in groups through elements 2I from N groups 8 ₁ , 8 ₂ , ..., 8 _N for input groups IQ1, IQ2, ..., IQN symbols of the output buffer BQ 6.

The internal bus of the priority (residual mask) MS, which is a group of second outputs of the multi-output block of priority 3, is connected to the inputs of the OR-NOT element 7, the output of which is the FZ zero flag and is connected to the information D-input of the D-flip-flop 10, the output of which is connected to the inputs of CE for enabling the output buffer BQ6, register RM1 of the general mask 9 and the control input of the switch KM mask 14.

The single value of the zero flag FZ = 1 is formed if zero values are set in all bits at the output of the switch KM mask 14.

The outputs of the output buffer BQ 6 contain N output symbols Q1, Q2, ..., QN in k bits and are external outputs of the device 13.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows.

The IMD mask code and the input data ID codes are sequentially received on one input data-mask IMD bus 1. The general mask code IM is stored in the general mask register RM1 during the decompression time of the DD dataset of N characters by k bits. The current mask being formed is stored in the RM2 register of the current mask 14.

Before starting work, all registers and D-flip-flop 10 are set to zero, and the zero flag takes on a single value FZ = 1.

After packing (compressing) the DD data containing N symbols of k bits each (Fig. 2), a sequence of compressed data is formed, the elements of which consist of one group of the IM symbol mask with a width of N and from the corresponding groups of ID data (symbols) containing up to w nonzero symbols for k data bits (Fig. 3). The maximum number of elements in the input sequence is Z =] N / w [(greater integer) when the number of non-zero characters V is greater than (N-w + 1).

The input data bus 1 of the proposed device receives an input sequence of packed data containing N bits of the IM symbol mask and input data bits of non-zero symbols ID, starting with the most significant symbols, which consist of w symbols by k bits each (Fig. 3). In this case, the unit value of the bits of the IM symbol mask corresponds to nonzero symbols in the original DD data before packing (compression).

The multi-output unit FU of priority 3 determines not only the signal with the highest priority, but also determines the signals with the second, third, ..., wth priority. In accordance with the code of the current mask M at the outputs of the multi-output block of priority 3, w priority groups U1, U2, ..., Uw are formed in priority order of priority. In this case, each of the N bits of the M symbol mask is assigned a fixed priority. In the device, the highest priority is assigned to the highest N-th bit of the N bits of the mask of symbols M, and then the priority decreases from bit to bit with decreasing bit number. The lowest priority is set for the lower 1st bit of the symbol mask M. Among the output w groups U1, U2, ..., Uw of the multi-output block of priority 3, the highest priority is assigned to the lowest first group U1, and then the priority decreases from group to group with increasing group number. The lowest priority is set for the group with the highest number Uw. At the outputs of each of the w priority groups U1, U2, ..., Uw, a result is generated in the form of a unitary code "1 from N" - a single signal will be set only at one output corresponding to the highest (senior) priority. The highest priority in each of the w priority groups U1, U2,…, Uw is assigned to the bit with the highest number.

Further, in accordance with the values w of the priority groups U1, U2, ..., Uw, no more than w corresponding non-zero symbols of the input data ID from the internal bus of the data-mask MD are transmitted to the outputs of the group of N data switches 4 ₁ , 4 ₂ , ..., 4 _N.

At the same time, a new value is written into the register RM2 of the current mask 15 from the internal MS priority bus, in which w bits of the most significant ones are excluded, which correspond to the processed non-zero symbols of the first group ID11, and the single values of the MS priority bus correspond to the next non-zero characters in the sequence.

On the next clock cycle, in accordance with the unit values of N bits of the current code, from the internal bus of the mask of symbols M, up to w input non-zero symbols of k bits are written from the internal bus of the mask of symbols MD, corresponding to w unit values, starting with the most significant bits of the current mask of symbols of M, and zero symbol values corresponding to the ones exceeding w, starting from the most significant bits of the current symbol mask M, into the corresponding registers 5 ₁ , 5 ₂ , ..., 5 _N.

Simultaneously, from the input data bus 1, the following values of the elements of the packed (compressed) data sequence are received into the input data register 2. Further, the data is restored in the same way and up to w next input non-zero symbols are received in k bits in the corresponding registers 5 ₁ , 5 ₂ , ... , 5 _N , in accordance with the values of the digits of the current character mask M.

If at the current cycle all the unit values of the digits of the current symbol mask M are processed, then zero values are set in all bits of the internal MS priority bus at the outputs of the multi-output unit FU of priority 3, a unit value of the zero flag FZ = 1 is formed and at the next cycle the unit value is set at the output D-flip-flop 10.

In addition, for each new input data DD on the first clock cycle, the primary value of the symbol mask IM, corresponding to all V non-zero symbols of the N input symbols before packing (compression), is written into the register RM1 of the general mask 9 at a single value at the output of the D-flip-flop 10.

In each cycle, in accordance with the unit values of the bits of the register RM1 of the general mask 9, the values of the symbols QB1, QB2, ..., QBN from the outputs of the corresponding registers 5 ₁ are transmitted to the outputs of N groups of k elements 2I 8 ₁ , 8 ₂ , ..., 8 _N , 5 ₂ , ..., 5 _N , or zero symbols are formed corresponding to the zero values of the bits of the register RM1 of the general mask 9. The values from the outputs of N groups of k elements 2I 8 ₁ , 8 ₂ ,…, 8 _N are fed to the inputs of the symbols IQ1, IQ2, ..., IQN of the output buffer BQ 6, which, with a single value at the output of the D-flip-flop 10, are written in the next clock cycle into the output buffer BQ 6 and fed to the external outputs 13 of the device. In this case, N output symbols by k bits of recovered data Q1, Q2, ..., QN (Fig. 4) correspond to DD data before packing (compression) without loss of information.

The proposed device works as follows.

When a single signal is applied to the input 12 of the synchronous setting R to the zero state by the clock signal C, the input register RD of data 1, a group of N registers 5 ₁ , 5 ₂ , ..., 5 _N , the output buffer BQ6, are set to the zero state at the external input 11, register RM1 of the general mask 9, D-flip-flop 10 and register RM2 of the current mask 15. In this case, zero values are also set in all N bits of the internal priority bus (residual mask) MS and the internal bus of the general mask of symbols QM, at all outputs of the multi-output priority block FU 3 and a single value of the zero flag FZ = 1 is formed at the output of the OR-NOT element 7.

Further, in the first clock cycle, the code of the first symbol mask IM1 is received from the input data bus 1 into the input data register RD 2. In this case, the reception in registers 5 ₁ , 5 ₂ , ..., 5 _N , and the output buffer BQ6 is not performed, since they have zero signals set at the CE enable inputs, which come from the output of the D-flip-flop 10. At the same time, D is set to a single state -trigger 10, since the zero flag FZ = 1 is set.

Further, the value of the symbol mask IM1 is transmitted to the input of the register RM1 of the general mask 9 and through the switch of the mask KM 14 to the input of the register RM2 of the current mask 15, the reception into which is carried out by the next clock signal C at the external input 11. At the same time, the first group ID11 from w input characters into data register RD 2 from input data bus 1 IMD.

In this case, in accordance with the code of the mask IM1, from the output of the register RM2 of the current mask 15, at the outputs of the multi-output unit FU of priority 3, w priority groups U1, U2, ..., Uw are formed in the order of priority priority. At the outputs of each of the w priority groups U1, U2, ..., Uw, a result is generated in the form of a unitary code "1 from N" - a single signal will be set only at one output corresponding to the highest (senior) priority. In accordance with the unit values of the priority signals U1, U2, ..., Uw in a group of N data switches 4 ₁ , 4 ₂ , ..., 4 _N , no more than w corresponding nonzero data symbols ID11 are transmitted to the outputs, and at the other outputs of the data switches 4 ₁ , 4 ₂ ,…, 4 _N set to zero characters.

At the same time, the bits of the QM mask code from the output of the RM2 register of the current mask 15 are transmitted to the corresponding CE inputs of the same name, allowing the operation of registers 5 ₁ , 5 ₂ , ..., 5 _N. , Which are received in the next clock cycle for all single values of the common QM mask code. In addition, if at the current clock cycle all the unit values of the digits of the current symbol mask M have been processed or if all the bits of the input mask IM have zero values, then zero values are set in all bits of the internal priority bus (residual mask) MS, which are fed to the outputs of the multi-output block FU priority 3 and further, according to which a single value of the zero flag FZ = 1 is formed at the output of the OR-NOT element 7, and if there are unprocessed single digits of the current mask of symbols M, the zero value of the zero flag FZ = 0 is formed.

According to the next clock pulse C, in accordance with the unit values of the bits of the code of the current mask M, the corresponding registers 5 ₁ , 5 ₂ , ..., 5 _N are written to w input non-zero symbols in k bits from the bus of the current mask M, starting with the most significant bits of the current mask symbols M, and null symbol values corresponding to the values of the current mask of M symbols, greater than w. In this case, a new value is also written into the register RM2 of the current mask 15 from the internal priority bus (residual mask) MS, in which w bits of the most significant unit values are excluded, which correspond to the processed nonzero symbols of the first group ID11, and the unit values of the MS priority bus correspond to the following nonzero characters of elements of the input sequence.

In addition, the corresponding value of the zero flag FZ is received in the D-flip-flop 10, which controls the switch CM of the mask 14. At the same time, the next data ID or the mask of symbols IM from the input data bus 1 is received into the input register 2.

Further, similarly, as in the previous clock cycles, the analysis of the next single digits of the code of the current mask M is carried out and in a group of N data switches 4 ₁ , 4 ₂ , ..., 4 _N , the corresponding next w nonzero symbols of the input data ID from the internal data bus MD are transmitted to the outputs -masks.

Simultaneously at each cycle, in accordance with the unit values of the digits from the register RM1 of the general mask 9 set on the QM mask code bus, the values of the symbols QB1, QB2, ... are transmitted to the outputs of N groups of k elements 2I 8 ₁ , 8 ₂ , ..., 8 _N , QBN from the outputs of the corresponding registers 5 ₁ , 5 ₂ , ..., 5 _N , or zero characters are formed corresponding to the zero values of the bits of the register RM1 of the general mask 9. Values from the outputs of N groups of k elements 2I 8 ₁ , 8 ₂ , ..., 8 _N come to the inputs of the symbols IQ1, IQ2, ..., IQN of the output buffer BQ 6, which, with a single value at the output of the D-flip-flop 10, on the next clock are written to the output buffer BQ 6 and go to the external outputs 13 of the device. In this case, N output symbols by k bits of recovered data Q1, Q2, ..., QN (Fig. 4) correspond to DD data before packing (compression) without loss of information.

In the clock cycle in FIG. 5 shows an example of a sequence of input data sets for DD1, ..., DD5, elements of the sequence of codes at the input of the device after packing (compression), containing IM mask codes and codes of ID character sets, and recovery of compressed data in the proposed device, with the number of input characters N = 16 of k = 4 bits and the number of characters w = 4 in the input data ID. FIG. 5 in brackets is the form of data representation - binary (2) or hexadecimal (16).

In cycle 1, the sixteen symbols of the first data DD1 before packing (compression) contain four nonzero symbols (B, A, 5, 2), which are further compressed, and the corresponding mask IM1 = 0C24 is formed, and then the mask code and data are sequentially received via the input bus IMD data mask 1 into the proposed device. In cycle 1, the mask code IM1 = 0C24 is first received, which is received in the input register 2 in cycle 2 and is transmitted to the internal mask data bus MD. Further, the mask code IM1 = 0С24 is transmitted to the input of the register RM1 of the general mask 9 and with a single value of TCE = 1 at the output of the D-flip-flop 10 it is also transmitted to the input of the register RM2 of the current mask 15, the reception of which is carried out in cycle 3. This sets the zero value the zero flag FZ = 0, which is transmitted to the output TCE = 0 of the D-flip-flop 10 at clock 3.

Simultaneously, on cycle 3, in accordance with the value of the mask code IM1 = 0С24 from the output of register RM2 of the current mask 15, the multi-output unit FU of priority 3 forms w priority groups U1 = 0800, U2 = 0400, U3 = 0020, U4 = 0004, according to which the data is restored in a group of N = 16 data switches 4 ₁ , 4 ₂ , ..., 4 ₁₆ , and then the results of restoration in clock cycle 4 are written to registers 5 ₁ , 5 ₂ ,…, 5 ₁₆ (QB1, QB2,…, QB16). At the same time, the code MS = 0000, from the internal bus of the priority (residual mask) MS, passes through the switch KM of the mask 14, since the zero state is set at the output TCE = 0 of the D-flip-flop 10, and which at clock 4 is written into the RM2 register of the current masks 15. In this case, the unit value of the zero flag FZ = 1 is set, which further sets the output of D-flip-flop 10 to a unit value TCE = 1 in step 5.

Simultaneously, on cycle 4, in accordance with the unit values of the bits QM = 0C24 of the RM1 register of the general mask 9, the values of the symbols QB1, QB2, ..., QB16 are transmitted to the outputs of N groups of k elements 2I 8 ₁ , 8 ₂ , ..., 8 ₁₆ from the outputs of the corresponding registers 5 ₁ , 5 ₂ , ..., 5 ₁₆ , which are fed to the inputs IQ1, IQ2, ..., IQ16 of the output buffer 6 and the recovered data (B, A, 5, 2) are written on the next clock cycle 5 to the output buffer 6 and fed to external outputs 13 of the corresponding output symbols Q1, Q2, ..., Q16 (QD1 in Fig. 5), with a single value at the output of the D-flip-flop 10. Thus, unpacking the input DDI data containing the mask IM1 = 0C24 and four non-zero symbols ID1 = BA52, which arrived at measures 1 and 2, was carried out in four measures.

In cycle 3, the second data DD2 before compression contains all zero characters. Therefore, the zero bits of the mask IM21 = 0000 are formed, which in clock cycle 4 are written into the input RD register 2 and enter the data mask MD bus, and then, with a single value of TCE = 1 at the output of the D-flip-flop 10, they pass through the switch KM of the mask 14 and are received into the register RM2 of the current mask 15, as well as into the register RM1 of the general mask 9. In this case, zero values are generated at all outputs U1-U4 of the FU block of priority 3. Therefore, in step 5, no writing is made to registers 5 ₁ , 5 ₂ , ..., 5 ₁₆ , in which the previous information is stored. But since zero information is set in the register RM1 of the general mask 9, then at the outputs of the elements 2I 8 ₁ , 8 ₂ , ..., 8 _N zero values of the character codes are also set, therefore, at the inputs IQ1, IQ2, ..., IQ16 of the output buffer BQ 6 zero values are formed, which are written in cycle 6 into the output buffer BQ 6 (QD2 are all zeros in Fig. 5).

In cycle 4, the third data DD3 contains eight nonzero symbols (E, B, 9, 8, 7, 6, 3, 1), which are compressed and the corresponding general mask IM3 = 4B6A is formed, containing eight one bits for all nonzero symbols. The mask code IM3 = 4B6A in cycle 4 is received via the input IMD bus of data-mask 1, is received in the input RD register 2 and in cycle 5 and is transmitted to the internal bus of the MD data-mask. Further, the mask code IM3 = 4B6A is transmitted to the input of the RM1 register of the general mask 9 and, with a single value of TCE = 1, at the output of the D-flip-flop 10, it is also transferred to the input of the RM2 register of the current mask 15. The reception in registers 9 and 15 is carried out in cycle 6. Simultaneously in in step 5, the zero value of the zero flag FZ = 0 is set, which in step 6 sets the value TCE = 0 at the output of D-flip-flop 10.

Simultaneously, in cycle 5, the code ID31 = EB98 corresponding to the first four non-zero symbols is received on the input IMD bus of the data-mask 1, and in cycle 6 the code ID32 = 7631 corresponding to the second four non-zero symbols of the third data DD3 is received. At the same time, at the same time at step 6 for the code of the current mask M = 4B6A from the register RM2 of the current mask 15 is transmitted to the multi-output unit FU of priority 3 and w = 4 groups of priority U1 = 4000, U2 = 0800, U3 = 0200, U4 = 0100 are formed, according to which recover data ID31 = EB98 in a group of N = 16 data switches 4 ₁ , 4 ₂ , ..., 4 ₁₆ , and then the results of recovery in step 7 are written into eight corresponding registers 5 ₁ , 5 ₂ , ..., 5 ₁₆ (QB1 , QB2, ..., QB16) in accordance with the current mask IM3 = 4B6A from the RM2 register of the current mask 15. In this case, zero values will be written to registers 5 ₁ , 5 ₂ , ..., 5 ₁₆ corresponding to the four least significant single digits of the mask, and in the digits corresponding to all zero values of the code of the current mask M = 4B6A, the previous values are retained.

Simultaneously, in cycle 6, the code MS = 006A, from the internal priority bus (residual mask) MS, passes through the switch KM of mask 14, since the value TCE = 0 is set at the output of D-flip-flop 10, and at cycle 7 it is written into the RM2 register of the current mask 15 and the current mask code is set M = 006A. Therefore, in step 7 for the code of the current mask M = 006A, from the output of the register RM2 of the current mask 15, in the multi-output block FU of priority 3, w = 4 priority groups U1 = 0040, U2 = 0020, U3 = 0008, U4 = 0002 are formed, according to which data recovery ID32 = 7631 is performed in a group of N = 16 data switches 4 ₁ , 4 ₂ , ..., 4 ₁₆ , and then the results of recovery in cycle 8 are written into eight corresponding registers 5 ₁ , 5 ₂ , ..., 5 ₁₆ (QB1, QB2, ..., QB16) in accordance with the code of the current mask M = 006A from the register RM2 of the current mask 15. Simultaneously, in step 7, the zero code of the residual mask MS = 0000 is generated, according to which a single value of the zero flag FZ = 1 is formed and further in step 8 in the single state TCE = 1 is set at the output of the D-flip-flop 10, which allows the reception of the next mask code IM4 = 1610 for the fourth data DD4.

In addition, on cycle 8, in accordance with the unit values of the bits QM = 4B6A of the RM1 register of the general mask 9, the values of the symbols QB1, QB2, ..., QB16 are transmitted to the outputs of N groups of k elements 2I 8 ₁ , 8 ₂ , ..., 8 ₁₆ from the outputs the corresponding registers 5 ₁ , 5 ₂ , ..., 5 ₁₆ , which are fed to the inputs IQ1, IQ2, ..., IQ16 of the output buffer BQ 6 and the recovered data of non-zero symbols (E, B, 9, 8, 7, 6, 3, 1) are written on the next clock cycle 9 into the output buffer 6, with a unit value of TCE = 1 at the output of the D-flip-flop 10, and are fed to the external outputs 13 of the corresponding output symbols Q1, Q2, ..., Q16 (QD3 in Fig. 5).

Simultaneously, in step 7, the fourth data DD4, containing four non-zero symbols (A, C, F, 4), is compressed and the corresponding general mask IM4 = 1610 is formed, containing four one-bits for all non-zero symbols. The mask code IM4 = 1610 in clock cycle 8 is received in the input register RD2 and is transferred from the outputs to the internal mask data bus MD. Further, the mask code IM4 = 1610 is transmitted to the input of the RM1 register of the general mask 9 and with a single value of TCE = 1 at the output of the D-flip-flop 10 it is also transmitted to the input of the RM2 register of the current mask 15, which are received in step 9. At the same time, in step 8, it is set the zero value of the zero flag FZ = 0, since the general mask code IM4 = 1610 is set at the output of the KM mask switch 14, and in step 9 the zero state is set at the output of TCE = 0 of the D-flip-flop 10. Simultaneously, in step 9, a group of input symbols is received ID41 = ACF4 to RD Data Register 2 from Input Data Bus 1.

In cycle 9, in accordance with the value of the mask code IM4 = 1610 from the output of the register RM2 of the current mask 15, the multi-output unit FU of priority 3 forms w priority groups U1 = 1000, U2 = 0400, U3 = 0200, U4 = 0010, according to which data is restored to a group of N = 16 data switches 4 ₁ , 4 ₂ , ..., 4 ₁₆ , and then the results of recovery in clock cycle 10 are written into the corresponding registers 5 ₁ , 5 ₂ ,…, 5 ₁₆ (QB1, QB2,…, QB16). In this case, from the internal bus of the priority (residual mask) MS, the code MS = 0000 passes through the switch KM of the mask 14, since the zero state is set at the output TCE = 0 of the D-flip-flop 10, and a single value of the zero flag FZ = 1 is set, according to which in step 10, a single state is set at the output TCE = 1 of D-flip-flop 10.

At the same time, in cycle 10, in accordance with the unit values of the bits QM = 1610 of the RM1 register of the general mask 9, the values of the symbols QB1, QB2, ..., QB16 are transmitted to the outputs of N groups of k elements 2I 8 ₁ , 8 ₂ , ..., 8 ₁₆ from the outputs of the corresponding registers 5 ₁ , 5 ₂ , ..., 5 ₁₆ , which are fed to the inputs IQ1, IQ2, ..., IQ16 of the output buffer BQ 6 and the recovered data (A, C, F, 4), are written on the next clock cycle 11 to the output buffer BQ 6 and are fed to the external outputs 13 of the corresponding output symbols Q1, Q2, ..., Q16 (QD4 in Fig. 5), with a single value of TCE = 1 at the output of the D-flip-flop 10.

In addition, in step 9 for the fifth data DD5, which contain all zero characters, the zero bits of the mask IM5 = 0000 are formed, which in step 10 are written into the input RD register 2 and fed to the data mask-data bus MD, and then with a single value of TCE = 1 at the output of the D-flip-flop 10 pass through the switch KM of the mask 14 and are received into the register RM2 of the current mask 15, as well as into the register RM1 of the general mask 9. At the same time, zero values are generated at all outputs of the FU block of priority 3, therefore, in cycle 11, no writing to registers 5 ₁ , 5 ₂ ,…, 5 ₁₆ , in which the previous information is saved. But, since zero information is set in the register RM1 of the general mask 9, then the outputs of the elements 2I 8 ₁ , 8 ₂ , ..., 8 _{N are} also set to zero values of the character codes, therefore, at the inputs IQ1, IQ2, ..., IQ16 of the output buffer BQ 6 zero values are also formed, which are written in cycle 12 to the output buffer BQ 6 and are fed to the external outputs 13 of the corresponding output symbols Q1, Q2, ..., Q16 (QD5 all zeros in Fig. 5), with a unit value of TCE = 1 at the output D -trigger 10.

Thus, the above information allows us to conclude that the proposed device solves the task of unpacking data without losing information. In this case, N output symbols by k bits of recovered data Q1, Q2, ..., QN correspond to DD data before packing (compression) without loss of information.

In comparison with the prototype in the proposed device, the bit width of the input data is reduced by eliminating the external N-bit bus of the IM symbol mask. It also reduces the amount of storage space after packaging and the amount of information transferred.

Thus, the above information allows us to conclude that the proposed device provides unpacking of input data without loss, has regularity of nodes and connections, simplicity of design and the device corresponds to the claimed technical result - a reduction in the bit width of the input data and a decrease in the amount of memory for storing a sequence of groups of input data of binary characters ...

Claims (9)

A device for unpacking data containing the IMD bus of input data 1, connected to the input data register RD 2, a multi-output block FU of priority 3, which contains w groups of outputs of pointers of high-order symbols U1, U2, ..., Uw by N bits each (where w is the number of input characters), a group of N switches KD data 4 ₁ , 4 ₂ , ..., 4 _N , a group of N registers 5 ₁ , 5 ₂ , ..., 5 _N with a synchronous input R set to zero, an output buffer BQ 6, whose outputs contain N output symbols Q1, Q2, ..., QN by k bits and which are external outputs of the device 13, OR-NOT element 7, N groups 8 ₁ , 8 ₂ , ..., 8 _N by k elements 2 AND, register RM1 of the general mask 9 , D-flip-flop 10 with a synchronous input R set to zero, and also containing an external input C of synchronization 11, an external input R of synchronous zeroing 12, an internal data-mask bus MD of w symbols of k bits each, an internal priority bus (residual mask) MS, which is a group of second outputs of a multi-output block of priority 3 , the internal N-bit bus of the general mask of symbols QM, which is the group of outputs of the register RM1 of the general mask 9, and the zero flag (flag of zero symbols) FZ, moreover, the external input C of synchronization 11 and the external input R of synchronous zeroing 12 are connected, respectively, to the inputs of synchronization C and inputs R of synchronous zeroing of the input register RD of data 2, N groups of registers 5 ₁ , 5 ₂ , ..., 5 _N , output buffer BQ 6, register RM1 of the general mask 9 and D-flip-flop 10, moreover, the outputs of the input register 2 are the corresponding w * k bits of the internal data-mask bus MD, which are connected to the information inputs of each data switch KD of a group of N data switches 4 ₁ , 4 ₂ , ..., 4 _N , the control inputs of which are connected to the corresponding with the same name bits w of groups of outputs U1, U2, ..., Uw of a multi-output unit FU of priority 3, while the outputs of a group of N switches KD data 4 ₁ , 4 ₂ , ..., 4 _{N are} connected to the corresponding information inputs D of the same-name registers of a group of N registers 5 ₁ , 5 ₂ , ..., 5 _N , whose outputs QB1, QB2, ... , QBN of all N registers 5 ₁ , 5 ₂ , ..., 5 _{N are} connected in groups with the corresponding first inputs of elements 2I of the same N groups 8 ₁ , 8 ₂ , ..., 8 _N , the outputs of which are connected with the corresponding groups of information inputs IQ1, IQ2, ..., IQN of the output buffer BQ 6, and the second inputs of elements 2I of N groups 8 ₁ , 8 ₂ , ..., 8 _N are interconnected in groups and connected to the corresponding bits of the same name of the internal N bit bus of the general mask of symbols QM, in addition, the output of the OR-NOT element 7 is a zero FZ flag and is connected to the information D-input of the D-flip-flop 10, the output of which is connected to the CE input for enabling the operation of the register RM1 of the general mask 9 and is connected to the CE input for enabling the output buffer VO 6, characterized in that the switch KM of the mask 14 and the register RM2 of the current mask 15 are additionally introduced into it, in which the synchronization input C is connected to the external input C of synchronization 11, and the input R of the synchronous setting to the zero state is connected to the external input 12 of the synchronous setting to the zero state , and also introduced the internal N-bit bus of the current mask of symbols M, moreover, the internal data-mask bus MD is also connected to the information inputs of the general mask register 9 and to the first group of information inputs of the switch KM of the mask 14, in which the second group of information inputs is connected to the internal priority bus (residual mask) MS, and the third control input of the switch selection KM mask 14 is connected to the output of the D-flip-flop 10, the group of outputs of the switch KM mask 14 is connected to the inputs of the OR-NOT element 7 and to the information inputs of the register RM2 of the current mask 15, the group of outputs of which is connected to the group of inputs of the multi-output block of priority 3 and is the internal bus of the current mask of symbols M, the bits of which are connected to CE inputs of the same name groups of registers 5 ₁ , 5 ₂ ,…, 5 _N.

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