RU2711752C2 - Data frequency adjustment method and phase detector - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: invention relates to a method of adjusting a clock frequency on data edges and a phase detector. Method consists in that signals at first and second outputs of detector are controlled by connection of first and second bipolar signals for summation, bipolar signals are summed up, filtered, the generated signal is used to control the generator frequency, the generator frequency is divided and the bars are formed, wherein at the first output of the detector a signal is generated from the data front to the next difference of cycles, wherein if the data front arrives at the center of the holding area, after the signal at the first output of the detector is completed, a signal is generated at the second output of the detector from the front of the beats to the beat of the slots, wherein the number of fronts of cycles passed after the arrival of the previous data front is considered, and in the control region with increasing the number of counted fronts of the cycles, the amplitude of the first and second bipolar signals is reduced.

EFFECT: technical result consists in improvement of stability in retention mode while maintaining high speed.

5 cl, 5 dwg

Description

The invention relates to radio engineering.

In the absence of direct clock transmission when receiving discrete signals, for correct data gating and time synchronization, it is necessary to adjust the clock frequency according to the data at a certain phase shift.

A known method of adjusting the frequency [1] for data switching. Data switching occurs twice as often as fronts. The method [1] has a large phase noise and low speed. Phases of edges and slices, as well as signals of additional channels with different delays, do not fall into a single time grid, which increases phase noise and reduces loop stability.

Known high-speed ways to adjust the clock frequency on the edges (or slices) of the data [2, 3].

A method for adjusting the clock frequency along the data fronts [2], in which the signals of the first and second outputs of the detector control the connection of the first and second bipolar signals for summing, the bipolar signals are summed, filtered, the generator frequency is controlled by the received signal, the generator frequency is divided and the clocks are formed, and the first output of the detector generates a signal from the data front to the next clock switching, if the data front arrives later than the center of the hold zone, then after the signal ends at the first output the tectors form a signal at the second output of the detector, a signal from the front of the steps to the cut of the steps.

When adjusting the frequency for a variable comparison frequency (for data differences) methods [1. 2. 3] have less stability than in the mode of operation at the average "constant" comparison frequency. Data Switch Timeout T:

where Tc is the cycle period (Tc = 1 / Fc), Fc is the clock (symbol) frequency; m = 2, 3, ...

Variable latency waiting for data switching affects the gain and loop band. A loop stable at the average frequency of the leading edges may not work correctly at large intervals between the data fronts T≥m _cr × Tc, where m _cr is the critical value of m, from which it may begin, stability loss and exit from the hold mode are possible. The maximum values are the number of waiting periods for switching (edges) of the data and m _cr for the methods [1. 2. 3] are the same.

Closest to the proposed are the method and phase detector [2] (prototypes).

Known phase detector [2], containing the detector and the driver of the bipolar signals, and the inputs of the detector are connected in pairs, respectively, with the inputs of the reference frequency and the input of the clock.

The purpose of the invention (technical result) is to increase stability in the holding mode while maintaining speed. The technical result is achieved by the fact that:

- consider the number of clock fronts that have passed after the receipt of the previous data edge, and in the regulation area, with an increase in the number of counted clock fronts, the amplitudes of the bipolar terms are reduced;

- a fixed ratio of the amplitude of the first bipolar signal to the amplitude of the second bipolar signal is established, this ratio is preserved when the amplitudes of the bipolar signals change, after the signal ends at the first output of the detector, a signal is always generated at the second output of the detector from the front to the cutoff of the clocks;

- a fixed ratio of the amplitudes of the first and second bipolar signals equal to two;

- the phase detector further comprises three D-flip-flops, two AND elements, an OR element, a counter, a code converter and a digital-to-analog converter, the clock input being connected to the C-inputs of three D-triggers and a counter, the reference frequency input being connected to the D-input the first trigger and the first input of the first AND element, the output of the first AND element is connected to the counter reset input and the first input of the OR element, the output of the first D trigger is connected to the D input of the second D trigger, the output of which is connected to the first input of the second AND element and D-in third D-flip-flop, whose inverse output is connected to other inputs of the first and second AND elements, the counter transfer output is connected to another input of the OR element, the output of which is connected to the CE input of the counter, the outputs of which are connected in pairs respectively with the inputs of the code converter, the outputs of which are connected in pairs respectively, with the inputs of the digital-to-analog converter, the output of which is connected to the control input of the bipolar signal former;

- where C is the input of the second D-trigger - direct, and C-inputs of the first and third D-triggers and counter - inverse.

The group of inventions is related by a common concept and satisfies the requirement of unity of invention, because a phase detector is part of a device for implementing the proposed method. When analyzing the level of technology and novelty of the claimed objects, no analogues were found with the above set of the above features. Therefore, the described technical solution meets the criterion of "novelty."

In FIG. 1. presents a frequency adjustment method and a phase detector. A timing diagram of operation with the center of the holding zone along the clock slice is shown in FIG. 2, and the corresponding detector and an example of controlling the amplitude of bipolar signals are shown in FIG. 3. A timing diagram of operation with the center of the retention zone offset from the cut of the clocks is shown in FIG. 4, a corresponding detector and an example of controlling the amplitude of bipolar signals, and - in FIG. 5. In the time diagrams of FIG. 2 and 4 also show the signals at the outputs of the elements of the phase detector. Examples of controlling the amplitudes of bipolar signals (Figs. 3 and 5) are implemented on "current mirrors" for n-p-n and p-n-p bipolar transistors. Functionally similar current circuits on CMOS transistors require a larger number of elements to ensure low residual voltage and bias gate currents.

The method of adjusting the clock frequency Fc on the edges of the data Fo (Fig. 1 and 2), in which the signals at the first P and second N outputs of the detector 2 control the connection of bipolar signals Sp and Sn (sources 121, 122 and keys 131, 132) for summing, sum S, filter 3, the signal U is controlled by the frequency of the oscillator 4, the frequency of the oscillator is divided and the clocks Fc are generated, and at the first output P of the detector 2, a signal is generated from the data front Fo to the next switching clock cycle Fc, and if the data front Fo arrives later center of the retention zone, then after the end The signal at the first output of the detector generates a signal at the second output of the detector, the signal from the edge of the Fc clocks to the cut of the Fc clocks, while 147 count the number of clock edges of the Fc clocks after the previous data edge Fo arrives, with an increase in the number of counted clock edges 147, the amplitudes of the bipolar signals reduce A (149).

In a fast phase-locked loop (PLL) in the hold mode, the frequency error Δω should be worked out, where {Δω = 2π × (Fc-Fo)}, and with some overshoot over several periods of the reference frequency (data drops).

Let in the hold mode upon receipt of the data front at time t _j , where j = 1, 2 ..., detector 2 detects a shift Δt _j and a phase error Δϕ _j . The frequency of the VCO 4 Fc changes in accordance with the transient response of the low-pass filter (LPF) 3. Upon receipt of the (j + 1) -th data edge at t _{(j + i)} = t _j + m _{(j + 1)} × T _C phase the error Δϕ _{(j + 1)} will be the initial (Δϕ _j ) minus the integral of the change in the frequency of the VCO 4 during the wait time j + 1 of the data front ..

For the stability of the PLL, it is necessary and sufficient that at every step:

where α is the coefficient, 0 <α <1.

Given the necessary margin for receiving data with noise and hardware loss, it is better to choose α: α≤0.5 ÷ 0.7

In the sequence of binary data, the front corresponds to the transition 0 → 1. In discrete data transmission channels, symbols are scrambled and uncorrelated; therefore, the probabilities of occurrence of binary 0 and 1 are 1/2. The probability of the appearance of the front in a given period of measures P _f = 1/4. Fcp average data edge frequency:

In the sequence of binary data, the transition 0 → 1 through m bits corresponds to the waiting time of the edge (the period of the edges) T with a duration of T = m × Tc.

The probability of a data sequence with a transition period of m bits Pm is determined by the formula:

where (m-1) is the number of variants of data sequences with a transition period of 0 → 1 m.

Ф _(m) is the probability of the appearance of a data front for m periods of cycles. Ф (m) with increasing m quickly approaches 1, so, for example, Ф ₍₇₎ = 0.94 and Ф ₍₁₆₎ = 0.995. Given the data transfer rate and long-term operation, it is necessary to ensure loop stability, despite the low probability of critical intervals.

A decrease in the amplitudes of the terms of the proposal will exclude dangerous overshoot and exit from the confinement zone at critical intervals. The low probability of occurrence of dangerous waiting times for data drops will allow, by reducing the gain in the loop only for critical intervals, to maintain the high speed ("wide" band) of the PLL.

The polarity of the terms S (Sp and Sn) implies an increase in the frequency of generator 4 with increasing voltage U. When the center of the confinement zone is ahead by the data front Fo, the clock frequency Fc is decreased, and when the front of the data Fo is behind the center of the confinement zone, the clock frequency Fc is increased. Bipolar signals can be obtained by connecting sources 121 and 122 to a unipolar Vcc power supply and a common GND wire (Figs. 1, 3, and 5). In the time diagrams of FIG. 2 and 4 additionally show the switching of the triggers 141, 142, 143 and the first element And 144 (R).

In the time diagram (Fig. 2), after m clocks calculated after the previous data edge Fo, with the control signal A (149), which corresponds to t, the data front Fo arrives at the time t ₁ before the center of the holding zone for a time t ₁ . On the front of the data Fo, the first signal of the detector P is generated and for the sum S a positive term whose amplitude is controlled by signal A (149). As a result, the voltage U increases slightly. In the process of a new calculation of the number of clock cycles, the signal A (149) gradually decreases to the next data edge. The next data edge comes after i clock cycles (i = 1, 2, ...) and for a time t ₂ later than the center of the hold zone. Along the data front, signals are generated at the output of the detector 2 P and N, and, accordingly, terms whose amplitude is controlled by signal A (149). As a result, the voltage U decreases somewhat. Note that during the formation of the sum S, the counting result and the control signal A do not change.

A simultaneous decrease in the amplitudes of bipolar signals in the work area can be carried out, for example, as a function of the number of periods of cycles, which is inversely proportional to the integral of the transition characteristic of the low-pass filter or its approximation.

In FIG. Figure 3 shows an example of controlling the amplitudes of bipolar signals from a current flowing signal A of DAC 149. Sources 121, 122 are made on bipolar transistors pnp 123-125 and. np-n 127, 128. For transistors with equal emitter areas and large coefficients h ₂₁ (β), we can assume that the collector currents are equal (see, for example, p. 75 Fig. 4-2, 4-3 [4] ) The amplitudes of the bipolar signals are equal and adjustable. The detector 2 for the center of the hold zone by the cut of clocks is built on the D-flip-flops 211, 212 and 213 and the elements And 221-224. All D-flip-flops are two-stage. The operation of a similar detector 2 for the center of the confinement zone along the clock front is given in [2].

In the timing diagram of FIG. 4 shows that after m clocks calculated from the previous data edge Fo, a bit later than the center of the holding zone (in the pause of clock pulses), the data front Fo arrives (in Fig. 4, time t ₁ ). The control signal A (149) corresponds to m. The detector signals P and N are generated along the data front, and for the sum S there are two (bipolar) terms, the amplitudes Sp and Sn (Sp = k × 1 and Sn = I), which are controlled by signal A (149). As a result, the voltage U decreases somewhat. The next data edge Fo arrives through i clock cycles (i = 1, 2, ...) and at a time t ₂ earlier than the center of the hold zone. After the data front, the detector signals P and N are formed, and the summands S (Sp and Sn), the amplitudes of which are controlled by signal A (149). As a result, the voltage U increases slightly.

An example of controlling the amplitudes of bipolar sources 121, 122 from the incoming current from output A of the DAC 149 (Fig. 5) Sources 121, 122 are made on bipolar transistors pnp 123-126 and npn 127,128. With equal areas emitters and large coefficients h ₂₁ (β), we can assume that the collector currents of the transistors are equal. The amplitude of the positive signal is equal to twice the amplitude of the negative signal (k = 2) and both are adjustable.

Detector 2 is built on D-flip-flops 211, 212 and elements And 221, 222 for the displaced center of the holding zone, relative to the cut of clock cycles. The detector is described in [3].

The phase detector 1 (Fig. 1) contains a detector 2 and a bipolar signal shaper, the first P and second N outputs of detector 2 being connected to the inputs of the bipolar signal shaper (sources 121, 122 and keys. 131, 132), and the inputs of detector 2 are connected in pairs respectively, with the inputs of the reference frequency Fo and clocks Fc, it additionally contains three D-flip-flops 141, 142 and 143, two elements AND 144 and 145, element OR 146, counter 147, code converter 148 and digital-to-analog converter 149, clock input Fc is connected with C-inputs of three D-flip-flops and counter 147, reference input frequency F is connected to the D-input of the first trigger 141 and the input of the first AND 144 element, the output of the first AND 144 element is connected to the input of the OR element 146, the output of the first D-trigger 141 is connected to the D-input of the second D-trigger 142, the output of which is connected with the input of the second element And 145 and with the D-input of the third D-flip-flop 143, the inverse output of which is connected to other inputs of the first and second elements And 144 and 145, the output of the second element And 145 is connected to the reset input of the counter 147, the transfer output of the counter 147 is connected with another input of the OR element 146, the output of which is connected n with the CE input of the counter 147, the outputs of which are connected in pairs, respectively, with the inputs of the code converter 148, the outputs of which are connected in pairs, respectively, with the inputs of the digital-to-analog converter 149, the output of which is connected to the control input of the bipolar signal generator.

The C-inputs of the first 141, the third 143 D-flip-flops, and the counter 147 are inverse, and the C-input of the second D-flip-flop 142 is direct.

The counter 147 counts the edges of the clock, and the signals at its outputs are switched by the cut of the clock. When the counter 147 overflows with the CE input, it stops and the counter is switched off to “0” (until the input R is reset). Converter 148 can be made in the form of read-only memory (ROM) or as a logical (combinational) converter.

The capacity of the counter 147 should be at least 6. The phase detector (Fig. 1) can work with different detectors and centers of the holding zones. At a different polarity (coding of logic levels) for the C-inputs of the counter and triggers (including detector 2), the centers of the holding zones are shifted by π.

Thus, the method and the phase detector according to the proposal are stable at high speed.

Sources of information

1. Patent US 6421404, CL 375/354, July 16, 2002

2. RF patent 2622628, IPC H03D 13/00, 03/03/2016

3. RF patent 2665241, IPC H03D 13/00, 10/13/2017

4. Greben A.B. Design of analog integrated circuits, trans. from English M., "Energy" 1976

Claims (5)

1. A method for adjusting the clock frequency along the edges of the data, in which the signals at the first and second outputs of the detector control the connection of the first and second bipolar signals for summing, the bipolar signals are summed, filtered, the generator frequency is controlled by the received signal, the generator frequency is divided and clock cycles are formed, and the first output of the detector generates a signal from the data front to the next clock edge, and if the data front arrives later than the center of the hold zone, the data front arrives later than the center of the zone hold, then after the end of the signal at the first output of the detector, a signal is generated at the second output of the detector, a signal from the clock edge to the slice of the clocks, characterized in that the number of clock edges that have passed after the receipt of the previous data edge is counted, and in the control area with an increase in the number of counted edges the amplitudes of the first and second bipolar signals are reduced. 2. The method according to p. 1, characterized in that a fixed ratio of the amplitude of the first bipolar signal to the amplitude of the second bipolar signal is established, this ratio is preserved when the amplitudes of the bipolar signals change, after the signal ends, the signal from the front is always generated at the first output of the detector at the second output of the detector measures to the cut of measures. 3. The method according to p. 2, characterized in that the ratio of the amplitude of the first bipolar signal to the amplitude of the second bipolar signal is two. 4. A phase detector comprising a detector and a bipolar signal generator, wherein the first and second detector outputs are connected to the inputs of the bipolar signal generator, and the detector inputs are connected in pairs with the reference frequency input and the clock input, characterized in that it further comprises three D-flip-flops, two AND elements, OR element, counter, code converter and digital-to-analog converter, moreover, the clock input is connected to the C-inputs, three D-flip-flops and a counter, the reference frequency input is connected to the D-input of the first of the second D-trigger and the input of the first element AND, the output of the first element And is connected to the input of the OR element, the output of the first D-trigger is connected to the D-input of the second D-trigger, the output of which is connected to the input of the second element And and with the D-input of the third D -trigger, whose inverse output is connected to other inputs of the first and second elements AND, the output of the second element And is connected to the counter reset input, the counter transfer output is connected to another input of the OR element, the output of which is connected to the CE input of the counter, the outputs of which are connected in pairs with the inputs of the code converter, the outputs of which are connected in pairs, respectively, with the inputs of the digital-to-analog converter, the output of which is connected to the control input of the bipolar signal generator. 5. The phase detector according to claim 4, characterized in that the C-inputs of the counter, the first and third D-flip-flops are inverse, and the C-input of the second D-flip-flop is direct.

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