RU2703493C1 - Method of localization of short-circuit faults of outputs of microcircuit chips jtag by interface and device for its implementation - Google Patents

Abstract

FIELD: electronic equipment.

SUBSTANCE: invention relates to production and diagnostics of highly integrated electronic modules in aircraft and space industry. Proposed device comprises personal computer with software connected via JTAG controller to JTAG interface of tested electronic module and contactless current sensor in the form of magnetic field converter to electric signal connected to inputs of non-inverting and inverting amplifiers. Output of the non-inverting amplifier through the first diode and the output of the inverting amplifier through the second diode are connected to the load resistance, to the input of the electronic switch and to the second input of the voltage comparator. Output of the electronic switch is connected to the analogue memory input, the output of which is connected to the resistive voltage divider by the middle point connected to the first input of the voltage comparator. Electronic switch control inputs, sampling and storage circuits, voltage comparator output and device activation button are connected to the appropriate JTAG cells of the microcircuit. JTAG interface of the microcircuit chip is connected to the JTAG interface of the entire device.

EFFECT: localization of short-circuit faults between outputs of JTAG chips connected in parallel to the information bus, high reliability of results of the localization process and its complete automation.

5 cl, 6 dwg, 4 tbl

Description

The present invention is intended to localize short circuit defects between the terminals of microcircuits with JTAG (Joint Test Action Group) interface, connected in parallel to the information bus in the production of highly integrated electronic modules in aviation and space.

Electronic modules in aviation and astronautics to increase the reliability of operation are performed in the form of several parallel working channels of the same type for converting and processing information, providing “hot standby”. The functionality of such channels is implemented on ultra-large integrated circuits (VLSI), most often implemented in BGA (Ball Grid Array) cases. Software configuration VLSI after the module is manufactured is usually performed through the JTAG interface described in the IEEE 1149.1 standard (IEEE Std 1149.1-2001 IEEE Standard Test Access Port and Boundary-Scan Atchitecture).

An example of a hot-standby electronic module in the form of a parallel three-channel structure on three integrated circuits (IMS1-IMS3) with an information bus is shown in FIG. one.

During the automated soldering of microcircuits in the BGA cases, short-circuit defects (short circuits) can occur between their terminals located in the subcircuit space of the microcircuits (Fig. 1), that is, in the zone of physical inaccessibility. To eliminate these defects due to the unknown location of faults under specific microcircuit cases, all microcircuits are removed from the board, which significantly increases the percentage of defects, the cost and time of repair of electronic modules.

The JTAG interface, in addition to performing the function of programming microcircuits, can be used to search for various defects in the communication lines of information buses, for example, by the method of boundary (peripheral) scanning (GS) (Testing and testable design. A. Gorodetsky. Components and technologies. No. 2, 2009 p. 6-7.).

The result of a defect search by the HS method in the form of detecting pairs of communication lines (LS): LS2-LS3, LS3-LS4 and LS2-LS4 in the information bus, between which a short circuit defect is detected, is shown in FIG. 1 - Three-channel structure of the electronic module with the information bus.

However, the application of the GS method does not allow us to determine between the terminals of which particular microcircuit that is parallelly connected to the communication lines of the information bus with other microcircuits, there is a short circuit defect. This leads to unjustified expenses of time and money in eliminating soldering defects, since all microcircuits, including those without short-circuit defects, are removed from the board.

Various techniques are known in the art for localizing faults of the type KZ in communication lines. For example, in devices for detecting short circuits in electrical circuits Toneohm 950 (Polar Toneohm Model 950. http://www.sovtest.ru/sites/default/files/Polar950.pdf) and Toneohm 970 (Toneohm 970. http: / / www, polarinstruments.com / products / toneohm / toneohm970.html) from Polar Instrument (Great Britain) uses a highly sensitive milliometer with vector support for finding the location of the defect. Power is supplied to the area of the alleged location of the fault defect on the board and the dependence of current changes when the probe is moved on the board is monitored. Search is provided by three pointers: digital, sound and vector. The digital indicator shows the current value, the sound indicator changes the tone as it approaches the defect, and the vector indicator indicates the direction of movement of the test probe.

The disadvantages of this method of determining the location of a fault defect are:

- the need for physical contact of the elements of the device with the conductors of the board having a protective coating when connecting an external test source or probes of a microvoltmeter. Connection to circuit elements may not be possible on boards with a high density of installation and minimum dimensions of conductors;

- the use of a human operator in the process of finding a defect, increasing the time and cost of diagnosis.

In the method for determining the location of a short-circuit defect (Copyright certificate No. 941910, class G01R 31/02, 1982), the main information source is a voltage sensor that detects the voltage drop in the sections of the communication line during serial switching along the communication line of the current source with the current sensor .

The disadvantage of this method for determining the location of a fault fault is the need to use a microvolt level voltage sensor to determine the voltage drop on the conductors of a printed circuit board with a length of 5-10 mm and the need to connect it to areas of printed conductors having a surface protective coating. In addition, to identify the location of several short-circuit defects in the communication line, it is necessary to eliminate the previously detected defect, which slows down and complicates the diagnostic process.

The short-circuit fault localization method (Author's certificate No. 1041963 A, class G01R 31/02, 1983) uses two current sensors that are mechanically rigidly interconnected and four voltage generators connected to the conductors of the printed circuit board. The presence of two connected current sensors and the connection of 4 pulse voltage generators to the conductors of the printed circuit board requires sufficient space on the printed circuit board, which may not be present during the installation of high density. In addition, in this method it is impossible to localize several short-circuit defects, since this will create a zone with no current in the communication line between two short-circuit defects, which will lead to disruption of the algorithm.

The closest technical solution (prototype) is the device and method described in (Patent No. US 20080215942 A1, United States, 2008). The essence of the method for localizing short-circuit defects between the terminals of microcircuits described in the patent is to use the method of boundary (peripheral) scanning. The interface built into the microcircuit by the JTAG manufacturer allows the use of microcircuit pins as sources and receivers of test signals.

The diagnostic complex of the device (prototype) consists of a test board connected via a USB controller (Universal Serial Bus) / JTAG interface to a control computer with software containing: diagnostic component models (Boundary Scan Description Language (BSDL) files); interconnect file (net-list); a program for generating and analyzing test suites, built-in user scripts (script), and a driver for the JTAG interface controller.

The description of the prototype patent (tables 1 and 2) provides algorithms for determining a short circuit between the terminals of microcircuits without the use of additional measuring equipment based on the analysis of test responses of the tested circuit.

The disadvantage of the method for determining short circuit defects proposed in the prototype patent is the impossibility of accurately localizing a fault defect between the terminals of several specific microcircuits connected in parallel to communication lines. This leads to unjustified loss of funds and time when performing operations to eliminate identified short-circuit defects.

The aim of the proposed method is the localization of short circuit defects of the terminals of integrated circuits with a JTAG interface connected in parallel to the communication lines of the information buses of highly integrated electronic modules.

The goal is achieved due to the fact that: the boundary scanning method is used to identify pairs of communication lines in the data bus with parallel-connected microcircuits that have a short circuit defect (in Fig. 1, pairs of communication lines LS2-LS3, LS3-LS4 and LS2-LS4 )

In addition, two communication lines — a first and a second communication line in which a short-circuit defect is detected, for example, the communication lines LS2 and LS3 in FIG. one.

The essence of the technical solution is illustrated by the following drawing:

In FIG. 1 shows a three-channel structure of an electronic module with an information bus;

in FIG. 2 shows the first and second communication lines with connected JTAG cells "n" chips;

in FIG. 3 presents an equivalent circuit for calculating currents in the conductors of the first drug;

in FIG. 4 shows equivalent circuits for calculating currents in the conductors of the left boundary (A) and the right boundary (B) of the first communication line;

in FIG. 5 shows a block diagram of a device for implementing a method for localizing fault defects of terminals of JTAG microcircuits;

in FIG. 6 is a functional diagram of a non-contact current sensor.

In FIG. Figure 2 separately shows the first and second communication lines of the information bus to which the terminals “n” of the IC (1) -IMC (n) microcircuits are connected in parallel through the JTAG cells. The microcircuits are connected to the first and second drugs via the JTAG built-in cells of the boundary scan register: C ₁₁ / C _1,2 - IC (1) ... C _{n, 1} / C _{n, 2} - IC (n). The first JTAG cell index indicates the number of the IC connected to the LAN, the second JTAG cell index indicates the number of the LAN (first or second LAN). As an example, in FIG. 2 shows the presence of short-circuit defects between the terminals 2.1 / 2.2 - IC (2); between the terminals n-1,1 / n-1,2 - IC (n-1); between the terminals n, 1 / n, 2-IC (n).

All JTAG cells of the terminals of microcircuits connected to communication lines with detected short-circuit defects are turned off by transferring them to the high-impedance state (Z).

Arbitrarily choose three adjacent chips with a JTAG interface, the conclusions of which are connected to the first and second communication lines of the information bus. In FIG. 2 shows randomly selected three adjacent chips: IC (i-1); IMS (i) and IMS (i + 1).

JTAG cell C _{i, 2 of the} middle of the three selected microcircuits connected to the second LAN is set to a logical zero state; JTAG cell of the selected three microcircuits connected to the first communication line - C _i-1,1 ; C _{i, 1} ; C _{i + 1,1} stimulate with test sets of the form: ZZ1; Z1Z; Z11; 1ZZ; 11Z; 111. In the test set, the JTAG cell state is turned off; the Z symbol corresponds to it; the logical unit state of the JTAG cell corresponds to the symbol 1. In total, six test sets are formed, excluding the ZZZ test set. As a result of stimulation, a test with sets of three JTAG cells of the selected three microcircuits in the areas of the first drug, between the microcircuits IC (i-1) / IC (i) and IC (i) IC (i + 1) currents I _i-1,1 will flow; I _i , ₁ (Fig. 2) for specific test kits.

An equivalent circuit for calculating the currents in the conductors of the first LAN is shown in FIG. 3

The JTAG cell in the logical “1” state is represented on the equivalent circuit by the voltage source E, the internal resistance of the drivers R ₀ and the position of the closed key “1” (Fig. 3). The JTAG cell in the logical “0” state is represented by the internal resistance of the drivers R ₀ and the key position “0”. JTAG cells disconnected from the drug in the high-impedance state Z are represented by open keys in the “Z” position (Fig. 3).

In the equivalent circuit (Fig. 3), for simplicity, the equality of currents is accepted: I ₁ = I _i-1,1 ; current I ₂ = I _{i, 1} .

Ammeters A1 and A2 measure the currents I ₁ and I _2, respectively, and have zero internal resistance, simulating the operation of a non-contact current meter.

Table 1 shows the values of the normalized currents I ₁ / I _MAX and I ₂ / I _MAX in the conductors of the first communication line, provided that there is no short-circuit defect between the terminals of the IC (i) (JTAG cell C _{i, 2 is} set to logic 0). The maximum current I _MAX is determined from the condition of the current flowing between neighboring cells of the first drug in the logical “1” and logical “0” states, respectively (for example, between C _i-1,1 and C _{i, 1} ):

Table 2 shows the normalized values of currents I ₁ / I _MAX and I _MAX in the conductors of the first communication line, provided that there is a fault between the terminals of the IC (i) (JTAG cell C _{i, 2} = 0).

According to the obtained values of the currents, the control number K is calculated for all combinations of the state of the outputs of the three selected microcircuits (tables No. 1 and No. 2):

N = 1 ... 7 - the number of the test set (table No. 1, No. 2);

X ₁ , X ₂ - logical variables for normalized currents I ₁ / I _MAX and

I ₂ / I _MAX, respectively;

The values of the control numbers K given in tables No. 1 and No. 2 are calculated by the formula (2) taking into account the conditions (3).

Determine the presence of a short circuit defect between the terminals "i, 1" and "i, 2" (Fig. 2, 3) of the central IC (i) from the equality of the control number K = 945.

Equivalent schemes for calculating the currents in the conductors of the left I _LG and right I _{PG of the} boundaries of the first LS (Fig. 2) are shown in Fig. 4A and 4B, respectively.

Table 3 shows the normalized values of currents I _LG / I _MAX in the left boundary wire of the first communication line for all options for the presence of short-circuit defects between the terminals of the IC (1) and the IC (2); JTAG cell C _{1,2 is} set to logical “0”.

Table 4 shows the normalized values of the currents I _PG / I _MAX in the right boundary wire of the first communication line for all variants of the presence of short-circuit defects between the terminals of the IC (n-1) and IC (n); JTAG cell C _{n, 2 is} set to logical "0".

The control number K _LG for the currents of the left boundary of the first drug are calculated from the expression:

The control number K _GH for currents of the right boundary of the first drug are calculated from the expression:

N = 1 ... 7 - number of the test set (table No. 3, No. 4);

X _LG , X _PG - logical variables for normalized currents I _LG / I _MAX and I _PG / I _MAX, respectively;

Determine the presence of a short circuit defect between the terminals of the IC (1) installed on the left border of the drug from the equality of the control number K _LG = 1260.

Determine the presence of a short circuit defect between the terminals of the integrated circuit (n) installed on the right border of the drug from the equality of the control number K _PG = 5040.

The presence or absence of currents in the conductors of the first drug is determined in a non-contact way using transducers, the magnetic field H, excited by the current flowing in the conductor into an electrical signal.

In order to increase the reliability of fault defects localization, the following is carried out: preliminary identification of the current detection location on the first communication line in the areas of the first LAN and the choice of the threshold level then corresponding to the current flow in the conductor.

The identification of the current detection location on the first communication line is carried out by sequential formation of the logical “1” and logical “0” levels in two JTAG cells of adjacent microcircuits connected to the first LAN. Formation begins with JTAG cells C _1,1 and C _2,1 (Fig. 2), setting cell C _1,1 state logical "1", cell C _2,1 - in the state logical "0". All other JTAG cells are in a high impedance state (Z). As a result of this, a current of amplitude I _MAX will flow between the IC (1) and the IC (2) in the area of the first drug, the value of which is determined from expression (1). Scanning of the following sections of the first drug with I _MAX current is carried out by sequential selection of stimulated JTAG cells along the first drug: C _2.1 ("1") / C _3.1 ("0"), the remaining cells are in the off state "Z". The last stimulated cells in the first drug: C _n-1 , ₁ ("1") and C _{n, 1} ("0") (Fig. 2). In the process of sequential scanning of the first drug, the output signal in the form of a logical “1” will appear at the time when the JTAG cells of two adjacent chips are stimulated, between which a non-contact method for determining the presence of current in the conductor is carried out.

The threshold level corresponding to the current flow in the conductor of the first drug is determined by storing the voltage U _MAX proportional to the maximum current I _MAX flowing in the conductor in the area of the first drug, at which its presence is currently determined. The threshold voltage value U ₀ in accordance with the conditions (3) and (6) is formed by quadrupling the voltage U _MAX :

S _BDT is the coupling coefficient between the current in the conductor I _MAX and the voltage U _MAX in a non-contact method for determining the presence of current.

Determination of the threshold level of the presence of current in the drug allows you to reduce the influence of destabilizing factors on the result of determining the current in the conductor in the form of instability of the mutual position of the conductors and converters the magnetic field into an electric signal.

The consistent application of the algorithm, consisting of locating a non-contact current indication method, calibrating the threshold level corresponding to the presence of current in the conductor and determining the presence of currents in the conductors between JTAG-stimulated cells of three adjacent circuits, followed by calculation of control numbers and their comparison with reference values for each microcircuit connected to the first and second drugs, determine the presence or absence of short-circuit defects of the terminals for each tested m kroskhemy first and second drugs.

The successive application of the algorithm for the localization of short circuit defects of the terminals of all microcircuits connected to the first and second communication lines of the information bus determines the presence or absence of a short circuit defect between the terminals of all microcircuits connected to all communication lines of the information bus between which short circuit defects were previously detected.

To implement the proposed method for the localization of short circuit defects of the terminals of microcircuits with a JTAG interface into a known device (Patent No. US 20080215942 A1, United States, 2008) containing (Fig. 5): personal computer 1 (PC), with installed software 2, including: diagnostic component models (BSDL files); inter-component communications file (net-list), test suite generation and analysis program (Test software), built-in user scripts (scripts), connected via JTAG controller 3 to JTAG interface 4 of the tested electronic module 5 with information bus 6, in order to determine the presence of currents in the conductors of the communication lines of the information bus 6, a non-contact current sensor 7 is introduced (Fig. 5). The contactless current sensor (BDT) 7 is connected via a magnetic field H to the current I flowing in the conductors of the information bus 6. The contactless current sensor 7 is connected to the personal computer 1 via the JTAG 4 interface via the JTAG interface controller 3.

The non-contact current sensor 7 of the fault location device between the terminals of the JTAG microcircuits (Fig. 5) is made in the form (Fig. 6): a magnetic field transducer into an electric signal 8, non-inverting 9 and inverting 10 voltage amplifiers; the first 11 and second 12 diodes, an electronic switch 13, a load resistance R3, a sampling and storage circuit (TSW) 14, a voltage divider 15 on resistors R1 and R2, a voltage comparator 16, a chip with a JTAG interface 17, and an activation button for the device 18.

The magnetic field to electric signal converter 8 is based on one of the physical effects: induction, Hall effect, magnetoresistive or giant magnetoresistive effect Giant Magneto-Resistive (GMR) (Baranochnikov ML Micromagnetoelectronics. T. 1. - M: DMK Press, 2001 .-- 544 pp. Ill.).

The output of the converter 8 is connected to the inputs of a non-inverting 9 and inverting 10 amplifiers. The outputs of the non-inverting amplifier 9 through the first diode 11 and the output of the inverting amplifier 10 through the second diode 12 are connected to the load resistance R3, to the input of the electronic key 13 and the second input (input 2) of the voltage comparator 16. The output of the electronic key 13 is connected to the input of the analog memory - sample circuit and storage (TSW) 14, the output of which is connected to a resistive voltage divider 15 at resistances R1 and R2. The midpoint of the voltage divider 15 is connected to the first input (input 1) of the voltage comparator 16. The activation button of the device 18 is connected with one terminal to the ground bus, the other terminal through the resistor R4 to the positive voltage source and to the JTAG cell "e" of the microcircuit 17. Electronic control inputs the key 13, the sampling and storage circuits 14 and the output of the voltage comparator 16 are connected to the corresponding JTAG cells "d", "c", "b" and "a" of the microcircuit 17. The JTAG interface of the microcircuit 17 is connected to the JTAG interface 4 of the entire device (Fig 5 )

Using an inverting amplifier 10, the first 11, and the second 12 diodes makes it possible to make the BDT circuit insensitive to the direction of the current in the drug wire, that is, to ignore the signs of currents (tables No. 1-4) in formulas (2), (4), (5) to calculate the corresponding control numbers.

The load resistance value R3 is chosen equal to the resistance value R2. In this case, in the absence of current in the LAN wire, the voltage across resistors R2 and R3 is equal to zero and the output voltage of the comparator 16 takes a logical zero value corresponding to the absence of current in the conductor of the first LAN.

The operation cycles of the BDT 7 through the JTAG interface 4 of the device are controlled by the user program “script” (Fig. 3), integrated into the software package 2 of the control computer 1. This allows you to synchronize the JTAG stimulation processes of the cells of the tested chips of the electronic module 5 and the operation of the non-contact current sensor 7 (Fig. . 5).

Contactless current sensor 7 (Fig. 6) works as follows.

In the initial state, the activation button of the device 18 is open and the JTAG cell “e” of the microcircuit 17 reads logical “1”, which puts the PC 1 of the device into standby mode. In this mode, the BDT 7 is installed on a selected section of the first LAN between two ICs. The output voltage of the voltage comparator 16 due to the lack of stimulation of JTAG cells and currents in the conductors of the first LAN corresponds to a logical "0".

When the JTAG button 18 closes, the cell “e” of the microcircuit 17 reads the value of the logical “0” in PC 1, and activates the operation of the fault defect localization program “script”.

In the mode "Location identification and calibration of the threshold level of BDT" signals JTAG cells "d" and "c" of the chip 17 (Fig. 6) is the opening of the electronic key 13 and zeroing the output voltage of the TSW 14. In this case, the program is run "script", which sequentially generates pairs of logical signals "1" and "0" for all JTAG cells connected to the first LAN (Fig. 2).

When stimulating the next pair of JTAG cells between the microcircuits of which the BDT is installed (for example, between the IC (i) and the IC (i + 1) - Fig. 2), at the output of the magnetic field to electric signal 8 converter, at the output of the non-inverting amplifier 9 and input 2 of the voltage comparator 16 appears a voltage of positive polarity corresponding to the positive direction of the current from the JTAG cell C _{i, 1} to the cell C _{i + 1,1} (Fig. 2). Since the voltage at input 1 of the comparator 16 is zero, its output voltage will take a logical value of “1”, which will be read through JTAG cell “a” of the microcircuit 17 in PC 1.

Thus, by the coincidence of the time of occurrence of the logical “1” at the output of the comparator 16 and the numbers of the JTAG cells currently stimulated, the exact location of the BDT 7 between the microcircuits connected to the first LAN is determined.

When the logical signal “1” is read out at the output of the comparator 16 by the script program in the JTAG cell “d” of the microcircuit 17, the key 13 closure signal is generated, and in the cell “b” - the voltage recording signal from the output of the non-inverting amplifier 9 to the analog memory - TSW 14 The voltage U _CBX at the output of the TSW 14 (Fig. 6) is proportional to the maximum current I _MAX in the conductor of the first LAN in accordance with (7). The voltage divider 15 generates a threshold voltage U ₁ = 0.25 * U _CBX on the resistor R2 in accordance with conditions (3) and (6). The threshold voltage U ₁ will be maintained by the TSW 14 during the entire cycle of formation of test sets to determine the presence or absence of currents in the conductor of the first LAN in the mode of fault defect localization. Thus, the calibration of the threshold level U ₁ BDT 7.

In the “Local fault defects localization” mode, the electronic key 13 is opened with the JTAG signal from cell “d” and the script program on PC 1 sequentially generates test sets for JTAG cells (according to tables Nos. 1–4) in the selected three adjacent ICs, connected to the first LAN (Fig. 2). For the positive direction of the current from the IC (i) to the IC (i + 1), a positive voltage is generated at the output of the non-inverting amplifier 9. For the reverse direction of the current, a positive voltage is generated at the output of the inverting amplifier 10. Negative voltages at the outputs of the amplifiers 9 and 10 are cut off by the corresponding diodes 11 and 12. Thus, in the short-circuit fault localization mode, only a positive voltage is supplied to the second input (input 2) of the voltage comparator 16, regardless of the direction of the current in the conductor of the first LAN. If the voltage at the second input (input 2) of the voltage comparator 16 will be greater than the reference voltage U ₁ at its first input (input 1), then a logical “1” voltage corresponding to the presence of current in the controlled conductor is generated at the output of the comparator 16, if less , at the output of the comparator 16 a logical “0” voltage is generated, corresponding to the absence of current in the monitored conductor. The output voltages of the comparator 16 are read through JTAG cell "a" of the microcircuit 17 in PC 1 and are used by the script program to calculate the control numbers K, K _LG and K _PG (tables No. 1-4) according to formulas (2), (4) and (5).

For the IC chip (1) (Fig. 2) of the electronic module 4 (Fig. 5), located on the left border of the drug, the calculation of the control number K _LG is performed only for the position of the BDT 7 between the IC (1) and the IC (2). The equality of the control number K _{LH to a} reference value of 1260 indicates the presence of a short-circuit defect between the terminals of the IMS (1).

For the IC chip (n) (Fig. 2) of the electronic module 4 (Fig. 5) located on the right border of the drug, the calculation of the control number K of the _{steam generator} is performed only for the position of the BDT 7 between the IC (n-1) and the IC (n) according to the formula (four). The equality of the control number K of the _{GHG to the} reference value of 5040 indicates the presence of a short-circuit defect between the terminals of the IC (n).

For ICs (2) -IMC (n-1) (Fig. 2) of the electronic module 4 (Fig. 5), the control number K is calculated for two positions of the BDT 7: between the IC (i-1) / IC (i) and between IMS (i) IMS (i + 1) according to the formula (2). The equality of the control number K to the reference value of 945 indicates the presence of a short-circuit defect between the terminals of the IC (i).

With subsequent changes in the position of the BDT 7 between the LS microcircuits, the button 18 opens and the execution of the script program stops.

After diagnosing all the microcircuits connected to the selected pair of drugs, test all the microcircuits connected to the remaining pairs of drugs on the information bus, between which short circuit defects were previously detected by the HS method.

1. The use of the proposed method for monitoring short-circuit defects between the terminals of JTAG microcircuits and devices for its implementation in the form of a set of distinctive features with respect to the known method (Patent No. US 20080215942 A1, United States, 2008) allows you to: localize short-circuit defects between physically inaccessible with the outputs of any number of microcircuits connected to communication lines of information buses, fully automate the process of localizing fault defects and ensure its high reliability, which allows IT significantly reduce costs in the production of highly expensive units of modern electronics.

Claims (5)

1. A method for localizing short circuit defects in the terminals of microcircuits with a JTAG interface connected to the information bus, which consists in generating test signals at the output of one JTAG cell connected through the output of the microcircuit to the communication line, receiving test signals by another JTAG cell connected through the output of the microcircuit to another communication lines and by the difference between the received test signal from the transmitted one, determine the presence of a short circuit defect between the terminals of the microcircuits, characterized in that all JTAG cells of the microcircuits connected to to the communication lines of the information bus, between which short-circuit defects were previously detected, they are turned off by transferring to the high-impedance state (Z), the first and second communication lines of the information bus with the previously detected short-circuit defect are randomly selected, three microcircuits are located at random, the terminals of which are connected to the first and second communication lines, a JTAG cell of the middle of the three microcircuits connected to the second communication line is set to a logical zero state; JTAG cells of the selected three microcircuits connected to the first communication line are stimulated with test sets (logical unit) of the following form: ZZ1; Z1Z; Z11; 1ZZ; 1Z1; 11Z; 111, then determine the presence or absence of currents in two conductors of the first communication line between the three selected microcircuits; calculate the control number as the sum of the products of the numbers of test sets (from 1 to 7) for non-zero current values of the two conductors of the first communication line and determine the presence of a short circuit defect between the terminals of the middle of the three selected circuits, provided that the obtained control number is equal to one of their three reference values. 2. The method according to p. 1, characterized in that they carry out preliminary identification of the location of the current on the first communication line, the choice of the threshold current level corresponding to the presence of current in the conductor by sequential pairwise generation of signals of high and low levels of JTAG cells in each of two adjacent microcircuits connected to the first communication line with all other switched off, transferred to the high-impedance state (Z), JTAG cells of microcircuits connected to the first and second communication lines. 3. The method according to p. 1, characterized in that the sequential application of the specified algorithm for localizing a short circuit defect between the terminals of one microcircuit determines the presence or absence of a short circuit defect between the terminals of all microcircuits connected to the first and second communication lines of the information bus. 4. The method according to p. 1, characterized in that the sequential application of the specified algorithm for localizing a short circuit defect between the terminals of all microcircuits of the first and second communication lines determines the presence or absence of a short circuit defect between the terminals of all microcircuits connected to all communication lines of the information bus, between which previously identified short circuit defects. 5. A device that implements a method comprising a personal computer with installed software, including: diagnostic component models (BSDL files); inter-component communication file (net-list), a program for generating and analyzing test sets, built-in user scripts (scripts), connected via the JTAG controller to the JTAG interface of the tested electronic module, characterized in that a non-contact current sensor connected via a magnetic field to conductors of communication lines and containing a magnetic field to electric signal converter, non-inverting and inverting amplifiers, first and second diodes, load resistance, electronic switch, sampling and storage circuit, a resistive voltage divider, a voltage comparator, a chip with a JTAG interface and a device activation button, while the output of the magnetic field to electric signal converter is connected in parallel to the amplifier inputs, the output of the non-inverting amplifier through the first diode and the output of the inverting amplifier through the second diode are connected to the load resistance R3, to the input of the electronic key and to the second input (input 2) of the voltage comparator, the output of the electronic key is connected to the input of the sampling and storage circuit, the output of which is connected to a resistive voltage divider at the resistances R1 and R2, the middle point of the voltage divider is connected to the first input (input 1) of the voltage comparator; control inputs of the electronic key, sampling and storage circuits, the device activation button and the voltage comparator output are connected to the corresponding JTAG cells of the microcircuit connected to the device's JTAG interface.

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