RU2699684C2 - Low voltage d-flip-flop with asynchronous value setting based on emitter-coupled logic - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: invention relates to the field of pulse technology. Low-voltage D-flip-flop is proposed, which consists of a single level of differential stages and resistors, forming a driving and driven triggers, synchronized in level. Driving and driven triggers consist of a pair of transistors with combined emitters of the first differential stage, amplifying the input signal, pairs of transistors with combined emitters of the second differential stage with positive feedback formed by connecting the base to the collector of the opposing transistor, allowing to hold the logic value reinforced by the first differential stage, and three resistors.

EFFECT: technical result consists in the possibility of applying the circuit at a supply voltage below 5 V, eliminating additional bias circuits of logical equations, reducing the input capacity of the reset output terminal RST or setting the stored SET value, reducing the input dependence of the forward CLK capacitance and the inverse input of the clock signal CLK, reducing the number of transistors used in the circuit.

1 cl, 3 dwg

Description

FIELD OF TECHNOLOGY

The invention relates to the field of pulse technology

BACKGROUND

From the existing level of technology it is known that for the implementation of phase-locked loop, it is necessary to use programmable frequency dividers, which are built on the basis of D-triggers with asynchronous setting of the stored value. The implementation of such triggers based on emitter-coupled logic allows you to get a high operating frequency. A circuitry is known for a D-trigger with asynchronous reset based on emitter-coupled logic, which is a two-stage structure based on two triggers synchronized in level, the so-called "Latches" with chains of reset or forced installation of the stored value. The latches consist of bipolar transistors, which together with the reset or set circuits form three levels of differential stages, which determine the current path in accordance with the logical voltage levels at the bases of the transistors and determine, respectively, the voltage levels at the output of the trigger US 5122682 A, 06.16.1992 . The disadvantages of this technical solution are: limitation of the possibility of using the circuit with a unipolar supply voltage below 5 V, due to the presence of three levels of differential cascades; high specific energy consumption due to the presence of additional bias circuits of logical voltage levels for the corresponding levels of differential stages, which leads to an additional signal delay during propagation in bias circuits.

Closest to the claimed technical solution is a D-flip-flop circuit with asynchronous reset and / or value setting based on emitter-coupled logic, which is a two-stage structure based on two “latch” triggers with reset circuits and / or setting the stored value, in which uses a single-level scheme US 7215170 B1, 8.05.2007. The implementation in the circuit of one level of differential cascades provides an active mode of operation of transistors with a typical unipolar supply voltage below 5 V up to 1.8 V, and this also eliminates additional bias circuits of logical voltage levels and related disadvantages. The disadvantage of this solution is: the excess number of transistors used in the circuit; low input impedance and high input capacitance of the reset output and / or setting the value due to the simultaneous connection of the output to the bases of four transistors; low input impedance and high input capacitance of the direct and inverse inputs of the clock signal due to the simultaneous connection of each output to the bases of four transistors.

SUMMARY OF THE INVENTION

The problem to which the invention is directed, is the creation of high-speed programmable frequency dividers with low energy consumption based on emitter-coupled logic.

This problem is solved due to the fact that the claimed low-voltage D-flip-flop with asynchronous reset is characterized by the fact that it consists of one level of differential stages and resistors forming master and slave triggers synchronized in level, which consist of:

pairs of transistors with combined emitters of the first differential stage amplifying the input signal;

pairs of transistors with combined emitters of the second differential cascade with positive feedback, formed by connecting the base to the collector of the opposite transistor, allowing to hold a logical value amplified by the first differential cascade;

three resistors, two of them are connected to the combined collectors of two transistors in one of the first and second differential stages, while the resistors are connected to the power bus through the third resistor.

подается на базу транзистора Т7. Эмиттер транзистора Т6 подключен к объединенным эмиттерам транзисторов второго дифференциального каскада ведущего триггера и к объединенным эмиттерам транзисторов первого дифференциального каскада ведомого триггера; коллектор транзистора Т6 подключен к шине питания; эмиттер транзистора Т7 подключен к объединенным эмиттерам транзисторов первого дифференциального каскада ведущего триггера и к объединенным эмиттерам транзисторов второго дифференциального каскада ведомого триггера; коллектор транзистора Т7 подключен к шине питания. Сигнал установки значения SET подается на базы двух транзисторов Т5 и Т8. Эмиттер транзистора Т5 подключен к объединенным эмиттерам транзисторов второго дифференциального каскада ведущего триггера и к объединенным эмиттерам транзисторов первого дифференциального каскада ведомого триггера; коллектор транзистора Т5 подключен к инверсному выходу ведущего триггера

; эмиттер транзистора Т8 подключен к объединенным эмиттерам транзисторов первого дифференциального каскада ведущего триггера и к объединенным эмиттерам транзисторов второго дифференциального каскада ведомого триггера; коллектор транзистора Т8 подключен к инверсному выходу ведомого триггера

.In this case, the combined emitters of the transistors of the first differential cascade of the master trigger are connected to the combined emitters of the transistors of the second differential cascade of the master trigger; the combined emitters of the transistors of the second differential stage of the master trigger are connected to the combined emitters of the transistors of the first differential stage of the slave trigger; the DC source I1 is connected to the combined emitters of the transistors of the first differential stage of the master trigger and the second differential stage of the slave trigger; the DC source I2 is connected to the combined emitters of the transistors of the second differential stage of the master trigger and the first differential stage of the slave trigger. The clock signal CLK is supplied to the base of the transistor T6, and the inverse clock signal

fed to the base of the transistor T7. The emitter of the transistor T6 is connected to the combined emitters of the transistors of the second differential stage of the master trigger and to the combined emitters of the transistors of the first differential stage of the slave trigger; the collector of the transistor T6 is connected to the power bus; the emitter of the transistor T7 is connected to the combined emitters of the transistors of the first differential stage of the master trigger and to the combined emitters of the transistors of the second differential stage of the slave trigger; the collector of the T7 transistor is connected to the power bus. The signal for setting the SET value is supplied to the bases of two transistors T5 and T8. The emitter of the transistor T5 is connected to the combined emitters of the transistors of the second differential cascade of the master trigger and to the combined emitters of the transistors of the first differential cascade of the slave trigger; the collector of the transistor T5 is connected to the inverse output of the master trigger

; the emitter of the transistor T8 is connected to the combined emitters of the transistors of the first differential stage of the master trigger and to the combined emitters of the transistors of the second differential stage of the slave trigger; the collector of the transistor T8 is connected to the inverse output of the slave trigger

.

The reset signal RST can be applied to the bases of two transistors T5 and T8, and it is necessary that: the emitter of the transistor T5 is connected to the combined emitters of the transistors of the second differential cascade of the master trigger and to the combined emitters of the transistors of the first differential cascade of the slave trigger; the collector of transistor T5 is connected to the direct output of the master trigger Z; the emitter of the transistor T8 is connected to the combined emitters of the transistors of the first differential stage of the master trigger and to the combined emitters of the transistors of the second differential stage of the slave trigger; the collector of the transistor T8 is connected to the direct output of the slave trigger Q.

, снижение количества используемых транзисторов в схеме.The technical result provided by the given set of features is the possibility of applying the circuit with a supply voltage below 5 V, eliminating additional bias circuits of logic levels, reducing the input capacitance of the reset output RST or setting the stored value SET, reducing the input capacitance of the direct CLK and the inverse clock input

, reducing the number of transistors used in the circuit.

The invention is illustrated by drawings, which depict:

In FIG. 1 is a circuit diagram of a low-voltage D-flip-flop with an asynchronous setting of a stored value;

In FIG. 2 is a circuit diagram of a low voltage D-flip-flop with asynchronous reset.

In FIG. 3 is a block diagram of a programmable frequency divider.

Low-voltage D-trigger with asynchronous reset, characterized in that it consists of one level of differential stages 3, 4, 5, 6 and resistors (R1, R2, R3, R4, R5, R6), which form the master 1 and slave 2 triggers synchronized by level, which consist of:

pairs of transistors T1, T2 (T9, T10) with combined emitters of the first differential stage 3 (5), amplifying the input signal;

pairs of transistors T3, T4 (T11, T12) with combined emitters of the second differential stage 4 (6) with positive feedback, formed by connecting the base to the collector of the opposite transistor, which allow holding the logic value amplified by the first differential stage;

three resistors R1, R3, R4 (R2, R5, R6), two of them R3, R4 (R5, R6) are connected to the combined collectors of two transistors through one of the first and second differential stages, while the resistors are connected to the power bus through the third resistor R1 (R2).

подается на базу транзистора Т7. Эмиттер транзистора Т6 подключен к объединенным эмиттерам транзисторов второго дифференциального каскада 4 ведущего триггера 1 и к объединенным эмиттерам транзисторов первого дифференциального каскада 5 ведомого триггера 2; коллектор транзистора Т6 подключен к шине питания; эмиттер транзистора Т7 подключен к объединенным эмиттерам транзисторов первого дифференциального каскада 3 ведущего триггера 1 и к объединенным эмиттерам транзисторов второго дифференциального каскада 6 ведомого триггера 2; коллектор транзистора Т7 подключен к шине питания. Сигнал установки значения SET подается на базы двух транзисторов Т5 и Т8. Эмиттер транзистора Т5 подключен к объединенным эмиттерам транзисторов второго дифференциального каскада 4 ведущего триггера 1 и к объединенным эмиттерам транзисторов первого дифференциального каскада 5 ведомого триггера 2; коллектор транзистора Т5 подключен к инверсному выходу ведущего триггера

; эмиттер транзистора Т8 подключен к объединенным эмиттерам транзисторов первого дифференциального каскада 3 ведущего триггера 1 и к объединенным эмиттерам транзисторов второго дифференциального каскада 6 ведомого триггера 2; коллектор транзистора Т8 подключен к инверсному выходу ведомого триггера

.In this case, the combined emitters of the transistors of the first differential stage 3 of the master trigger 1 are connected to the combined emitters of the transistors of the second differential stage 6 of the slave trigger 2; the combined emitters of the transistors of the second differential stage 4 of the master trigger 1 are connected to the combined emitters of the transistors of the first differential stage 5 of the slave trigger 2; a direct current source I1 is connected to the combined emitters of the transistors of the first differential stage 3 of the master trigger 1 and the second differential stage 6 of the slave trigger 2; the DC source I2 is connected to the combined emitters of the transistors of the second differential stage 4 of the master trigger 1 and the first differential stage 5 of the slave trigger 2. The clock signal CLK is supplied to the base of the transistor T6, and the inverse clock signal

fed to the base of the transistor T7. The emitter of the transistor T6 is connected to the combined emitters of the transistors of the second differential stage 4 of the master trigger 1 and to the combined emitters of the transistors of the first differential stage 5 of the slave trigger 2; the collector of the transistor T6 is connected to the power bus; the emitter of the transistor T7 is connected to the combined emitters of the transistors of the first differential stage 3 of the master trigger 1 and to the combined emitters of the transistors of the second differential stage 6 of the driven trigger 2; the collector of the T7 transistor is connected to the power bus. The signal for setting the SET value is supplied to the bases of two transistors T5 and T8. The emitter of the transistor T5 is connected to the combined emitters of the transistors of the second differential stage 4 of the master trigger 1 and to the combined emitters of the transistors of the first differential stage 5 of the slave trigger 2; the collector of the transistor T5 is connected to the inverse output of the master trigger

; the emitter of the transistor T8 is connected to the combined emitters of the transistors of the first differential stage 3 of the master trigger 1 and to the combined emitters of the transistors of the second differential stage 6 of the slave trigger 2; the collector of the transistor T8 is connected to the inverse output of the slave trigger

.

The reset signal RST can be supplied to the bases of two transistors T5 and T8, and it is necessary that: the emitter of the transistor T5 is connected to the combined emitters of the transistors of the second differential stage 4 of the master trigger 1 and to the combined emitters of the transistors of the first differential stage 5 of the slave trigger 2; the collector of transistor T5 is connected to the direct output of the master trigger Z; the emitter of the transistor T8 is connected to the combined emitters of the transistors of the first differential stage 3 of the master trigger 1 and to the combined emitters of the transistors of the second differential stage 6 of the slave trigger 2; the collector of the transistor T8 is connected to the direct output of the slave trigger Q.

The operation of the device is as follows.

обеспечивается отвод токов источников I1 и I2 на шину питания в обход активной части схемы за счет открытия одного из транзисторов Т6, Т7. Когда ток источника I1 шунтирован, ток источника 12 поровну делится между первым дифференциальным каскадом ведущего триггера и вторым дифференциальным каскадом ведомого триггера, затем при смене фазы синхроимпульса на 180 градусов происходит шунтирование тока источника I2 на шину питания, при этом ток источника I1 поровну делится между вторым дифференциальным каскадом ведущего триггера и первым дифференциальным каскадом ведомого триггера. Процесс захвата логического значения на дифференциальном входе D можно условно разделить на 3 этапа:When a paraphase clock arrives at the CLK inputs,

provides the removal of currents of sources I1 and I2 to the power bus bypassing the active part of the circuit due to the opening of one of the transistors T6, T7. When the current of source I1 is shunted, the current of source 12 is evenly divided between the first differential cascade of the master trigger and the second differential cascade of the slave trigger, then when the phase of the clock changes by 180 degrees, the current of source I2 is bypassed to the power bus, while the current of source I1 is equally divided between the second the differential cascade of the master trigger and the first differential cascade of the master trigger. The process of capturing a logical value at the differential input D can be divided into 3 stages:

установлен низкий логический уровень напряжения, ток источника I1 шунтирован на шину питания, ток источника I2 поровну разделен между первым дифференциальным каскадом ведущего триггера и вторым дифференциальным каскадом ведомого триггера. Обеспечивается усиление значения, установленного на информационном входе для его последующего сохранения в ведущем триггере;1) At the direct input of the CLK clock signal, a high logical voltage level is set, at the inverse input of the clock signal

a low logic voltage level is set, the current of the source I1 is shunted to the power bus, the current of the source I2 is evenly divided between the first differential cascade of the master trigger and the second differential cascade of the slave trigger. It provides amplification of the value set at the information input for its subsequent storage in the master trigger;

установлен высокий логический уровень напряжения, ток источника I2 шунтирован на шину питания, ток источника I1 поровну разделен между вторым дифференциальным каскадом ведущего триггера и первым дифференциальным каскадом ведомого триггера. За счет положительной обратной связи во втором дифференциальном каскаде ведущего триггера обеспечивается удержание захваченного значения на этапе 1), а за счет первого дифференциального каскада ведомого триггера производится усиление хранящегося значения для последующего сохранения в ведомом триггере.2) At the direct input of the CLK clock signal, a low logic voltage level is set, at the inverse input of the clock signal

a high logical voltage level is set, the current of the source I2 is shunted to the power bus, the current of the source I1 is evenly divided between the second differential cascade of the master trigger and the first differential cascade of the slave trigger. Due to the positive feedback in the second differential cascade of the master trigger, the captured value is held in step 1), and due to the first differential cascade of the master trigger, the stored value is amplified for subsequent storage in the master trigger.

установлен низкий логический уровень напряжения, ток источника I1 шунтирован на шину питания, ток источника I2 поровну разделен между первым дифференциальным каскадом ведущего триггера и вторым дифференциальным каскадом ведомого триггера. Обеспечивается усиление значения, установленного на информационном входе, на данном этапе, для его последующего сохранения в ведущем триггере и за счет положительной обратной связи во втором дифференциальном каскаде ведомого триггера обеспечивается удержание значения захваченного на этапе 1).3) At the direct input of the CLK clock signal, a high logical voltage level is set, at the inverse input of the clock signal

a low logic voltage level is set, the current of the source I1 is shunted to the power bus, the current of the source I2 is evenly divided between the first differential cascade of the master trigger and the second differential cascade of the slave trigger. The value set at the information input is amplified at this stage, for its subsequent storage in the master trigger and due to the positive feedback in the second differential stage of the slave trigger, the value captured at stage 1) is maintained.

в противофазе.The described steps continuously replace each other while there is a change of logic levels on the CLK pins,

in antiphase.

не менее чем на 150 мВ для шунтирования основной части токов источников. При этом, вне зависимости от сигналов на остальных входах D-триггера, обеспечивается асинхронная установка высокого логического уровня напряжения на выходе.When a high logical level of voltage is established at the SET terminal, the currents of sources I1 and I2 are shunted to the power bus through resistors R1, R3 and R2, R5, respectively, providing the necessary voltage drop and setting a logical unit at the outputs of the master and slave triggers. Since the emitters of the transistors T5, T6, T7, T8 are combined, the level of high logic voltage at the terminal SET must be greater than the high logical level of voltage at the terminals CLK,

not less than 150 mV for shunting the main part of the source currents. At the same time, regardless of the signals at the other inputs of the D-flip-flop, an asynchronous installation of a high logical output voltage level is provided.

The low-voltage D-flip-flop circuit with asynchronous setting of the stored value is made on the basis of one level of bipolar differential stages, which makes it possible to unipolar power the circuit with voltage below 5 V, while ensuring the active operation of transistors. This is due to the fact that when the supply voltage decreases, the moment comes when the potential on the collector becomes lower than the base potential, after which the transistor starts to work in saturation mode, therefore for circuits based on emitter-coupled logic, the relation Vsp> IR + NVbe + VI

where Vsp is the supply voltage;

IR - voltage drop across the resistors in the collector circuit;

N is the number of levels of bipolar differential cascades;

Vbe is the voltage of the open pn junction of the base-emitter of the transistor;

VI - minimum allowable voltage drop at the current source.

It can be seen from this relation that the minimum allowable supply voltage, at which the active operation mode of transistors is provided, is achievable only at N = 1, i.e. at one level of bipolar differential cascades.

The creation of a low-voltage D-trigger with asynchronous reset based on emitter-coupled logic provides maximum product performance due to the high cutoff frequency of bipolar transistors.

Thus, the claimed D-flip-flop circuit with asynchronous value setting allows you to successfully create high-speed programmable frequency dividers with low energy consumption based on emitter-coupled logic.

Claims (10)

A low-voltage D-trigger with asynchronous reset, characterized in that it consists of one level of differential stages and resistors, which form the master and slave triggers synchronized in level, which consist of: pairs of transistors with combined emitters of the first differential stage amplifying the input signal; pairs of transistors with combined emitters of the second differential cascade with positive feedback, formed by connecting the base to the collector of the opposite transistor, allowing to hold a logical value amplified by the first differential cascade; three resistors, two of them are connected to the combined collectors of two transistors in one of the first and second differential stages, while the resistors are connected to the power bus through the third resistor; a DC source I1 connected to the combined emitters of the transistors of the second differential cascade of the master trigger and the combined emitters of the transistors of the first differential cascade of the slave trigger; DC source I2 connected to the combined emitters of the transistors of the first differential stage of the master trigger and the combined emitters of the transistors of the second differential stage of the slave trigger; transistor T6, the emitter of which is connected to the combined emitters of the transistors of the second differential stage of the master trigger and to the combined emitters of the transistors of the first differential stage of the slave trigger, the collector of the transistor T6 is connected to the power bus, and the clock signal CLK is applied to the base; transistor T7, the emitter of which is connected to the combined emitters of the transistors of the first differential stage of the master trigger and to the combined emitters of the transistors of the second differential stage of the driven trigger, the collector of the transistor T7 is connected to the power bus, and the inverse clock signal is applied to the base

; transistor T5, the emitter of which is connected to the combined emitters of the transistors of the second differential cascade of the master trigger and to the combined emitters of the transistors of the first differential cascade of the master trigger, the collector of the transistor T5 is connected to the inverse output of the master trigger

and the SET signal is applied to the base of transistor T5 or the collector of transistor T5 is connected to the direct output of the master trigger Z, and the reset signal RST is sent to the base of transistor T5; transistor T8, the emitter of which is connected to the combined emitters of the transistors of the first differential stage of the master trigger and to the combined emitters of the transistors of the second differential stage of the slave trigger, the collector of the transistor T8 is connected to the inverse output of the slave trigger

and the SET signal is applied to the base of the transistor T8 or the collector of the transistor T8 is connected to the direct output of the slave trigger Q, and the reset signal RST is sent to the base of the transistor T8.

Images