RU2677363C1 - Reconfigurable computing system - Google Patents

Abstract

FIELD: computer equipment.SUBSTANCE: invention relates to the field of computing, in particular to reconfigurable high-performance computing systems of the cluster type. Reconfigurable computing system contains the EtherNet switch 1 of the computing system control, master server 2, interface board 5, group of K slave computing nodes (CN) 4, …, 4and PCI-Express 31 switchboard, each CN contains PCI-Express 11 switchboard, computer 8, a group of N state memories 9, …, 9and a group of N reconfigurable computing devices (RCD) 13, …, 13, each of which contains PCI-Express 19 switch, group of M computing FPGAs 20, …, 20, interface FPGA 22, a group of M computational VLSI 33, …, 33, with single rectangular radiator 27 installed above them, configuration and monitoring unit 23, memory of FPGA configurations 24, switch mode control unit 30, group of M memory configurations of FPGA 35, …, 35, a group of M individual monitoring units 15, …, 15and high-speed serial interfaces PCI-Express 10, 16, 17, 18, 21, 28, 29.EFFECT: technical result consists in increasing the computing power and reducing the power density of the power consumption of the computing system.1 cl, 1 dwg

Description

The invention relates to the field of computer technology, in particular to reconfigurable high-performance computing systems of a cluster type, designed to solve labor-intensive tasks, process large information arrays and streams using parallelization and pipelining of computing processes.

A reconfigurable cluster-type computing system is a set of slave computing nodes operating under the control of a master server, united by a communication environment. The communication environment provides interaction between the master server and the slave computing nodes, as well as directly between the slave computing nodes.

Computing nodes of reconfigurable cluster-type computing systems include a universal computing tool (computer), reconfigurable computing devices, interaction interfaces, and means for switching them.

Reconfigurable computing devices are those connected to the universal computing facility using an external PCI-Express I / O interface and operating under its control high-performance computers that contain FPGAs and specialized computing processors made on custom VLSI.

Reconfiguration is a process of changing interactions in a computer system programmatically, with the aim of organizing various schemes of sequential (conveyor), parallel and / or sequentially parallel data processing within a given group of computing tools, to implement the required processing algorithms.

FPGAs are programmable logic integrated circuits that incorporate a large number of logical and memory elements that can be dynamically programmed as devices designed to organize the required calculations, as well as to support the required interaction interfaces.

Custom VLSIs are specialized integrated circuits designed for circuitry implementation of specific labor-intensive algorithms for computationally complex variant problems of discrete mathematics.

Known reconfigurable computing module (RU No. 168565 U1, IPC G06F 15/177, announced 11/21/2016, published 02/08/2017), which can be used in reconfigurable computing units of multiprocessor computing systems, containing an external port for exchanging information, PCI-Express switch , interface and N computing FPGAs, each of which contains a high-speed serial PCI-Express interface, and the ports of the PCI-Express switch are connected to the external ports of the module and to the PCI-Express interfaces of the interface FPGA and N computing FPGAs , a group of N computational VLSIs, each VLSI of N computational VLSIs connected by individual bi-directional data buses to the corresponding computing FPGAs, an operational reconfiguration unit for memory starting configurations of computing FPGAs connected to the interface FPGAs, each FPGA from a group of N computing FPGAs connected to corresponding starting memories configurations of computing FPGAs, which are also interconnected with the operational reconfiguration bus and with the operational river block configuration memories of the starting configurations of the FPGAs, the power monitoring and control unit and the monitoring unit connected by bi-directional buses to the interface FPGA, the JTAG monitoring and control port and the interface FPGA configuration memory connected to the on-board FPGA configuration module, the interface FPGA connected by a bi-directional common bus to N computing FPGAs, each FPGA from the group N computing FPGAs and each VLSI from the group N computing VLSIs are connected by a bi-directional moni bus Oring with the monitoring unit, a synchronization unit coupled bidirectional bus interface to the FPGA, VLSI each group of N computers connected VLSI bus synchronization with the synchronization block.

The disadvantages of this module are the low average speed of information exchange of computing FPGAs on the external port and the uneven power consumption of the module, depending on the nature of the tasks it solves, when using this module in multi-user (multitasking) systems.

The reason that impedes the achievement of the technical result indicated below is the distribution of computing resources between users of reconfigurable computing systems built on the basis of modules, in which the minimum resource unit for the user is the computing module as a whole, consisting of N computing FPGAs and N computing VLSIs, which is associated with with a unified power management system, synchronization and operational reconfiguration of computing FPGAs, in which all computing submarines C and VLSI module can operate in the current time interval only over performing similar tasks that may require a high metabolic rate or high power consumption.

The closest computing system of the same purpose to the claimed invention, by the totality of features adopted as a prototype, is a reconfigurable computing system (RU No. 156778 U1, IPC G06F 15/16, announced April 10, 2015, published November 20, 2015 Bull. No. 32) containing a master server 2 connected via a network interface 3 to a control switch EtherNet 1 of a computer system, which is connected via a network interface EtherNet 7 ₁ , ..., 7 _K to a group of K slave computing nodes 4 ₁ , ..., 4 _K , each of which contains PCI-Express 11 switch, computer 8 and a group of N reconfigurable computing devices 13 ₁ , ..., 13 _N , each of which contains a PCI-Express 19 switch, a group of M computing FPGAs 20 ₁ , ..., 20 _M , an interface FPGA 22, a configuration and monitoring unit 23, a control unit PCI-Express 30 switch mode and FPGA configuration memory 24, with the interface FPGA 22 connected to the PCI-Express 30 switch mode control unit, FPGA configuration memory 24 and configuration and monitoring unit 23, which is connected to a common configuration and monitoring bus of computing FPGAs 25 groups th of the M computing FPGA 20 _1, ..., 20 _M, and PCI-Express 17 each switch PCI-Express 19 is connected to 30 PCI-Express switch mode control unit, the interface FPGA 22 over a high speed serial interface with computing FPGA 20 ₁ ..., 20 _M , via high-speed serial PCI-Express 21 ₁ , ..., 21 _M serial interfaces.

The disadvantage of this computing system is the low computing power with a relatively high power consumption when implementing laborious computational algorithms.

The reason that impedes the achievement of the technical result indicated below is that when implementing labor-intensive computational algorithms on computing FPGAs, there is a large percentage of overhead that reduces the efficiency of using computing resources, as well as low operating frequencies of operations, which is associated with the specifics of the internal structure of FPGAs on the basis of which this reconfigurable computing system is implemented.

The problem to which the invention is directed, is to create a high-performance reconfigurable computing system.

The technical result of the invention is to increase computing power and reduce the specific power consumption of a computer system.

To solve this problem, a reconfigurable computer system containing a master server 2 connected via a network interface 3 to an EtherNet 1 control switch of a computer system, which is also connected via EtherNet 7 ₁ , ..., 7 _K network interfaces to a group of K slave computing nodes 4 ₁ , ... , 4 _K , each of which contains a PCI-Express 11 switch, a computer 8 and a group of N reconfigurable computing devices 13 ₁ , ..., 13 _N , each of which contains a PCI-Express 19 switch, a group of M computing FPGAs 20 ₁ , ... , 20 _M , interface FPGA 22, block configuration and monitoring 23, the PCI-Express 30 switch mode control unit and the FPGA configuration memory 24, the interface FPGA 22 being connected to the PCI-Express 30 switch mode control unit, the FPGA configuration memory 24 and the configuration and monitoring unit 23, which is shared via the configuration bus monitoring and computing FPGA 25 is connected with the group of computing M FPGA 20 _1, ..., _M 20, and each PCI-Express switch 19 is connected to 30 PCI-Express switch mode control unit via the control bus 12, an interface 22 for high-speed Internet FPGAs -velocity PCI-Express serial interface 17 and to computing FPGA 20 _1, ..., 20 _M, at a high-speed serial interfaces are PCI-Express 21 _1, ..., 21 _M,

additionally introduced a two-port interface board 5, a PCI-Express switch 31 combining reconfigurable computing devices 13 ₁ , ..., 13 _N slave computing nodes 4 ₁ , ..., 4 _K , each of which contains a group of N state memories 9 ₁ , ..., 9 _N reconfigurable computing devices 13 ₁ , ..., 13 _N , each of which contains a group of M computing VLSI 33 ₁ , ..., 33 _M , a single rectangular radiator 27 mounted above the computing VLSI 33 ₁ , ..., 33 _M , a group of M individual monitoring and control units 15 _1, ..., 15 _M and the group M memories of starting configurations 35 _1, ..., 35 _M corresponding computing FPGA 20 _1, ..., 20 _M,

moreover, in each slave computing node 4 ₁ , ..., 4 _K, computer 8 is connected to the corresponding EtherNet 7 ₁ , ..., 7 _K network interface, connected to N state memories 9 ₁ , ..., 9 _N reconfigurable computing devices 13 ₁ , ..., 13 _N and is connected by a high-speed serial PCI-Express 10 interface to a PCI-Express 11 switch, which is a group of N high-speed serial PCI-Express 16 ₁ , ..., 16 _N ports connected to the NT / US ports of the corresponding PCI-Express 19 switches of a group of N reconfigurable computing devices 13 ₁ , ..., 13 _N , in each of which computing FPGAs 20 ₁ , ..., 20 _{M are} connected to the corresponding memories of the same name 35 ₁ , ..., 35 _M configurations of computing FPGAs on individual buses 36 ₁ , ..., 36 _M reconfiguration of computing FPGAs and on individual buses 32 ₁ , ..., 32 _M operational memory reconfiguration of start configurations, as well as connected to the same computing VLSI 33 ₁ , ..., 33 _M via individual communication buses 34 ₁ , ..., 34 _M and through individual monitoring control buses 26 ₁ , ..., 26 _M to individual monitoring units 15 ₁ , ..., 15 _M, which are connected to sootvets VLSI computing vuyuschim 33 _1, ..., 33 _M of the tire monitor 14 _1, ..., 14 _M,

in addition, the NT / DS / US ports of the PCI-Express switches 19 of the reconfigurable computing devices 13 ₁ , ..., 13 _{N are} connected to the corresponding interface from the group of N high-speed serial interfaces combining PCI-Express 28 ₁ , ..., 28 _N , which are combined in K groups 29 ₁ , ..., 29 _K over N high-speed serial interfaces combining PCI-Express slave computing devices 4 ₁ , ..., 4 _K and are connected to the corresponding DS ports of the PCI-Express 31 switch, whose US port is connected to the DS port of the dual-port interface board 5 for high speed sequencing PCI-Express 18 interface, and the US port of the dual-port interface board 5 is connected via a high-speed serial PCI-Express 6 interface to the master server 2.

In FIG. 1 shows a functional diagram of the proposed reconfigurable computing system.

In FIG. 1 and the following abbreviations are adopted in the text:

VU - computing node;

RVU - reconfigurable computing device;

IP - interface board with PCI-Express bus;

KP - a computer with a PCI-Express bus on the motherboard;

DS - output "transparent" port of the PCI-Express switch;

US - input "transparent" port of the PCI-Express switch;

NT - “non-transparent” port of the PCI-Express switch;

To - the number of slave WU computing system;

N is the number of reconfigurable computing devices in each slave slave;

M - the number of computing FPGAs and computing VLSI in each RVU;

i, j are counting variables.

1 - EtherNet control switch computing system;

2 - leading server computing system;

3 - EtherNet network interface between the EtherNet 1 management switch and master 2;

4 ₁ , ..., 4 _K - a group of them K slave WU;

5 - dual port interface board;

6 - high-speed serial PCI-Express interface between the leading server 2 and IP 5;

7 ₁ , ..., 7 _K - a group of K EtherNet network interfaces between the EtherNet 1 control switch and a group of K slave slaves 4 ₁ , ..., 4 _K ;

8 - computer slave WU 4 ₁ , ..., 4 _K ;

9 ₁ , ..., 9 _N is a group of N state memories of reconfigurable computing devices 13 ₁ , ..., 13 _N ;

10 - high-speed serial PCI-Express interface between KP 8 of the slave slave and switch 11;

11 - PCI-Express switch slave VU 4 ₁ , ..., 4 _K ;

12 - PCI-Express 19 switch mode control bus in reconfigurable computing devices 13 ₁ , ..., 13 _N ;

13 ₁ , ..., 13 _N - a group of N reconfigurable computing devices in the slave WU 4 ₁ , ..., 4 _K ;

14 ₁ , ..., 14 _M - a group of M buses for monitoring computer VLSI 31 ₁ , ..., 31 _M ;

15 ₁ , ..., 15 _M - a group of M individual monitoring units for computing VLSI 31 ₁ , ..., 31 _M ;

16 ₁ , ..., 16 _N - a group of N high-speed serial PCI-Express interfaces between the PCI-Express 11 switch and reconfigurable computing devices 13 ₁ , ..., 13 _N slave slaves;

17 - high-speed serial PCI-Express interface between the PCI-Express 19 switch and the FPGA interface 22 reconfigurable computing devices 13 ₁ , ..., 13 _N ;

18 - high-speed serial PCI-Express interface between IP 5 and the PCI-Express 31 switch;

19 - PCI-Express switchboard of reconfigurable computing devices 13 ₁ , ..., 13 _N ; 20 ₁ , ..., 20 _M - a group of M computing FPGAs of reconfigurable computing devices 13 ₁ , ..., 13 _N ;

21 ₁ , ..., 21 _M is a group of M high-speed serial PCI-Express interfaces between the PCI-Express 19 switch and computing FPGAs 20 ₁ , ..., 20 _M in reconfigurable computing devices 13 ₁ , ..., 13 _N ;

22 - interface FPGA reconfigurable computing devices 13 ₁ , ..., 13 _N ;

23 is a block configuration and monitoring reconfigurable computing devices 13 ₁ , ..., 13 _N ;

24 - memory configurations FPGA reconfigurable computing devices 13 ₁ , ..., 13 _N ;

25 - a common bus for configuring and monitoring computing FPGAs of reconfigurable computing devices 13 ₁ , ..., 13 _N ;

26 ₁ , ..., 26 _M - a group of M individual monitoring control buses;

27 - a single radiator of a rectangular shape mounted above the computing VLSI 33 ₁ , ..., 33 _M ;

28 ₁ , ..., 28 _N - a group of N high-speed serial PCI-Express interfaces combining reconfigurable computing devices 13 ₁ , ..., 13 _N ;

29 ₁ , ..., 29 _K - K groups of N high-speed serial interfaces for combining PCI-Express slaves WU 4 ₁ , ..., 4 _K ;

30 - control unit mode switch PCI-Express 19 in reconfigurable computing devices 13 ₁ , ..., 13 _N ;

31 - PCI-Express switch for combining reconfigurable computing devices 13 ₁ , ..., 13 _N slave computing nodes 4 ₁ , ..., 4 _K via high-speed serial PCI-Express interfaces;

32 ₁ , ..., 32 _M - a group of M individual buses for operational reconfiguration of the memory of the starting configurations of computing FPGAs 20 ₁ , ..., 20 _M ;

33 ₁ , ..., 33 _M - a group of M computing VLSI reconfigurable computing devices 13 ₁ , ..., 13 _N ;

34 ₁ , ..., 34 _M - a group of M individual data buses of the same name computing VLSI 33 ₁ , ..., 33 _M and computing FPGAs 20 ₁ , ..., 20 _M ;

35 ₁ , ..., 35 _M - a group of M memories of configurations of computing FPGAs 20 ₁ , ..., 20 _M in reconfigurable computing devices 13 ₁ , ..., 13 _N ;

36 ₁ , ..., 36 _M - a group of M individual buses for reconfiguration of computing FPGAs 20 ₁ , ..., 20 _M.

The proposed reconfigurable computer system comprises a master server 2, a two-port interface board 5, a group of K slave slaves 4 ₁ , ..., 4 _K , an EtherNet 1 switch for the control of the computer system, and a PCI-Express switch 31 combining reconfigurable computing devices of the slave nodes 4 ₁ , ... , 4 _K.

Each of the slave slaves 4 ₁ , ..., 4 _K contains a PC 8 computer with a PCI-Express 11 switch and a group of N state memories 9 ₁ , ..., 9 _N on the motherboard, as well as a group of N reconfigurable computing devices 13 ₁ , ... , 13 _N.

Each of N reconfigurable computing devices 13 ₁ , ..., 13 _N contains a PCI-Express 19 switch, a group of M computing FPGAs 20 ₁ , ..., 20 _M , a group of M computing VLSI 33 ₁ , ..., 33 _M , a single rectangular radiator 27, mounted over VLSI computing 33 ₁ , ..., 33 _M , interface FPGA 22, configuration and monitoring unit 23, PCI-Express 19 switch mode control unit 30, memory 24 FPGA configurations, a group of M individual monitoring and control units 15 ₁ , ..., 15 _M and a group of M memory starting configurations 35 ₁ , ..., 35 _M computing FPGA 20 ₁ , ..., 20 _M.

The master server 2 is intended for the organization of task flow control for the slave WU 4 ₁ , ..., 4 _K through the EtherNet 1 switch for controlling the computer system via the EtherNet 3 network interface, loading operating systems in KP 8 slave WU 4 ₁ , ..., 4 _K and for managing slaves WU 4 ₁ , ..., 4 _K for solving labor-intensive computational tasks, as well as for organizing monitoring of the state of technical means of a computing system, controlling turning on and off the power supply of KP 8 reconfigurable computing devices 13 ₁ , ..., 13 _N , collection and analysis telemetric information about the temperature and power modes of the slave VU 4 ₁ , ..., 4 _K.

The dual-port IP 5 is designed to ensure the interaction of the master server 2 via the high-speed serial interface PCI-Express 18 with the PCI-Express 31 switch, which is designed to ensure the interaction of both the master server 2 with the CP 8 of the slave VU 4 ₁ , ..., 4 _K , and control the interaction of KP 8 slave WU 4 ₁ , ..., 4 _K via high-speed serial PCI-Express 29 ₁ , ..., 29 _K interfaces.

The driven VU 4 ₁ , ..., 4 _K are designed for high-speed information processing and solving labor-intensive computational problems.

KP 8 slave WU 4 ₁ , ..., 4 _K are designed to control power on and off, organize the collection, analysis and recording in the corresponding state memory 9 ₁ , ..., 9 _M reconfigurable computing devices 13 ₁ , ..., 13 _N telemetric temperature information mode and a component supply mode, and control the organization configurable computing devices 13 _1, ..., 13 _N in the solution consuming computational problems and to provide data exchange between the master server 2 with both high-speed serial inter eysam PCI-Express 29 _1, ..., 29 _K, and on the EtherNet network through a switch 1.

The PCI-Express 11 switch is designed to provide interoperability via high-speed serial PCI-Express 16 ₁ , ..., 16 _N interfaces between reconfigurable computing devices 13 ₁ , ..., 13 _N and with gearbox 8 via the high-speed serial PCI-Express 10 interface.

Reconfigurable computing devices 13 ₁ , ..., 13 _N slave VU 4 ₁ , ..., 4 _K are intended for the direct solution of labor-intensive tasks and processing large information arrays and streams using parallelization and pipelining of computing processes.

The PCI-Express 19 switch of reconfigurable computing devices 13 ₁ , ..., 13 _{N is} designed to organize the exchange of interface FPGA 22 information via the high-speed serial PCI-Express 17 interface and computing FPGA 20 ₁ , ..., 20 _M via the high-speed serial PCI-Express 21 ₁ interfaces , ..., 21 _M between each other and via a high-speed serial interface PCI-Express 16 through a PCI-Express 11 switch with a gearbox of 8 slave slaves with a master server 2.

Computing FPGAs 20 ₁ , ..., 20 _M are designed for high-performance pre-processing of incoming input data, subsequent processing of the results of computational VLSI 33 ₁ , ..., 33 _M , as well as providing data and results exchange with computational VLSI 33 ₁ , ..., 33 _M on individual data exchange buses 34 ₁ , ..., 34 _M , with individual monitoring units 15 ₁ , ..., 15 _M , on individual monitoring control buses 26 ₁ , ..., 26 _M , control the power and adjust the operating frequencies of computational VLSI 33 ₁ , ... , 33 _M, wasp estvlyayut avtorekonfigurirovanie new program for individual tires the reconfiguration of 36 _1, ..., 36 _M by reprogramming from its own configuration memory 35 _1, ..., 35 _M. on individual tires 32 ₁ , ..., 32 _M.

Computational VLSI 33 ₁ , ..., 33 _M are intended for direct circuit implementation of critical sections of labor-intensive fragments of computational algorithms. Computational VLSI 33 ₁ , ..., 33 _M are implemented as custom VLSI to perform the required algorithms.

The interface FPGA 22 is designed to organize the exchange of information with the CP 8 via the high-speed serial interface PCI-Express 17 to provide interaction with the configuration and monitoring units of 23 reconfigurable devices and the FPGA configuration memory 24.

FPGA configuration memory 24 is designed to store configurations for the interface FPGAs 22 and the starting configuration for computing FPGAs 20 ₁ , ..., 20 _M.

The mode control unit 30 of the PCI-Express switch 19 is designed to control the operation mode of the NT / DS / US and NT / US ports of the PCI-Express 19 switch via the control bus 12 of the switch.

The configuration and monitoring unit for reconfigurable devices 23 is intended for organizing the configuration of computing FPGAs 20 ₁ , ..., 20 _M via the PCI-Express 17 interface using the resources of the interface FPGA 22 and from the FPGA 24 configuration memory when the power is turned on, monitoring the temperature regime and controlling power modes computing FPGAs 20 ₁ , ..., 20 _M via the configuration and monitoring bus 25, using temperature sensors built into computing FPGAs 20 ₁ , ..., 20 _M.

Individual monitoring and control units 15 ₁ , ..., 15 _M are designed for independent (without using the resources of the interface FPGA 22) temperature control, power management and providing the required operating frequencies computing VLSI 33 ₁ , ..., 33 _M on individual monitoring buses 14 ₁ , ..., 14 _M

The memory 35 ₁ , ..., 35 _M configurations of computing FPGAs 20 ₁ , ..., 20 _M are designed to store individual starting configurations of computing FPGAs 20 ₁ , ..., 20 _M , which in the general case can be the same or different.

A single rectangular-shaped radiator 27, mounted above the computational VLSI 33 ₁ , ..., 33 _M , is designed to improve the heat dissipation of the crystals of the computational VLSI 33 ₁ , ..., 33 _M and to average the operating temperature of the computational VLSI 33 ₁ , ..., 33 _M with higher and lower power consumption , which reduces the likelihood of failure due to overheating of the crystals of the computational VLSI 33 ₁ , ..., 33 _M.

The proposed reconfigurable computer system operates as follows.

The master server 2, in conjunction with the EtherNet 1 switches, is powered on first. After the initial loading of the operating system (OS), the leading server 2 first turns on the power and loads the operating systems in the KP 8 of the slave slaves 4 ₁ , ..., 4 _K via the EtherNet network, which in turn carries out the power on of the reconfigurable computing devices 13 ₁ , ... 13 _N , and after loading the interface FPGA 22 and computing FPGAs 20 ₁ , ..., 20 _M from the configuration memory of FPGA 24, the thresholds for temperature protection of the computing FPGAs 20 ₁ , ..., 20 _M and computing VLSI 33 ₁ , ..., 33 _M are configured and switch mode PCI-Express 19 and rebooting the OS KP 8 slave WU 4 ₁ , ..., 4 _K. After rebooting the OS in KP 8, which can be carried out in general from stand-alone disks or via EtherNet, the leading server 2 also reboots and launches programs that independently reconfigure the computing FPGAs 20 ₁ , ..., 20 _M reconfigurable computing devices 13 ₁ , ..., 13 _N in the slave WU 4 ₁ , ..., 4 _K , in accordance with the current requirements for the architecture of the reconfigurable computing system. Next, the voltage of the interface FPGA 22, computing FPGAs 20 ₁ , ..., 20 _M and computing VLSI 33 ₁ , ..., 33 _M , as well as the connections of all computing FPGAs 20 ₁ , ..., 20 _M with the PCI-Express switches of the slave controllers are checked 4 ₁ , ..., 4 _K via PCI-Express interfaces.

Since at the initial configuration of computing FPGAs 20 ₁ , ..., 20 _M, they are initialized as agents of the PCI-Express network, in a format that obviously covers the resource needs of users (except for individual, isolated cases), and are allocated in memory of KP 8 at the stage of their load, then after reconfiguring the computing FPGAs 20 ₁ , ..., 20 _{M with the} working programs for rebooting the OS of the slave slaves, as a rule, it is not required. Computing FPGAs 20 ₁ , ..., 20 _{M are} initialized as agents of the PCI-Express network and are distributed in three memory areas of KP 8, one megabyte each.

One of the areas (BAR2) is designed for the interaction of KP 8 of the slave VU 4 with the control and status registers, including with the direct memory access control (DMA) control registers, which are available in each of the FPGA 20 as PCI-Express network agents.

Another area (BAR1) is intended for data exchange with the KP 8 processor of the slave VU 4 via the internal interfaces of the FPGAs 20. These include the interfaces via the internal memory of the FPGA random access (BRAM) and serial access (FIFO), as well as the direct command interface with user hardware devices.

The third area (BAR0) is intended for data exchange between PCI-Express network agents located in the same address space, i.e. between computing FPGAs 20, which are located within the same slave VU 4. The exchange between computing FPGAs 20 is supported at the software and hardware level.

When using data exchange between computing FPGAs 20 within the same slave VU 4 for all reconfigurable computing devices 13 in the data transfer mode via PCI-Express interfaces, one can obtain the union of all computing FPGAs 20 ₁ , ..., 20 _M into a single computing field of VU 4.

When using data exchange between computing FPGAs of 20 different WUs 4 via PCI-Express 28 interfaces through groups of NT / DS / US ports of switches 19 and DS29 ports of switch 31, it is possible to combine all computing FPGAs 20 into a single computing field within the computing system as a whole . Data exchange between computing FPGAs 20 located in different VU 4 is carried out through NT ports, which are actually “opaque” bridges that divide the address spaces of computing nodes 4, and allowing computing FPGAs 20 to interact through established address windows. To establish communication between the WUs, it suffices to use one of the N ports 28 of computing devices 13.

In order to redistribute the resource of computing FPGAs 20 between different WUs 4, at the stage of setting thresholds for temperature protection and the operating mode of the PCI-Express 19 switch, configure the NT / US ports of switch 19, the computing FPGAs 20 are connected to KP 8 WU 4 from the US port , while using the NT port, the address spaces of VU 4 are divided in the memory of the master server 2.

When solving labor-intensive tasks and processing large information arrays and streams, using parallelization and pipelining of computational processes, to speed up computations, the computational processes are decomposed into functional fragments executed by universal and specialized devices that are combined into specific configurations that can be changed dynamically or statically. At the same time, universal devices are entrusted with the task of executing not labor-intensive algorithms, but functions of preprocessing and preparing data for labor-intensive algorithms and exchange data and results with external devices. The architecture of specialized devices adapts to the characteristics of executable computing processes.

In the proposed computing system, computing FPGAs 20 perform not only the functions of universal devices for pre-processing and data exchange, but also service functions for monitoring and controlling the configuration, power and tuning of the operating frequencies of computing VLSI 33, thus ensuring the independent functioning of computing VLSI 33 as inside reconfigurable computing devices of slave WU 4, and the computing system as a whole. In this case, the functions of specialized devices are performed by computational VLSI 33, which are implemented on custom VLSI and are intended for direct circuitry implementation of specific critical fragments of algorithms that may be present in various computing problems. Moreover, overhead VLSI compared to universal FPGAs have reduced overhead: for the organization of connections between elements that consist of a set of segments of the trace channels connected to each other by matrices of programmable switches (keys), which account for up to 90% of the crystal area, as well increased delay in the transfer of data between elements, which account for up to 70% of the operation time, and redundancy in the implementation of schemes due to the high level of universalization.

The monitoring system of the state of the system components allows not only continuous independent monitoring of the state of the main parameters of the computing system (supply voltage, current temperatures of computing FPGAs 20 and computing VLSI 33), as well as timely disconnecting power from overheating computing FPGAs 20 and computing VLSI 33, in order to reduce risk of their irreparable failure.

The proposed reconfigurable computing system provides a multi-user and multi-tasking mode of operation with a minimum resource unit for a user one computing FPGA 20 with the corresponding computing VLSI 33, since all computing FPGAs 20 ₁ , ..., 20 _M have independent interfaces for interaction with PC 8 and can be independently configured with various tasks using the appropriate configuration memory 35 ₁ , ..., 35 _{M of the} same computing FPGA 20 ₁ , ..., 20 _M.

In the proposed reconfigurable computer system, when tasks are distributed across the entire field of computing FPGAs 20 and VLSI 33, tasks are distributed with intensive data exchange over NT / US ports and with high power consumption, together with tasks that do not require intensive exchange or high power consumption, which is achieved by the implementation in the proposed computing module of an independent reconfiguration of the corresponding working FPGAs 20 of the same individual memory starting configurations 35, as well as separate individual adjustment of operating frequencies and separate individual power control for each FPGA computer 20 with appropriate computing eponymous VLSI 33, and individual monitoring of computing for each FPGA 20 to 33 VLSI.

The proposed reconfigurable computing system can be implemented on the following elements:

As a leading server 2, a Kraftway server based on the ED25 platform can be used: Intel (R) Xeon (R) E2620V4 processor 2.10 GHz 8 cores; RAM 64 Gb; hard drive 1 Tb; Switch 1 as GigabitEthernet interface board 5 of the leading server - ABE-2010 based on the PEX8619 switch chip from PLX Technology.

Slave WU 4: Intel (R) Xeon (R) E2620V4 2.10 GHz 8 cores; RAM 64 Gb; hard drive 1 Tb; eight reconfigurable computing devices 13 containing four reconfigurable computing FPGAs 20 and four computing VLSI 33 each.

Reconfigurable computing devices 13: interface FPGAs 22 and reconfigurable computing FPGAs 20 - on Xilinx chips of type XC7A75T-FGG484; PCI-Express 19 switch - on a PX8732 switch chip from PLX Technology; configuration and monitoring unit 23 - on the CPLD XC2C64A, MAX6656, TMP461AIRUNT microcircuits; individual control and monitoring units 38 — on the MAX1239 and si570 microcircuits, start configuration memory 24 and configuration memory 35 — on the M25P64 SPI memory microcircuits.

Thus, in the proposed reconfigurable computer system, VLSI calculations are performed at higher frequencies individually configured for each VLSI, therefore, in comparison with the prototype, this system has higher speed, computing power and lower specific energy consumption due to the use of VLSI computing for direct circuit implementation of critical sections of labor-intensive fragments of computational algorithms that have the best frequency characteristics tics and have a lower percentage of overhead for the implementation of algorithms in relation to FPGAs. In addition, due to the use of unified radiators and the redistribution of system computing resources between tasks with high and low power consumption, the average operating temperature of computational VLSI systems and the probability of their overheating are reduced, and due to the redistribution of system computing resources between tasks with high and low exchange rates, the queues are reduced service in the system, thereby increasing the average speed of data exchange computing FPGAs on external ports.

The above information allows us to conclude that the proposed reconfigurable computing system solves the problem and corresponds to the claimed technical result - it has more computing power and less specific energy consumption.

Claims (1)

A reconfigurable computing system comprising a master server 2 connected via a network interface 3 to an EtherNet 1 control switch of a computer system and via EtherNet 7 ₁ , ..., 7 _K network interfaces with a group of K slave computing nodes 4 ₁ , ..., 4 _K , each which contains a PCI-Express 11 switch, a computer 8 and a group of N reconfigurable computing devices 13 ₁ , ..., 13 _N , each of which contains a PCI-Express 19 switch, a group of M computing FPGAs 20 ₁ , ..., 20 _M , an interface FPGA 22, configuration and monitoring unit 23, control unit the mode of the PCI-Express 30 switch and the FPGA configuration memory 24, the interface FPGA 22 is connected to the PCI-Express 30 switch mode control unit, the FPGA configuration memory 24 and the configuration and monitoring unit 23, which is connected via the common bus for configuring and monitoring computing FPGAs 25 with a group of M computing FPGAs 20 ₁ , ..., 20 _M , and each PCI-Express 19 switch is connected to the control unit of mode 30 of the PCI-Express switch via control bus 12, interface FPGA 22 via a high-speed serial PCI-Ex interface press 17 and with computing FPGAs 20 ₁ , ..., 20 _M , using high-speed serial PCI-Express 21 ₁ , ..., 21 _M serial interfaces, characterized in that it also has a dual-port interface board 5, a PCI-Express 31 switch combining reconfigurable computing devices 13 ₁ , ..., 13 _N , slave computing nodes 4 ₁ , ..., 4 _K , each of which contains a group of N state memories 9 ₁ , ..., 9 _N reconfigurable computing devices 13 ₁ , ..., 13 _N , each of which a group of M computing VLSI 33 ₁ , ..., 33 _M , a single rectangular radiator, were introduced form 27, installed over VLSI computing 33 ₁ , ..., 33 _M , a group of M individual monitoring and control units 15 ₁ , ..., 15 _M and a group of M starting configuration memories 35 ₁ , ..., 35 _{M of the} corresponding computing FPGAs 20 ₁ , ..., 20 _M , and in each slave computing node 4 ₁ , ..., 4 _K, computer 8 is connected to the corresponding EtherNet network interface 7 ₁ , ..., 7 _{K is} connected to N state memories 9 ₁ , ..., 9 _N reconfigurable computing devices 13 ₁ , ..., 13 _N and is connected by a PCI-Express 10 high-speed serial interface to a PCI-Expre switch ss 11, which is a group of N high-speed serial PCI-Express interfaces 16 ₁ , ..., 16 _N connected to the NT / US ports of the corresponding PCI-Express switches 19 groups of N reconfigurable computing devices 13 ₁ , ..., 13 _N , in each of which computing FPGAs 20 ₁ , ..., 20 _{M are} connected to the corresponding memories of the same name 35 ₁ , ..., 35 _M configurations of computing FPGAs on individual buses 36 ₁ , ..., 36 _M reconfiguration of computing FPGAs and on individual buses 32 ₁ , ..., 32 _M operational reconfiguration memory starting configurations, as well as they are connected to the same VLSI computational 33 ₁ , ..., 33 _M via individual data exchange buses 34 ₁ , ..., 34 _M and individual monitoring control buses 26 ₁ , ..., 26 _M to individual monitoring units 15 ₁ , ..., 15 _M , which connected to the corresponding VLSI computing 33 ₁ , ..., 33 _M via the monitoring buses 14 ₁ , ..., 14 _M , in addition, the NT / DS / US ports of the PCI-Express switches 19 reconfigurable computing devices 13 ₁ , ..., 13 _{N are} connected to the corresponding an interface from the group of N high-speed serial PCI-Express combining interfaces 28 ₁ , ..., 28 _N They are combined in K groups 29 ₁ , ..., 29 _K on N high-speed serial interfaces for combining PCI-Express slave computing devices 4 ₁ , ..., 4 _K , and connected to the corresponding DS ports of the PCI-Express 31 switch, whose US port is connected to the port DS of the dual-port interface board 5 via the high-speed serial PCI-Express 18 interface, and the US port of the dual-port interface board 5 is connected via the high-speed serial PCI-Express 6 interface to the host server 2.

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