RU2668983C1 - Input stage of high-speed operational amplifier - Google Patents

Abstract

FIELD: electrical engineering; radio engineering and communication.SUBSTANCE: invention relates to radio engineering and electronics. Input stage of the high-speed operational amplifier comprises: first (1) and second (2) input transistors, first (3) local negative feedback resistor, third (4) and fourth (5) input transistors, second (6) resistor, first (7) device input, second (8) device input, first (9) current stabilizing two-terminal network, first (10) powersupply rail, second (11) current-stabilizing two-terminal network, third (12) current-stabilizing two-terminal network, second (13) powersupply rail, fourth (14) current-stabilizing two-terminal network, first (15) current output of the device, second (16) current output of the device, third (17) current output of the device, fourth (18) current output of the device, first (19) correcting capacitor, second (20) correction capacitor.EFFECT: technical result is increased operating speed of the operational amplifier.1 cl, 10 dwg, 2 tbl

Description

The invention relates to the field of radio engineering and electronics can be used as a device for amplifying analog signals in the structure of high-speed analog microcircuits of various functions and analog interfaces based on them (for example, high-speed operational amplifiers (op amps), multidifferential op amps, etc.).

Known schemes for complementary differential input stages (DC) on bipolar, BiJFet and CMOS transistors [1-15]. DCs of this class (the so-called dual-input-stage) have become the main amplifying element of many analog devices.

The closest prototype (Fig. 1) of the claimed device is the input stage of the operational amplifier described in US patent 5.770.972, containing the first 1 and second 2 input transistors of the same conductivity type, between the emitters of which are included the first 3 local negative feedback resistor, the third 4 and the fourth 5 input transistors of a different type of conductivity, between the emitters of which a second 6 local negative feedback resistor is connected, the first 7 input of the device with which the bases of the first 1 and third 4 input transistors are connected c, the second 8 input of the device with which the bases of the second 2 and fourth 5 input transistors are connected, the first 9 current-stabilizing two-terminal connected between the emitter of the first 1 input transistor and the first 10 bus of the power source, the second 11 current-stabilizing two-terminal connected between the emitter of the second 2 input transistor and the first 10 bus power supply, the third 12 current-stabilizing bipolar connected between the emitter of the third 4 input transistor and the second 13 bus power supply, the fourth 14 current-stabilizing a two-terminal device connected between the emitter of the fourth 5 input transistor and the second 13 bus of the power supply, the collector of the first 1 input transistor connected to the first 15 current output of the device, matched with the second 13 bus of the power source, the collector of the second 2 input transistor connected to the second 16 current output of the device matched with the second 13 bus of the power source, the collector of the third 4 input transistor is connected to the third 17 current output of the device, matched with the first 10 bus of the power source, call the vector of the fourth 5 input transistor is connected to the fourth 18 current output of the device, consistent with the first 10 bus power source.

A significant drawback of the known input stage is that during transients with a large pulse input differential signal, it does not provide large increments of the output currents, which does not allow for the implementation of high-speed operational amplifiers, continuous voltage stabilizers with low levels of "bursts" and " dips ”of the output voltage at pulsed load currents, etc.

The main objective of the proposed invention is the formation of various (specified by the developer) levels of the output dynamic currents of the device, proportional to the derivative of the input differential voltage (voltage between inputs 7 and 8). This can significantly improve the performance of many subclasses of analog circuits (operational amplifiers, voltage stabilizers, etc.) and ensure the identity of the leading and trailing edges of the transient in negative feedback circuits.

The problem is achieved in that in the input stage of the operational amplifier of FIG. 1, containing the first 1 and second 2 input transistors of one type of conductivity, between the emitters of which the first 3 local negative feedback resistor is connected, the third 4 and fourth 5 input transistors of another type of conductivity, between the emitters of which the second 6 local negative feedback resistor is connected, the first 7 the input of the device with which the bases of the first 1 and third 4 input transistors are connected, the second 8 the input of the device with which the bases of the second 2 and fourth 5 input transistors are connected, the first 9 current-stabilizing two x-pole connected between the emitter of the first 1 input transistor and the first 10 bus of the power supply, the second 11 current-stabilizing two-terminal, connected between the emitter of the second 2 input transistor and the first 10 bus of the power source, the third 12 current-stabilizing two-pole connected between the emitter of the third 4 input transistor and second 13 the power supply bus, the fourth 14 current-stabilizing two-terminal connected between the emitter of the fourth 5 input transistor and the second 13 bus power supply, and the collector the first 1 input transistor is connected to the first 15 current output of the device, matched to the second 13 bus of the power supply, the collector of the second 2 input transistor is connected to the second 16 current output of the device, matched to the second 13 bus of the power supply, the collector of the third 4 input transistor is connected to the third 17 the current output of the device, matched with the first 10 bus power supply, the collector of the fourth 5 input transistor is connected to the fourth 18 current output of the device, matched with the first 10 bus power source ika power provided new elements and connections - between the emitter of one of the first and fourth input transistors 5 included a first adjustment capacitor 19 and between the emitter of the second 2 and the emitter of the third input transistor 4 is turned on a second correction capacitor 20.

The prototype amplifier circuit is shown in FIG. 1. In the drawing of FIG. 2 shows the inventive device in accordance with paragraph 1 of the claims.

In the drawing of FIG. 3 shows a diagram of the inventive input stage in accordance with paragraph 2 of the claims.

In the drawing of FIG. 4 shows a diagram of the inventive input stage when it is implemented based on CMOS transistors.

In the drawing of FIG. 5 shows a diagram of the inventive input stage in the structure of high-speed CMOS op-amp.

In the drawing of FIG. 6 shows a diagram of the inventive input stage in the structure of a high-speed CMOS op-amp with the specific implementation of current mirrors 23 and 24.

In the drawing of FIG. 7 is a diagram of the inventive input stage in the structure of a high-speed op-amp in an Orcad environment on tsmc035_t65 transistor models.

In the drawing of FIG. 8 shows the amplitude-frequency characteristic (AFC) of the gain of an open-loop op amp circuit of FIG. 7 with the following capacities of correction capacitors 19, 20 and 27: C ₁₉ = C ₂₀ = 0, C ₂₇ = 1 pF.

In the drawing of FIG. Figure 9 shows the waveforms of the input and output voltages of the op-amp (leading edge) for different capacitances of the correction capacitors 19 and 20 (C ₁₉ = C ₂₀ = Cvar), as well as the capacitance of the main correction capacitor 27 C ₂₇ = 1 pF, currents I ₉ = I ₁₂ = I ₁₄ = 10 μA, pulse width 1 μs.

In the drawing of FIG. Figure 10 shows the waveforms of the input and output voltages of the op amp (trailing edge) for different capacitances of the correction capacitors 19 and 20 (C ₁₉ = C ₂₀ = Cvar), as well as the capacitance of the main correction capacitor 27 C ₂₇ = 1 pF, currents I ₉ = I ₁₂ = I ₁₄ = 10 μA, pulse width 1 μs.

The input stage of the high-speed operational amplifier of FIG. 2 contains the first 1 and second 2 input transistors of one type of conductivity, between the emitters of which the first 3 local negative feedback resistor is connected, the third 4 and fourth 5 input transistors of another type of conductivity, between the emitters of which the second 6 local negative feedback resistor is connected, the first 7 the input of the device with which the bases of the first 1 and third 4 input transistors are connected, the second 8 the input of the device with which the bases of the second 2 and fourth 5 input transistors are connected, the first 9 current-stabilizing two a wicker gate connected between the emitter of the first 1 input transistor and the first 10 bus of the power supply, the second 11 current-stabilizing bipolar connected between the emitter of the second 2 input transistor and the first 10 bus of the power supply, the third 12 current-stabilizing bipolar connected between the emitter of the third 4 input transistor and second 13 the power supply bus, the fourth 14 current-stabilizing two-terminal connected between the emitter of the fourth 5 input transistor and the second 13 power supply bus, and the collector ne the first 1 input transistor is connected to the first 15 current output of the device, matched to the second 13 bus of the power supply, the collector of the second 2 input transistor is connected to the second 16 current output of the device, matched to the second 13 bus of the power supply, the collector of the third 4 input transistor is connected to the third 17 the current output of the device, matched with the first 10 bus power supply, the collector of the fourth 5 input transistor is connected to the fourth 18 current output of the device, matched with the first 10 bus source but nutrition. The first 19 correction capacitor is connected between the emitter of the first 1 and fourth 5 input transistors, and the second 20 correction capacitor is connected between the emitter of the second 2 and the emitter of the third 4 input transistors.

In the drawing of FIG. 3, in accordance with paragraph 2 of the claims, the first 21 correction resistor is connected in series with the first 19 correction capacitor, and the second 22 correction resistor is connected in series with the second 20 correction capacitor.

In the drawing of FIG. 4 shows a diagram of the inventive input stage when it is implemented based on CMOS transistors.

In the drawing of FIG. 5 shows a diagram of the inventive input stage in the structure of a high-speed CMOS op-amp, which contains additional current mirrors 23 and 24, a buffer amplifier 25, the output of which 26 is the output of an operational amplifier, and the main correction capacitor 27, which ensures the stability of the op-amp and the unit gain frequency forming it.

In the drawing of FIG. 6 is a diagram of the inventive input stage in the structure of a high-speed CMOS op-amp with the specific implementation of additional current mirrors 23 and 24, which are implemented respectively on transistors 28, 29 and 30, 31.

Consider the operation of the inventive device of FIG. 2.

The main feature of the proposed differential cascade is the formation of large pulsed currents at the second 16 and third 17, as well as the first 15 and fourth 18 current outputs with a pulse change in the input differential voltage (voltage between the first 7 and second 8 inputs) for both positive and negative polarity u _in .

амплитуда выходного токового импульса определяется первым 19 корректирующим конденсатором, а для отрицательной

- вторым 20 корректирующим конденсаторомFor positive polarity

the amplitude of the output current pulse is determined by the first 19 correction capacitor, and for negative

- second 20 correction capacitor

In this case, the maximum value of the output currents depends on the resistance of the emitter junctions of the first 1 and fourth 5, as well as the second 2 and third 4 input transistors. The introduction (in accordance with paragraph 2 of the claims) in series with the first 19 and second 20 capacitors of the correction resistors 21 and 22, as well as by selecting the numerical values of the capacitance of the first 19 and second 20 capacitors (C19, C20) allows you to control the numerical values of the maximum output currents , in particular, to choose them unequal for different input voltage polarities. This important property of the claimed circuit helps to eliminate the so-called dynamic asymmetry, which manifests itself in uneven transient processes with a positive and negative pulse input signal, for example, in operational amplifiers. Moreover, in the circuit of FIG. 3 maximum output currents can be limited at a given level.

where R ₂₁ , R ₂₂ - resistance of the first 21 and second 22 correction resistors.

The circuit of FIG. 4 corresponding to FIG. 2, is implemented on CMOS transistors in which the gate corresponds to the base, the source to the emitter, and the drain to the collector of a bipolar transistor.

The diagrams of FIG. 5 and FIG. 6 shows the possibility of using the inventive input stage circuit in the CMOS structure of a high-speed op-amp.

Computer simulation of the circuit of FIG. 6 in the Orcad environment (FIG. 7) on the transistor models tsmc035_t65 shows (FIG. 9, table 1 and FIG. 10, table 2) that the maximum slew rate of the output voltage of the op-amp of FIG. 6 increases (for the leading edge) by more than 20 times, and for the trailing edge - by more than 40 times. If necessary, this asymmetry can be reduced by choosing different resistances of the first 21 and second 22 correction resistors. It is important to note that such a gain is achieved when the input stage is in microcurrent mode (I ₉ = I ₁₁ = I ₁₂ = I ₁₄ = 10 μA).

Thus, the claimed device is characterized by a higher speed in comparison with the prototype.

BIBLIOGRAPHIC LIST

1. Patent EP 1150423 A2, fig. 3

2. Patent US 6194962

3. Patent US 5714906, fig. 9a

4. Patent US 6433637

5. Patent application US 2001/0052818, fig. 1, fig. 9

6. Patent US 6822513

7. Patent application US 2005/0001681

8. Patent application US 2007/0159248, fig. 2

9. Patent US 5714906

10. Patent US 4636743

11. Patent US 4783637

12. Patent US 5291149

13. US Pat. No. 4,649,352, fig. one

14. Patent US 5512859, fig. one

15. Patent US 5770972.

Claims (2)

1. The input stage of a high-speed operational amplifier containing the first (1) and second (2) input transistors of one type of conductivity, between the emitters of which the first (3) local negative feedback resistor is connected, the third (4) and fourth (5) input transistors of another conductivity type, between the emitters of which a second (6) local negative feedback resistor is connected, the first (7) input of the device with which the bases of the first (1) and third (4) input transistors are connected, the second (8) input of the device with which base second o (2) and fourth (5) input transistors, the first (9) current-stabilizing two-terminal connected between the emitter of the first (1) input transistor and the first (10) bus of the power source, the second (11) current-stabilizing two-terminal connected between the emitter of the second (2 ) of the input transistor and the first (10) bus of the power source, the third (12) current-stabilizing two-terminal connected between the emitter of the third (4) input transistor and the second (13) bus of the power source, the fourth (14) current-stabilizing two-pole connected between the emitter a solid (5) input transistor and a second (13) power supply bus, the collector of the first (1) input transistor connected to the first (15) current output of the device, matched with the second (13) power supply bus, the collector of the second (2) input transistor connected to the second (16) current output of the device, matched to the second (13) bus of the power supply, the collector of the third (4) input transistor connected to the third (17) current output of the device, matched to the first (10) bus of the power supply, the collector of the fourth ( 5) input The resistor is connected to the fourth (18) current output of the device, matched with the first (10) bus of the power source, characterized in that the first (19) correction capacitor is connected between the emitter of the first (1) and fourth (5) input transistors, and between the emitter of the second (2) and an emitter of a third (4) input transistor includes a second (20) correction capacitor. 2. The input stage of the high-speed operational amplifier according to claim 1, characterized in that the first (21) correction resistor is connected in series with the first (19) correction capacitor, and the second (22) correction resistor is connected in series with the second (20) correction capacitor.

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