RU2653312C1 - Device for addition of k numbers by module m - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to the field of automation and computer technology and can be used in computing structures working with a discrete-phased representation of the numbers of the modular number system. Device contains k information inputs of the device, a harmonic phase meter, synchronizing device input, k-1 phase addition units, three device outputs.

EFFECT: increase is the speed of the device due to the implementation of the addition of discrete phases of harmonics.

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Description

The invention relates to the field of automation and computer engineering and can be used in computational structures working with a discrete-phased representation of numbers of a modular number system.

There is a known code converter of a system of residual classes into voltage (Pat. 2290754 C1 Russian Federation, IPC Н03М 1/66 (2006.01). Declared July 11, 2005; published December 27, 2006.), where the addition of the integer remainders of a number by modules m _i (i = 1..N), containing information inputs, harmonic oscillation generator, controlled phase shifters, π / 2 angle phase shifter, attenuator, balanced phase detector, output.

The disadvantage is low performance.

A device for adding N numbers modulo P is known (Pat. 2188448 C2 Russian Federation, IPC G06F 7/72 (2006.01). Declared 15.11.2000; Published 27.08.2002), containing information inputs, decoders, harmonic signal generator, controlled phase shifters, phase shifters for fixed phase values, harmonic signal phase meter, encoder, output. The disadvantage is low performance.

Closest to the claimed invention is an invention (Pat. 2270476 C1 Russian Federation, IPC G06F 7/72 (2006.01). Claims 06/28/2004; publ. 02/20/2006.), Containing a harmonic signal generator, phase meter of a harmonic signal, phase shifters to a fixed phase value, decoder, controlled phase shifter, encoder, device output, switch, amplitude detector, harmonic signal amplifier, device control input, multiplexer, device information inputs.

The disadvantage is the low speed due to the use of digital controlled phase shifters based on delay lines, switched into an electric circuit by means of keys.

The technical problem, which is aimed by the claimed device, is to increase performance.

The technical result is expressed in the performance of the desired operation through the addition of discrete phases of harmonics without the use of devices operating on the basis of switching delay lines by means of electric switches (controlled phase shifters).

) объединен с третьим входом (i-1)-го блока сложения фаз, выход j-го блока сложения фаз соединен с вторым входом (j+1)-го блока сложения фаз (

), выход (k-1)-го блока сложения фаз соединен с вторым входом измерителя фазы гармонического сигнала, а также объединен с третьим выходом устройства.The technical result is achieved in that a device for adding k numbers modulo m, containing k information inputs of the device, a phase meter of a harmonic signal, introduces a synchronizing input of the device, k-1 blocks of phase addition, the first, second and third outputs of the device, while the input of the device is combined with the first input of the phase addition units, as well as the first input of the phase meter of the harmonic signal, the first output of which is combined with the first output of the device, the second output of the harmonic phase meter Igna combined with the second output device, a first information input device is combined with a second input of the first phase summation block, the i-th information input devices (

) is combined with the third input of the (i-1) th phase addition block, the output of the jth phase addition block is connected to the second input of the (j + 1) th phase addition block (

), the output of the (k-1) -th phase addition unit is connected to the second input of the harmonic signal phase meter, and is also combined with the third output of the device.

In FIG. 1 is a block diagram of a device for adding k numbers modulo m.

In FIG. 2 shows a diagram of a phase addition unit.

In FIG. 3 shows a diagram of a phase meter of a harmonic signal.

The essence of the invention lies in the implementation of the desired operation by direct addition of the phases of the harmonics in accordance with the known trigonometric expressions, and not due to the phase incursion of the signal to some discrete value, as in the prototype. The main reason that reduces the speed of the prototype compared to the device being implemented is the transition from calculating one sum of k numbers to another, since it entails the process of changing discrete values of phase rotation by recommuting delay lines. Even the fastest high-speed semiconductor switches that work with signals in the microwave range carry out this operation for several nanoseconds (p. 12, Shchavruk N.V. Design and manufacture of microelectromechanical switches on GaAs substrates for the microwave range: dis. ... cand. Tech. Sciences: 05.27.01 / Moscow, 2015, 130 pp.). Thus, the application of the properties of harmonic signals when performing operations on a discrete-phased representation of numbers without using switches in an implemented device at an operating frequency, for example, 100 GHz, accelerates calculations by two orders of magnitude.

It should be noted that the branching of the microwave signal lines in FIG. 1 and 3 should be accompanied by the presence of a power divider and amplifiers to increase the amplitude of harmonics to a single value, but to simplify the circuits, these elements are omitted.

An additional effect is to increase the accuracy of calculations due to the constancy of the impedance of the device being implemented, in contrast to the prototype, where, when switching from calculating one sum to another, the signal delays are changed. Another positive effect is the expansion of functionality through the execution on the same device of the desired operation for any module m, in contrast to the prototype, where the phase delay values are fixed. The latter circumstance also entails another positive effect, which consists in the possibility of simultaneously summing the residuals over different modules of the system of residual classes (RNS), which makes it possible to use the implemented device as an output stage in a circuit for calculating the positional characteristics of a modular number.

Shown in FIG. 1 device for adding k numbers modulo m contains a clock input of device 1, information inputs of device 2.1-2.k, phase addition blocks 3.1-3. (K-1), harmonic signal phase meter 4, first 5, second 6 and third 7 device outputs.

), при этом выход блока сложения фаз 3.j соединен с вторым входом блока сложения фаз 3.(j+1) (

), при этом выход блока сложения фаз 3.(k-1) соединен с вторым входом измерителя фазы гармонического сигнала 4, а также объединен с третьим выходом устройства 7.The clock input of device 1 is combined with the first input of phase addition units 3.1-3. (K-1), as well as the first input of the phase meter of the harmonic signal 4, the first output of which is combined with the first output of the device 5, while the second output of the phase meter of the harmonic signal 4 combined with the second output of the device 6, while the information input 2.1 is combined with the second input of the phase addition unit 3.1, while the information input 2.i is combined with the third input of the phase addition unit 3. (i-1) (

), while the output of the phase addition block 3.j is connected to the second input of the phase addition block 3. (j + 1) (

), while the output of the phase addition unit 3. (k-1) is connected to the second input of the phase meter of the harmonic signal 4, and is also combined with the third output of the device 7.

Shown in FIG. 2, the phase addition unit contains the first 8, second 9 and third 10 inputs, a mixer 11, a band-pass filter 12, a mixer 13, a band-pass filter 14, an amplifier 15 and an output 16.

The second input 9 is combined with the first input of the mixer 11, the third input 10 is combined with the second input of the mixer 11, the output of which is connected to the input of the bandpass filter 12, the output of which is connected to the second input of the mixer 13, while the first input 8 is combined with the first input of the mixer 13, the output of which is connected to the input of the band-pass filter 14, the output of which is connected to the input of the amplifier 15, the output of which is combined with the output 16.

Shown in FIG. 3, the harmonic signal phase meter circuit contains first 17 and second 18 inputs, a phase shifter with a fixed value π / 2 19, mixer 20, mixer 21, low-pass filters 22 and 23, first 24 and second 25 outputs.

The first input 17 is combined with the second input of the mixer 20 and the input of the phase shifter to a fixed value π / 2 19, the output of which is connected to the second input of the mixer 21, the second input 18 is combined with the first input of the mixer 20 and mixer 21, the output of which is connected to the low-pass filter 23 the output of which is combined with the second output 25, while the output of the mixer 20 is connected to a low-pass filter 22, the output of which is combined with the first output 24.

a γ_i ∈ [0, m-1]. Здесь m - модуль системы остаточных классов (СОК). В первом блоке сложения фаз 3.1 на смесителе 11 (фиг. 2) производится перемножение сигналов:The operation of the device is as follows. The synchronizing input 1 receives a harmonic signal S = sin (ωt). Discrete-phased harmonics arrive at the information inputs 2.1-2.k: S _i = sin (ωt + 2π⋅γ _i / m), where

a γ _i ∈ [0, m-1]. Here m is the module of the system of residual classes (RNS). In the first block of phase addition 3.1 on the mixer 11 (Fig. 2) is the multiplication of signals:

S ₁ = sin (ωt + 2π⋅γ ₁ / m) and

S ₂ = sin (ωt + 2π⋅γ ₂ / m).

From a well-known trigonometric expression

it follows that after the bandpass filtering of the high-frequency component on block 13, an intermediate result is formed:

The harmonic signal from input 8 is multiplied by a mixer 13 with an intermediate harmonic. Implementing a trigonometric expression

after bandpass filtering of the lower-frequency component at block 14 and amplification at block 15, it gives a result in the form of a harmonic with a unit amplitude and a phase shifted relative to the clock signal by 2π⋅ (Y ₁ + Y ₂ ) / m:

S _{o 3.1} = sin [ωt + 2π⋅ (γ ₁ + γ ₂ ) / m].

As a result of the sequential operation of the phase addition units, a signal is generated at the third output of the device 7:

which can be used for further operations in other modular discrete-phased computing devices.

, который поступает на первый выход устройства 5. Параллельно в измерителе 4 происходит увеличение фазы синхронизирующего сигнала на фиксированное значение π/2 на блоке 19 (S=cos(ωt)) с дальнейшим перемножением в смесителе 21 с результирующей гармоникой S_peз. При этом, согласно выражению (2), после фильтрации нижних частот 23 на втором выходе 25 формируется уровень напряжения, пропорциональный

, который поступает на второй выход устройства 6. Аналоговые значения на первом 5 и втором 6 выходах устройства могут быть использованы, например, для получения в дальнейшем цифрового эквивалента модулярного числа или других применений.This signal also passes through the second input 18 to the phase meter of the harmonic signal 4 (Fig. 3), where on the mixer 20 it is multiplied with the synchronizing harmonic S = sin (ωt), and according to expression (1), after the low-pass filter 22 at the first output 24 a voltage level proportional to

which goes to the first output of device 5. In parallel, in meter 4, the phase of the synchronizing signal increases by a fixed value π / 2 on block 19 (S = cos (ωt)) with further multiplication in mixer 21 with the resulting harmonic S _re . Moreover, according to expression (2), after filtering the low frequencies 23, a voltage level proportional to

, which is supplied to the second output of the device 6. Analog values at the first 5 and second 6 outputs of the device can be used, for example, to obtain the digital equivalent of a modular number or other applications.

Example

We add three numbers (k = 3) modulo m = 5. The device for addition (Fig. 1) will contain, respectively, three information inputs 2.1-2.3 and two phase addition units 3.1-3.2. Let the added numbers, for example, be equal to A1 = 12, A2 = 33 and A3 = 21, the integer remnants of which are modulo five, respectively,: γ ₁ = 2, γ ₂ = 3 and γ ₃ = 1. The harmonic signal S = cos (ωt) is supplied to the synchronizing input 1. The information inputs 2.1-2.3 receive discrete-phased harmonics:

S ₁ = sin (ωt + 2π⋅2 / 5),

S ₂ = sin (ωt + 2π⋅3 / 5],

S ₃ = sin (ωt + 2π⋅1 / 5).

In the first block of phase addition 3.1 on the mixer 11 (Fig. 2) is the multiplication of signals S ₁ and S ₂ . From the expression (1) it follows that after bandpass filtering of the high-frequency component, an intermediate harmonic is formed on block 12:

The harmonic signal from input 8 is multiplied by a mixer 13 with an intermediate harmonic. The implementation of expression (2) after bandpass filtering of the lower-frequency component on block 14 and amplification on block 15 gives the result in the form of a harmonic with a unit amplitude and a phase shifted by 2π⋅0 / 5 relative to the clock signal:

S _{oy 3.1} = sin [ωt + 2π⋅0 / 5].

As a result of a similar operation on block 3.2, a signal is generated at the third output of device 7:

S _pez = sin [ωt + 2π⋅1 / 5],

which can be used for further operations in other modular discrete-phased computing devices.

, который поступает на первый выход устройства 5. Параллельно в измерителе 4 происходит увеличение фазы синхронизирующего сигнала на фиксированное значение π/2 на блоке 19 (S=cos(ωt)) с дальнейшим перемножением в смесителе 21 с результирующей гармоникой S_peз. При этом согласно выражению (2) после фильтрации нижних частот 23 на втором выходе 25 формируется уровень напряжения пропорциональный

, который поступает на второй выход устройства 6. Аналоговые значения на первом 5 и втором 6 выходах устройства могут быть использованы, например, для получения в дальнейшем цифрового эквивалента посредством аналого-цифрового преобразования и вычисления результирующего остатка по модулю. В данном случае (исходя из S_peз) γ_рез=1. Проверим полученный результат. А1+А2+А3=12+33+21=66, что по модулю 5 дает целый остаток, равный 1.This signal also passes through the second input 18 to the phase meter of the harmonic signal 4 (Fig. 3), where on the mixer 20 it is multiplied with the synchronizing harmonic S = sin (ωt), and according to expression (1), after the low-pass filter 22 at the first output 24 a voltage level proportional to

which goes to the first output of device 5. In parallel, in meter 4, the phase of the synchronizing signal increases by a fixed value π / 2 on block 19 (S = cos (ωt)) with further multiplication in mixer 21 with the resulting harmonic S _re . Moreover, according to expression (2), after filtering the low frequencies 23, a voltage level proportional to the second output 25 is formed

, which is supplied to the second output of device 6. Analog values at the first 5 and second 6 outputs of the device can be used, for example, to obtain a digital equivalent in the future by analog-to-digital conversion and calculate the resulting remainder modulo. In this case (assuming S _pez) γ _res = 1. Check the result. A1 + A2 + A3 = 12 + 33 + 21 = 66, which modulo 5 gives a whole remainder equal to 1.

The resulting device reflects the principles of constructing arithmetic devices based on a system of residual classes working with a discrete-phased form of representing numbers. From the point of view of practical application, the device realizes the possibility of constructing analogue microwave computers that exceed the current level of computers in terms of speed.

Claims (1)

A device for adding k numbers modulo m, containing k information inputs of the device, a phase meter of a harmonic signal, characterized in that a synchronizing input of the device, k-1 blocks of phase addition, the first, second and third outputs of the device are introduced, while the synchronizing input of the device is combined with the first input of the phase addition units, as well as the first input of the phase meter of the harmonic signal, the first output of which is combined with the first output of the device, the second output of the phase meter of the harmonic signal is combined with the second th output of the apparatus, the first information input apparatus combined with a second input of the first phase summation block, the i-th data input device

combined with the third input of the (i-1) -th phase addition unit, the output of the j-th phase addition unit is connected to the second input of the (j + 1) -th phase addition unit

, the output of the (k-1) -th phase addition unit is connected to the second input of the harmonic signal phase meter, and is also combined with the third output of the device.

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