RU2642381C1 - Digital functional converter - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: digital functional converter contains four adders, two shear registers, an analysis block, a storage block of constants, a control unit, four inputs and four outputs, wherein the shear registers are linked to the adders-readers, the outputs of which are connected with the analysis block and its outputs - with the control block and all adders-readers.

EFFECT: expansion of the arsenal of tools to calculate functional dependencies.

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Description

The invention relates to digital computing and may find application for a hardware implementation of function calculation.

Known digital functional Converter [A.S. 744595 USSR, 1978], comprising an analysis unit, first and second adders-subtractors, first and second registers and a control unit, wherein the output of the first register is connected to the first input of the first adder-subtractor, the outputs of the control unit are connected to the control inputs of the first and second registers and the clock inputs of the first and second adders-subtracters, the outputs of which are connected to the inputs of the analysis unit, the first output of which is connected to the input of the control unit, and the second output is connected to the control inputs of the first and second adders the output of the second register is connected to the first input of the second adder-subtractor, the second inputs of the first and second adders-subtracters are connected to the information inputs of the second and first, respectively, and are the inputs of the Converter.

The converter is designed to calculate the function of the partial sum of squares by the sum of two arguments.

A disadvantage of the known converter is that it is not intended to calculate other functions.

Closest to the claimed is a digital functional converter [A.S. 922760 USSR, 1982], including an analysis unit, first and second adders-subtractors, first and second shift registers, a control unit and their communications, further comprising a third and fourth adders-deductors and a constant storage unit, the input of the constant storage unit being connected to the first the output of the control unit, the second output of which is connected to the clock inputs of the third and fourth adders-subtracters, the first inputs of which are connected to the output of the constant storage unit, the installation input of which is connected to the input of the unit the converter, the output of the analysis unit is connected to the control inputs of the adders-subtracters, the second inputs of which are connected to the installation input to zero of the converter.

Its disadvantages are also low functionality for calculating other functions.

The objective of the invention is the improvement of the digital functional Converter.

и

где X, Y, W, S - аргументы функций.The technical result is an additional extension of the possible functional dependencies, in particular, due to functions of four arguments of the form

and

where X, Y, W, S are the arguments of the functions.

The technical result is achieved due to the fact that each information input of the digital functional converter is split into two information inputs independent from each other, two of which are connected to the inputs of the first and second adders-subtracters, and the other two to the inputs of the first and second shift registers.

In FIG. The block diagram of the converter is shown. The converter contains adders-subtractors 1-4, shifting registers 5-6, block 7 storing constants, block 8 analysis and block 9 control.

Information inputs are four inputs: X, Y - inputs of the second and first adders-subtractors 2, 1, respectively, and W, S - inputs of the first and second shift registers 5, 6, respectively.

There are technological inputs: the installation input of the constant storage unit 7 (for writing “1”), the start input (for the pulse to start the calculation) and the input “set 0” for preliminary resetting to the “0” of the third and fourth adders 3, 4.

Adders-subtractors 1-4 can be performed on single-digit adders-subtracters and a cumulative shift register. The first input of a single-bit adder is the first input of the adder-subtracter, the second input of which is the information input of the register, the output of which is the output of the adder-subtracter. The output of the least significant bit of the register is connected to another input of the single-bit adder-subtracter, the output of which is connected with the input of the highest bit of the register. The clock input is connected to the register shift input. The control input is connected to the input of a single-bit adder-subtracter, the signal on which controls the addition-subtraction mode at the first input. The adder-subtractor can also be implemented on a parallel combinational circuit.

The inputs of analysis block 8 are the outputs of the first 1 and second 2 adders-subtractors, and its outputs are connected to the second input of the control unit 9 and the control inputs of all four adders-subtracters 1-4 (addition-subtraction mode).

The constant storage unit 7 of the form 2 ^{- (j + 1)} can be implemented on a shift recirculation register, the highest bit of which is connected to the unit setup circuit, and shift clock pulses (second output of the control unit 9) are fed to the register shift input. The constant storage unit 7 may be implemented as a one-way memory device.

The operation of this digital functional converter is based on the simultaneous solution of a system of recurrent difference equations in an iterative process

where j = 0,1,2, ..., (n - 1); n is the bit depth of the arguments.

The convergence of this iterative process (1) - (5) is ensured for (w + s) ≥ (x - y).

All equations are solved simultaneously (X _n in the adder-subtractor 2, Y _n in the adder-subtractor 1, Z _n in the adder-subtractor 3, the operator q _j is determined in analysis block 8, the quantity x ⋅ 2 ^{- (j + 1) is} obtained in shifting register 5, the value y ⋅ 2 ^{- (j + 1) is} obtained in shifting register 6, the value 2 ^{- (j + 1)} is generated in the constant storage unit 7), and each of the equations can be calculated either sequentially or in parallel.

The calculations in the proposed Converter are as follows.

Before starting work, the first and second arguments Y and X, respectively, are set in the adders-subtractors 1, 2, and the third and fourth arguments W w S, respectively, are set in the shift registers 5, 6.

In the sequential calculation principle, a unit is entered in the constant storage unit 7 (the highest bit of the register of the constant storage unit 7). At the second inputs of the adders-subtracters 3-4, a signal is set to zero. Then, the start pulse is supplied to the control unit 9. From the first output of the control unit 9, a clock pulse is supplied to the shift registers 5-6 and the constant storage unit 7, which shifts the values of the registers by one binary digit to the right of the binary point. Then, the clock pulses from the second output of the control unit 9 advance the contents of the shift registers 5-6 and the registers of the constant storage unit 7 to the inputs of the corresponding adders-subtractors 1-4. In the latter, the incoming operands with the previous values are added or subtracted.

The addition-subtraction mode at the next iteration is determined by the difference X _j - Y _j in block 8 of the analysis. In the case of a positive difference (X _j - Y _j ≥ 0), the signal q _j (in the form of a voltage level) is output from the second output of the analysis block, which determines the addition in the adders-subtractors 1 and 3 and the subtraction in the adders-subtractors 2 and 4. When negative difference (X _j - Y _j ) in adders-subtractors 2 and 4, addition is performed, and in adders-subtractors 1 and 3, subtraction is performed. The change in signal q _{j is} performed after each iteration at the time the clock pulse appears at the first output of the control unit 9.

в сумматоре-вычитателе 3 содержится значение функции

а в сумматоре-вычитателе 4 содержится значение функции

After performing n iterations, the calculations are completed and the control unit 9 ceases to issue clock pulses. In adders-subtracters 1-2 contains the value of the function

in the adder-subtractor 3 contains the value of the function

and in the adder-subtractor 4 contains the value of the function

, а также вычисление функций

и

причем время вычисления остается прежним. Расширение функциональных возможностей достигается путем минимальных затрат (добавления только двух сумматоров-вычитателей).Compared with the known, the proposed converter has enhanced functionality, as it provides additional function calculation

as well as function calculation

and

moreover, the calculation time remains the same. The expansion of functionality is achieved through minimal costs (adding only two adders-subtracters).

The proposed converter is intended for the hardware implementation of the calculation of these functions, which is widely used in measuring technology (for calculating the modulation coefficient, determining relative errors), in radar technology (for example, when normalizing signals of conditional errors, during auto tracking, etc.), specialized calculators for scientific calculations and control of technological processes and physical objects.

Claims (1)

A digital functional converter comprising an analysis unit, first, second, third, fourth adders-subtractors, first, second shift registers, a control unit, a constant storage unit, the outputs of the first and second shift registers connected to the first inputs of the same adders-subtracters, the outputs of the block the controls are connected to the control inputs of both shift registers, the constant storage unit and the clock inputs of all adders-subtracters, the output of the constant storage unit is connected to the first inputs of the third and the fourth adder-subtractor, the outputs of the first and second adder-subtractor are connected to the inputs of the analysis unit, the outputs of which are connected to the control unit and the control inputs of all four adders-subtracters, the outputs of which are the outputs of the digital functional converter, characterized in that each information input is digital the functional converter is split into two information inputs independent of each other, two of which are connected to the inputs of the first and second adders-subtracters her, and the other two - with the inputs of the first and second shift registers.

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