RU2614663C1 - Varicap and method of making same - Google Patents

Abstract

FIELD: physics, instrument-making.

SUBSTANCE: invention relates to microelectronics and microsystem engineering and is a capacitor with a voltage-controlled capacitance, i.e., a varicap. The varicap is a "metal-porous silicon" heterostructure, where pores of the porous silicon are filled with metal by electrochemical deposition. The varicap can be used in integrated electronic devices for adjusting frequency and frequency modulation, as well as in devices requiring the use of high-capacitance capacitors in integrated form.

EFFECT: invention increases specific capacitance and varicap capacitance overlapping coefficient.

2 cl, 7 dwg

Description

The invention relates to the field of microelectronics and microsystem technology and is a capacitor with a capacitance controlled by voltage, that is, a varicap. The varicap can be used in integrated devices of electronic equipment for tuning the frequency and frequency modulation, as well as in devices requiring the use of high-capacity capacitors in the integrated version.

A high value of the specific capacity of the varicap is achieved by increasing the area of the plates when using porous silicon. A method of manufacturing a varicap provides for the possibility of its manufacture on a single chip with an integrated circuit or a silicon micromechanical transducer.

A known method of manufacturing a varicap based on a Schottky diode, including the creation of epitaxial buildup of the semiconductor region, ion doping of the semiconductor region and the creation of a metal electrode / 1 /.

The disadvantage of this method is the complexity of the manufacture of the device, which is associated with the need to use processes of epitaxial growth, ion doping, thermal annealing. The need to use annealing to restore the broken crystalline structure of the semiconductor and to activate an impurity complicates the process of incorporating the proposed method into the technological chain of manufacturing a varicap as part of microelectromechanical systems.

A known method of producing semiconductor devices with variable capacitance, including the formation of a p-n junction by plastic deformation of a semiconductor wafer and the connection of conclusions adopted for the prototype / 2 /. The plate is deformed by bending around the direction <110> to obtain a V-shape with an angle at the apex of 90-140 ° concentrated load at a temperature of 800-870 ° C. Electrical contacts are connected to the deformed material by thermal compression with the formation of a ball or spot welding, gold with the appropriate additives is used as a cold material.

The disadvantage of this method is the use of a plastic deformation process to create a varicap. Mechanical stresses in a semiconductor arising after mechanical deformation will cause a gradual change and degradation of the device parameters. In addition, the creation of contacts by thermocompression increases the dimensions of the device and reduces its reliability.

Known diode with variable capacitance based on the p-n junction containing the epitaxial layer and two layers formed by diffusion, between which the p-n junction is formed / 3 /.

The disadvantage of this device is that a significant change in capacitance requires a voltage change over a wide range, for example, a 20 pF change in capacitance requires approximately a 25 V voltage change. This is unsuitable for many modern integrated devices, since the supply voltage of such products It is usually within 3 ÷ 15 V. Another disadvantage of the device is that to increase the maximum capacitance and the overlap coefficient of the diode capacity, an increase in breakdown voltage is required. This is achieved by reducing the resistivity of the semiconductor layer, and, as a result, leads to an increase in the size of the diode.

Known semiconductor device with reactivity controlled by voltage (varicap), adopted as a prototype / 4 /. The device includes a semiconductor made in the form of a film with an inhomogeneous impurity distribution profile, or with an inhomogeneous film thickness profile, or with an inhomogeneous impurity distribution profile and film thickness. This design of the varicap allows you to implement an arbitrary dependence of the capacitance on the voltage.

The disadvantage of this device is the low value of the maximum specific capacity due to the planar structure of the varicap. Another disadvantage is the complexity of manufacturing the device and a significant number of operations required for its manufacture. Creating a given profile of impurity distribution, providing a certain type of voltage dependence of the capacitance, will require precise control of the parameters of technological processes. Obtaining an impurity profile, in addition, requires the use of ion doping or thermal diffusion. Creating an inhomogeneous (along the plate surface) distribution profile complicates the doping process, increasing the number of related operations.

The objective of the invention is the increase in specific capacity, the coefficient of overlap for the capacity of the varicap.

A varicap is proposed that includes a semiconductor substrate and a metal-semiconductor contact, characterized in that the metal-semiconductor transition is formed on a porous silicon layer with a large specific surface, the pores of which are filled with metal.

A method for producing a varicap is proposed, which includes the formation of a metal-semiconductor transition, characterized in that the working layer of the semiconductor region is formed by electrochemical anodizing of silicon, the metal-semiconductor transition is formed by electrochemical deposition of metal in the pores of porous silicon.

The invention allows the creation of capacitors with controlled capacitance (varicaps) with a high value of specific capacitance and a large coefficient of overlap in capacitance. A high value of specific capacitance is achieved through the use of porous silicon as a semiconductor electrode with a developed surface. A metal electrode is formed by electrochemical deposition of metal into the pores of porous silicon. The technology for producing a varicap is compatible with the technologies of microelectronics and microsystem technology, does not require the introduction of non-standard technological operations, meets the trends of miniaturization and the expansion of the functional characteristics of microdevices.

Compared with the prototype, the invention has the advantage that the manufacturing method does not involve the use of plastic deformation of silicon. In the device manufactured according to the proposed method, no mechanical deformation occurs. The method involves the manufacture of a device using batch processing, meets the requirements of miniaturization, is compatible with microelectronics and microsystem technology.

The advantage of the varicap compared to the prototype is that with the same planar dimensions, the varicap will have a larger specific capacity. This is ensured by using porous silicon having a developed surface as a semiconductor, the specific surface of porous silicon can reach values of 1000 m ² / cm ³ . The real surface area of the porous layer according to calculations made using the fractal geometry approaches / 5 / exceeds the geometric area of the varicap by at least three orders of magnitude. Another advantage of the invention compared to the prototype is that the design of the varicap does not require a complex profile of the distribution of impurities and, accordingly, the use of additional doping operations of the semiconductor and lithographic processes in the manufacture of the device.

The varicap is shown in FIG. 1, where: 1 is the lower metal electrode, 2 is the p + -type silicon substrate, 3 is the p-type silicon layer, 4 are the interstitial walls in the porous silicon layer, 5 is the metal intercalated into the pores, 6 is the upper metal electrode, 7 is depleted layer.

A method of manufacturing a varicap is presented on

FIG. 2, where 2 is the p + -type silicon substrate, 3 is the p-type silicon layer;

FIG. 3, where 1 is the lower metal electrode, 2 is the p + -type silicon substrate, 3 is the p-type silicon layer;

FIG. 4, where 1 is the lower metal electrode, 2 is the p + -type silicon substrate, 3 is the p-type silicon layer; 4 - inter-pore walls in a layer of porous silicon, 8 - pores in a layer of porous silicon;

FIG. 5, where 1 is the lower metal electrode, 2 is the p + type silicon substrate, 3 is the p-type silicon layer; 4 - inter-pore walls in a layer of porous silicon, 5 - metal intercalated into pores, 6 - upper metal electrode;

FIG. 6 is an image of an experimentally obtained structure with a layer of porous silicon, where 3 is a p-type silicon layer, 4 are inter-pore walls in a porous silicon layer;

FIG. 7 is an image of an experimentally obtained structure with a layer of porous silicon and an intercalated metal, where 3 is a p-type silicon layer, 4 are pore walls in a p-type porous silicon layer, 5 is a metal intercalated into pores.

The capacity of the barrier layer of varicap C _{b is} proportional to the area of the transition S _{to the} metal-semiconductor / 6 /:

,

,

where e is the electron charge; N _a is the concentration of electrically active impurities; ε is the dielectric constant of the medium; ε ₀ is the dielectric constant of vacuum; ϕ _to - contact potential difference; U is the bias voltage. Obviously, with an increase in the area of the heterojunction, its barrier capacity increases. When the reverse voltage changes, the capacitance of the varicap varies widely.

The maximum reverse bias of the varicap is limited both by the breakdown of the heterojunction and by the voltage at which the spatial charge regions of 5 neighboring pores overlap. In this regard, to ensure maximum capacity at zero displacement, the thickness of the inter-pore walls 3 L _article must satisfy the condition:

L _article > 2W _eff ,

where W _eff is the effective thickness of the space charge region, is defined as / 7 /:

,

,

L _D is the Debye screening length, k is the Boltzmann constant, T is the temperature. The change in the barrier capacitance of the diode with a change in the reverse voltage is due to the movement of the main charge carriers in the semiconductor region adjacent to the heterojunction. The time constant τ of this process, or relaxation time, is determined according to the expression / 8 /:

τ = 2εε ₀ ρ

where ρ is the resistivity of the semiconductor. The time constant for holes in the p-region is of the order of 10 ^-12 ÷ 10 ^-13 s. Such a low value of the relaxation time indicates that changes in the magnitude of the barrier capacitance of the varicap with a change in the bias voltage can affect only very high frequencies.

For the practical implementation of the invention, the following processes are used. A developed-surface silicon electrode is fabricated on KDB10 (100) single-crystal silicon substrates with a p + / p homojunction to create an ohmic contact to the substrate. The formation of the porous layer is carried out by anodizing silicon in an aqueous-alcoholic solution with 10% hydrofluoric acid. Anodizing is carried out in galvanostatic mode at a current density of 80 mA / cm ² . The surface layer of porous silicon is removed in a solution of sodium hydroxide, after which the samples are washed in a solution of ethanol. Copper is used as a metal electrode. Copper precipitation is carried out from an aqueous solution of CuSO ₄ ⋅ 5H ₂ O with the addition of alcohol. During the deposition process, the current density varies between 0.1 ÷ 2 mA / cm ² . For experimental varicap samples, the capacitance of the structure was calculated from the charge-discharge curves. For structures with a size of 5 × 5 mm, with a porous layer thickness of 10 μm, the average value of the capacitance was 0.1 mF, which in terms of the specific capacity is 0.4 mF / cm ² . The use of a working layer based on porous silicon gives, in comparison with a structure with a flat working layer, an increase in the specific capacity by 400 times. The reduced value of the specific capacitance of the experimental structure compared to the expected calculated value can be explained by the spread in pore sizes and the overlapping of the space charge regions in the porous layer.

Thus, the implementation of the invention will increase the specific capacity and the coefficient of overlap for the capacity of the varicap. The increase in the specific capacity of the varicap is achieved by increasing the area of the plates when using porous silicon. Compared with the prototype, the invention has the advantage that the manufacturing method does not involve the use of plastic deformation of silicon, while there is no mechanical stress. The method does not require the introduction of non-standard technological operations, involves the manufacture of the device using batch processing, meets the requirements of miniaturization and expansion of the functional characteristics of microdevices, is compatible with microelectronics and microsystem technology.

The advantage of the varicap compared to the prototype is that with the same planar dimensions, the varicap will have a larger specific capacity. This is ensured by using porous silicon as a semiconductor having a developed surface, the specific surface of which can reach values of 1000 m ² / cm ³ . Another advantage of the invention compared to the prototype is that the design of the varicap does not require a complex profile of the distribution of impurities and, accordingly, the use of additional doping operations of the semiconductor and lithographic processes in the manufacture of the device.

Information sources

1. US patent No. 20010031538.

2. USSR author's certificate No. 510059 - prototype.

3. US patent No. 4475117.

4. RF patent No. 2119698 - prototype.

5. N.A. Torkhov, V.G. Bozhkova, I.V. Ivonin, V.A. Novikov, "Determination of fractal dimension of the surface of epitaxial n-GaAs in a local limit", Semiconductors, 2009, vol. 43, No. 1, pp. 33-41.

6. Gaman V.I. Physics of Semiconductor Devices: Textbook. - Tomsk: NTL Publishing House, 2000. P. 15.

7. Zi S. Physics of semiconductor devices. In 2 books. Prince 1. Trans. from English 2nd rev. and add. ed. - M .: Mir, 1984.P. 84.

8. Pasynkov VV, Chirkin L.K. Semiconductor devices. - M.: Higher School, 1987.S. 86.

Claims (2)

1. A varicap comprising a semiconductor substrate and a metal-semiconductor transition, characterized in that the metal-semiconductor transition is formed on a porous silicon layer with a developed specific surface, the pores of which are filled with metal. 2. A method of manufacturing a varicap, including the formation of a metal-semiconductor transition, characterized in that the working layer of the semiconductor substrate is formed by electrochemical anodizing of silicon to obtain a layer of porous silicon, and the metal-semiconductor transition is formed by electrochemical deposition of metal into the pores of porous silicon.

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