RU2504891C1 - Method of generating output frequency of direct synthesis digital synthesiser - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: method of generating output frequency of a direct synthesis digital synthesiser involves calculating a frequency code in accordance with the required output frequency value; recording in a frequency register and transmitting the frequency code to a phase accumulator; if the calculated value of the frequency code is a fraction, calculating a first frequency code corresponding to the initial frequency code rounded off to a whole number and the fractional part of the initial frequency code; selecting a second frequency code differing by one from the first frequency code, and recording in the frequency register; alternately reading from the frequency register the first and second frequency codes with periodicity defined by the fractional part of the initial frequency code; the frequency code comes from the frequency register and the phase accumulator; the phase accumulator calculates an address which is input into the ROM of a phase register; the phase register calculates the instantaneous value of the output signal in digital form, which is transmitted to a digital-to-analogue converter and is converted to a corresponding signal value in analogue form.

EFFECT: low level of secondary discrete components of the output signal.

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Description

The invention relates to electronics, in particular to digital synthesizers of direct synthesis, and can be used to generate the output frequency of a digital synthesizer of direct synthesis (DSPC) with a low level of undesirable harmonics in the spectrum of the output signal of the synthesizer.

The traditional DSPC circuit consists of a frequency register, a phase accumulator, a phase register, a phase to amplitude converter and a digital-to-analog converter.

This scheme operates as follows. In the frequency register, write a number in the binary system that determines the frequency value of the output signal of the synthesizer and is called the frequency code. The frequency code is supplied to one of the inputs of the phase accumulator, to the other input of which a digital clock frequency signal f _{CLK is} supplied from an external reference frequency source. The phase accumulator calculates the address corresponding to the instantaneous value of the phase, and feeds it to the input of the phase register. The latter is usually a ROM with tabular values of the sine function. At the output of the phase register, the current phase value is obtained, which the phase to amplitude converter converts into the current signal value in digital form. A digital-to-analog converter converts this digital value to the corresponding voltage or current value.

Digital direct synthesis synthesizers (DSPCs) provide high frequency tuning speed, low phase noise. However, during direct digital synthesis, non-harmonic side components arise due to the effects of discretization and rounding at the synthesizer nodes. Errors causing the appearance of secondary discrete components in the spectrum of the output signal can be divided into three types. The first type includes errors caused by phase rounding when addressing a ROM with a table of the synthesized function. The second type is errors related to the finite bit depth of the data bus. The third type includes errors caused by the digital-to-analog converter. The greatest contribution to the deterioration of the spectral characteristics of the synthesizer is made by errors associated with phase rounding, causing the appearance of undesirable discrete components in the spectrum of the output signal of the synthesizer.

The occurrence of spurious discrete components in the near range of the output signal spectrum corresponding to a detuning of 1-150 kHz from the main signal is associated with the need to round the frequency code to the nearest integer when calculated by the formula:

,

,

where f is the synthesized frequency; N - phase battery capacity (accumulating adder), f _CLK - clock frequency.

The resulting number is entered digitally into the frequency register. From the frequency register, the calculated code enters the phase accumulator. As a result, an error occurs in the frequencies of the calculated and true output signal, which will gradually accumulate in the phase accumulator. Due to the finite capacity of the phase accumulator, the capacity of which is usually 32 bits, the rate of accumulation of this error will be sufficient to change the value of the first significant bit per unit when addressing a ROM with a table of sines of the synthesized function with a certain period, as a result of which an output in the output spectrum will be observed signal. This overflow of the ROM address will occur rather rarely, as a result of which the observed spurious discrete components will appear only in the near zone of the output signal.

However, the range of the output signal detuning in the range of 0.1-120 kHz falls into the Doppler range of the output frequency, which is subject to strict requirements for the level of discrete spurious components, the level of which should be no more than minus 100-110 dB.

A known method of generating the output frequency of the DSPC, which provides suppression of discrete side components and is described in US patent No. 4410954, in which in addition to the classical structural diagram of the synthesizer with a phase drive, an additional pseudo-random code generator is introduced. Periodically adding a pseudo-random number to the contents of the phase storage device allows you to destroy the coherence of the phase error and thus blur the unwanted discrete components in the spectrum of the output signal.

However, the use of this method requires the introduction of additional elements into the synthesizer circuit, and since most digital direct synthesizers are produced in the form of microcircuits, this method requires a change in the microcircuit, which in most cases cannot be done.

Closest to the claimed invention is a method of generating a frequency of a signal free of non-harmonic distortion of the signal described in patent application EP No. 543186. In this method, the preliminary clock frequency fl is set and the frequency code value (read address) is set in accordance with the output frequency. Then, the value of the ratio of the number of ROM memory cells to the frequency code value is determined. If the result of division is an integer natural number, then the preliminary clock frequency fl is used to synthesize the output frequency. If the ratio is obtained with the remainder, the frequency code value is changed (P), choosing it larger than the number of ROM memory cells N, and divide M by it, calculating the result of dividing M by P. Based on the obtained data, the clock frequency f2 is calculated to provide the required output frequency depending on the frequency code P. Thus, to generate the output frequency of the synthesizer, use the frequency code P and the clock frequency f2. The specified method allows to obtain a stable frequency of the output signal, independent of the capacities of the phase accumulator and ROM, and a relatively clean spectrum of the output signal.

However, despite all the advantages of the described method, it requires changing the DSPC circuit and introducing a frequency-tunable signal source to provide a variable clock frequency. Often it is not possible to change the DSPC circuit, and an additional tunable source will introduce additional noise.

The objective of the invention is the provision of generating an output signal with a low level of side spectral components in the spectrum of the output signal of a digital direct synthesis synthesizer.

The essence of the claimed invention lies in the fact that in the method of generating the output frequency of a digital direct synthesis synthesizer, including calculating the frequency code in accordance with the desired value of the output frequency, writing the frequency code to the frequency register, supplying the frequency code to the phase accumulator, calculating the address phase by the accumulator, phase register sent to ROM, calculation by phase register of the instantaneous value of the output signal in digital form and conversion by means of a digital-to-analog converter into the corresponding value in analog form, if the calculated frequency code value is fractional, calculate the first frequency code corresponding to the frequency code rounded to an integer, and the fractional part of the frequency source code, select a second frequency code that differs by one from the first frequency code, write the second frequency code in the frequency register, alternately read from the frequency register the first and second frequency codes with a frequency determined by the fractional part of the original frequency code.

In addition, a method is claimed in which, along with the above characteristics, a second frequency code is used, one greater than the first frequency code, and frequency codes are read with a frequency determined by the formula:

,

,

where a is the number of downloads of the first frequency code from the frequency register, b is the number of downloads of the second frequency code from the frequency register, ΔM is the fractional part of the initial frequency code.

The technical result of the claimed invention is to reduce the level of side discrete components of the output signal of the synthesizer without changing the scheme of the DSPC.

The specified technical result is achieved through the use of two frequency codes, one of which corresponds to the frequency code calculated in accordance with the required value of the output signal frequency and rounded to the nearest whole number, and the second differs from the first one; and switching between them during the generation process with a frequency sufficient to compensate for the error that occurs due to rounding of the frequency code. At the same time, switching to the closest possible frequency code ensures the generation of a signal at another, but closest to the carrier frequency, which compensates for the accumulation of errors. Due to the compensation of the cumulative error, there are no periodic surges occurring in the form of secondary discrete components in the spectrum of the output signal. Along with the suppression of secondary discrete components, there is a decrease in phase noise in the near zone from the carrier during a detuning of 200 kHz. The level of suppression reaches 20 dB. The inventive method allows to purposefully reduce the level of secondary discrete components without introducing additional phase noise and without changing the scheme of the DSPC.

The method is as follows. A signal with a clock frequency is fed to the CLOCK input of the DSPC, based on the condition that the required output frequency should be no more than 0.4 of the clock frequency. To synthesize the required frequency, the phase shift value is calculated - the frequency code in accordance with the formula:

,

,

where f is the synthesized frequency; N - phase battery capacity, f _CLK - clock frequency.

The resulting frequency code value is rounded to the nearest integer. This rounding introduces an accumulated error in the output signal, which manifests itself in the form of secondary spectral components in the spectrum of the output signal. When the phase accumulator overflows, the accumulated error is ejected in the form of a secondary spectral component located near the carrier and which cannot be suppressed even by a narrow-band filter due to the filter bandwidth being limited when filtering the main signal.

To solve this problem, it is necessary to compensate for the error that occurs.

In one of the frequency registers write the first frequency code M, expressed in binary representation and characterizing the phase increment. For each specific frequency, the error corresponding to the discarded decimal numbers is determined by the formula: ΔM = M0-M, where M0 is the initial unrounded frequency code, M is the first frequency code, which is the source frequency code rounded to an integer.

In the other frequency register, write the next value of the frequency code M1 = M + 1 - the second frequency code, and switch the codes with a frequency that depends on the magnitude of the error.

The frequency switching frequency codes are determined by the formula:

,

,

where a is the number of downloads of the first frequency code from the frequency register, b is the number of downloads of the second frequency code from the frequency register, ΔM is the fractional part of the initial frequency code.

This approach, which differs from the known methods for suppressing incidental spectral components, leads to the fact that the level of the incidental discrete component decreases, passing into phase noise near the carrier.

Example.

A specific implementation of the proposed method is presented for the frequency f = 336 MHz at a clock frequency f _CLK = 1008 MHz and the battery capacity of the phase N = 32 bits for the AD9910 chip from Analog Devices. The calculation of the frequency code M0 is carried out according to the formula:

.

.

M0 = 1431655765.3 (3) in decimal.

In the frequency register, the source code of the frequency M0 is converted to a hexadecimal number system with rounding to the nearest integer. Thus, the code converted by the frequency register has the form M = 55555555 in the hexadecimal notation. In the decimal number system: M = 1431655765. Then, the second frequency code M1 is calculated, which is equal to the first frequency code M increased by one: M1 = M + 1. Thus, the second frequency code is M1 = 55555556 in the hexadecimal number system and M1 = 1431655766 in the decimal number system.

Calculate the relative error ΔM that occurs when rounding the source code of the frequency M0 to an integer M, according to the formula:

ΔM = M0-M.

For this specific example, ΔM = 1/3.

Calculate the relative error ΔM1 that occurs when using the frequency code M1, according to the formula:

ΔM1 = M0-M1.

For this specific example, ΔM1 = -2 / 3.

To determine the switching frequency between the first frequency code M and the second frequency code M1, a linear combination of ΔM and ΔM1 is made up, which is necessary to compensate for the error that occurs when using frequency codes M and M1 that are different from the original M0 by the formula:

Δ = a · ΔM + b-ΔM1.

Full compensation is achieved when A tends to 0.

The coefficients a and b are then determined, which specify the switching frequency between the rounded frequency code M and the second frequency code M1. Those. the value of the coefficient a corresponds to the number of frequency downloads corresponding to the number of continuous readings of the first code M from the frequency register, after which the frequency downloads corresponding to the second code M1, with a duration corresponding to the value of the coefficient b.

For this specific example, the linear combination takes the form: 0 = a · 1/3 + b · (-2/3).

Hence a = 2, b = 1.

For this specific example, FIG. 1 shows the spectrum of the DSPC output with a 1 MHz span using error compensation (a) and without it (b). Figure 2 shows the phase noise of the DSPC output signal with a frequency of 336 MHz with a 1 MHz span at a clock frequency of 1008 MHz using error compensation (-) and without it (-).

Claims (2)

1. A method of generating an output frequency of a direct synthesis digital synthesizer, including calculating a frequency code according to a desired output frequency, writing a frequency code to a frequency register, supplying a frequency code to a phase accumulator, calculating an address forwarded to the phase register ROM by the phase accumulator, calculating by means of the phase register of the instantaneous value of the output signal in digital form and conversion by means of a digital-to-analog converter into the corresponding value in analog form, distinguishing in that if the calculated frequency code value is fractional, the first frequency code corresponding to the frequency code rounded to an integer and the fractional part of the initial frequency code are calculated, the second frequency code is selected, which differs by one from the first frequency code, and the second frequency code in the frequency register, alternately read from the frequency register the first and second frequency codes with a frequency determined by the fractional part of the source frequency code. 2. The method according to claim 1, characterized in that a second frequency code is used, one greater than the first frequency code, and frequency codes are read with a frequency determined by the formula:

,
where a is the number of downloads of the first frequency code from the frequency register,
b is the number of downloads of the second frequency code from the frequency register,
ΔM is the fractional part of the frequency source code.

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