RU2503990C1 - System for controlling data output with dynamic zero balancing - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: apparatus includes a data memory register, a digital-to-analogue converter, an input bus, an output bus, a pulse former, a comparator, a selector, first and second two-input AND logic elements, a bidirectional counter, a sampling/storage device, an additional digital-to-analogue converter and an additional input bus.

EFFECT: reduced errors caused by destabilising factors.

1 dwg

Description

The invention relates to automation and computer technology and can be used in the design of research process control systems, in particular in the development of an automated system designed to determine the physicomechanical properties of materials by kinetic indentation.

A device for controlling the output of data [1]. This device has a high error from the influence of destabilizing factors.

Also known is a data output control system, which is the closest technical solution to the proposed invention [2]. This system is also characterized by a high error from the influence of destabilizing factors.

The aim of the invention is to reduce the error from the influence of destabilizing factors.

This goal is achieved by the fact that in the data output control system with dynamic "zero" balancing (system), containing data memory register 1 (register 1), digital-to-analog converter 7 (DAC 7), input bus 11, and also output bus 13, additionally a pulse shaper 2, a comparator 3, a selector 4, a first logic element 5 2I and a second logic element 6 2I are introduced. The system also additionally contains a reversible counter 8, a device 9 sampling-storage (UVX 9), an additional digital-to-analog converter 10 (DAC 10) and an additional input bus 12, and the input of the driver 2 pulses and the second input of the register 1 are interconnected and connected to the input bus 11. The output of the register 1 is connected to the second input of the selector 4, the third input of which is connected to the additional input bus 12, and the output to the first input of the DAC 7. The output of the DAC 7 is connected to the combined first inputs of the UVX 9 and comparator 3, the second input VX 9 is connected with the first output of the pulse shaper 2. The third output of the pulse shaper 2 is connected to the first inputs of the first and second logic elements 5 and 6 2I connected together, respectively, the second output is also connected to the first inputs of the register 1 and selector 4. The first output of the comparator 3 is connected to the second input of the first logical element 2I, the second output is to the second input of the second logic element 6 2I, the output of which is connected to the second input of the reversing counter 8. The output of the first logic element 5 2I is connected to the first input of the reversing counter ka 8, whose output is combined with the input of the additional DAC 10 that its output is connected to a second input of the DAC 7. The second input of the comparator 3 is connected to the electrical "zero", is connected to the output bus 13 of output of SHA 9.

Consider the operation of the system on its specific application in an automated system designed to determine the physicomechanical properties of materials by the kinetic indentation method.

In the process of indentation from the input bus 11 to the second input of the register 1 receives data codes and simultaneously with them to the input of the shaper 2 pulses receive synchronizing pulses. For each synchronizing pulse, the pulse shaper 2 generates control pulses at its outputs in the necessary sequence and duration. When a synchronizing pulse arrives at the input of the pulse shaper 2, a signal will be installed at the first output of this shaper and, accordingly, at the second input of the UVX 9, which will switch the UVX 9 from the sampling mode to the storage mode, i.e. for the duration of this signal at the output of the UVX 9 and, accordingly, on the output bus 13, the value of the output signal of the UVX 9 will be recorded. Next, a signal will be generated at the second output of the pulse shaper 2 and, accordingly, at the first inputs of the register 1 and selector 4 in register 1, the code of the data installed on its second input from the input bus 11, and will provide the output of the selector 4 and, respectively, to the first input of the DAC 7 code data received from the additional input bus 12 to the third input of the selector 4. At the additional input a code is set on the bus 12, the value of which is logical “zero”, then the DAC 7, in accordance with the “zero” code, will form an analog signal at its first input, the value of which is equal to electric zero. From the influence of destabilizing factors, the magnitude of the output voltage at the output of the DAC 7 may differ from zero and have a different polarity. This voltage, for example, of positive polarity, arriving at the first input of the comparator 3, sets at its first output and, accordingly, the second input of the first logical element 5 2 And the logical "unit", and at the second output and, accordingly, at the second input of the second logical element 6 2I - logical "zero". Next, the pulse shaper 2 will install on its third output and, respectively, at the first inputs of the first and second logic elements 5 2I and 6 2I, respectively, a signal that, passing through the logic element 5 2I to the first input (subtracting) of the reverse counter 8, will reduce the value of its output code, and this, in turn, will lead to a decrease in the voltage at the output of the DAC 10 and, accordingly, at the second input (zero balancing input) of the DAC 7. A decrease in voltage at the second input of the DAC 7 will lead to a decrease in the voltage polarity at its output. Next, the 2 pulse shaper will remove the signals installed on its second and third outputs and after the necessary time on the first one, after which the code recorded in register 1 will go through selector 4 and converted to the analogue equivalent in DAC 7, but with a smaller error, it will go through UVX 9, which is in the sampling mode, to the output bus 13. As the synchronizing pulses arrive from the input bus 11, the processes of balancing "zero" will be similar to the above. In the case when the “zero” code at the first input of the DAC 7 at its output will be a voltage of negative polarity, at the first output of the comparator 3 and, accordingly, at the second input of the first logic element 5 2I will be set to logical “zero”, and on the second output of this the comparator and, accordingly, at the second input of the second logical element 6 2I is a logical "unit", and this, in turn, will ensure the passage of the signal from the third output of the pulse shaper 2 to the second input (summing) of the reverse counter 8, increasing its value in Source Code. An increase in the code at the output of the reverse counter 8 and, respectively, at the input of the DAC 10 will increase the voltage at the output of the DAC 10 and, accordingly, at the second input of the DAC 7. An increase in voltage at the second input of the DAC 7 will lead to a decrease in the voltage of negative polarity output. A further decrease in the magnitude of this voltage for each clock pulse will cause the voltage at the output of the DAC 7 to be set equal to zero.

Thus, the set of system components with their interconnections provides a reduction in the error from the influence of destabilizing factors. An additional positive quality is the elimination of interference on the output bus 13, due to changes in the values of the codes at the first input of the DAC 7, since during transients in the DAC 7 the UVX 9 is in storage mode.

Information sources

1. RF patent No. 2445673, 11/17/2010

2. RF patent No. 2445675, 11/17/2010

Claims (1)

Dynamic zero-balanced data output control system, comprising a data memory register, a digital-to-analog converter, an input as well as an output bus, characterized in that it additionally contains a pulse shaper, a comparator, a selector, first and second logic elements 2I, a reversible counter, a device sample-storage, an additional digital-to-analog converter and an additional input bus, and the input of the pulse former and the second input of the data memory register are interconnected and connected to the input bus, the output of the data memory register is connected to the second input of the selector, the third input of which is connected to the additional input bus, and the output is connected to the first input of the digital-to-analog converter, the output of the digital-to-analog converter is connected to the combined first inputs of the sampling-storage device and the comparator, the second the input of the sample-storage device is connected to the first output of the pulse shaper, the third output of which is connected to the first inputs of the first and second logic elements 2, interconnected And, the second output - with the first inputs of the data memory register and selector also interconnected, the first output of the comparator is connected to the second input of the first logic element 2I, the second output - to the second input of the second logic element 2I, the output of which is connected to the second input of the reversible counter, the output of the first logical element 2I is connected to the first input of the reversible counter, the output of which is combined with the input of the additional digital-to-analog converter, which is connected with the second input of the digital-channel by its output ovogo inverter, a second input of the comparator is connected to the electric zero, the output of sample-store unit is connected to the output bus.