RU2485704C1 - Four-port backup device for coupling of circular networks of communication network - Google Patents

Abstract

FIELD: radio engineering, communications.SUBSTANCE: four-port backup device (FPBD), comprises two switchboards (2) of data packets, every of which is connected to the other switchboard (2) and with two ports (3 and 4), designed for connection into the first and second circular communications networks, and a clock synchronisation unit (5). To the unit (5) the outlets of two receivers (6) and (7) are connected, as well as inlets of two transmitters (8) and (9), designed for the first circular network, outlets of two receivers (10 and 11), inlets of two transmitters (12 and 13), designed for the second circular network, and the outlet of the receiver (14) of the external synchronisation signal. The unit (5) is made as capable of generation of a clock signal synchronised with output signals of receivers with introduction of a fixed delay of an output signal for each receiver, issue of a generated signal to inlets of transmitters, and as capable of translation of output signals of receivers to inlets of transmitters designed for the identical network. The device is equipped with a configuration interface (15) as capable of setting the receivers and transmitters of the synchronising signal, delay values of output signals of receivers and permit or prohibition of transmission of output signals of receivers to inlets of transmitters.EFFECT: improved accuracy of clock synchronisation.2 dwg

Description

FIELD OF TECHNOLOGY

The invention relates to the field of construction of communication networks of data transmission with ring redundancy and can find application in automation systems of power facilities built according to the international standard IEC61850 [IEC 61850-5 “Communication systems and networks in substations. Part 5. Communication requirements for the performance of functions and equivalent circuits of (electronic) devices. ” 2003 (electronic resource). Access mode http://www.standards.ru/document/3643715.aspx] with increased requirements for the accuracy of time synchronization.

In particular, the proposed four-port device can be used to pair a pair of ring networks into a common communication network operating according to the HSR protocol of the international standard IEC 62439-3 [IEC 62439-3 “Industrial communication networks. Networks with high readiness for automatic processing. Part 3. Parallel Redundancy Protocol (PRP) and High Availability Seamless Redundancy (HSR). ” 2010 (electronic resource). Access mode: http://www.standards.ru/document/4561443.aspx].

BACKGROUND

The IEC 62439-3 standard describes the QuadBox device, which is a four-port device for connecting two ring networks into a single communication network with ring redundant data transmission.

Synchronization of data transmission in an integrated network using a known device is carried out through the use of specific rules for the transmission of data packets, which does not allow for the increased requirements for synchronization accuracy imposed by the IEC61850 standard (for example, in accordance with classes T4 or T5 of the specified standard, the synchronization accuracy should be not worse than ± 4 μs or ± 1 μs, respectively).

SUMMARY OF THE INVENTION

The technical result of the invention is to improve the accuracy of clock synchronization during data transmission in a communication network with redundancy, formed by pairing at least two ring networks. In the case of using the invention in an automation system of an energy facility built in accordance with IEC 61850, the accuracy of synchronization is ensured in accordance with class T5.

The above technical result is achieved due to the fact that four receivers and four transmitters are additionally introduced in the four-port redundancy device (hereinafter - CHUR), which contains two connected data packet switches, each of which is connected to two data transmission ports, and a clock synchronization unit the clock signals and the receiver of the external synchronization signal, the outputs of the receivers and the inputs of the transmitters are connected to the clock synchronization unit, which is configured to generate a clock signal ala synchronized with the output signals of the receivers with the introduction of a fixed delay for each of the receivers, issuing the generated signal to the inputs of the transmitters, and with the possibility of broadcasting the output signals of at least two receivers of clock signals to the inputs of the respective transmitters, the device is equipped with a configuration interface with the ability to setting the modes of receivers and transmitters of clock signals, delay values of signals of receivers and enable or disable broadcast of clock signals .

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a diagram of the proposed CHUR.

Figure 2 shows an exemplary diagram of a communication network with two ring networks connected by the proposed CHUR.

DETAILED DESCRIPTION OF THE INVENTION

CHUR 1 contains (see figure 1):

- two switches 2 data packets interconnected;

- two communication ports 3, interconnected by a switch 2 and intended for the first ring network;

- two communication ports 4, interconnected by another switch 2 and intended for the second ring network;

- block 5 clock synchronization;

- the first 6 and second 7 clock receivers designed for the first ring network;

- the first 8 and second 9 clock transmitters for the first ring network;

- the first 10 and second 11 clock receivers for the second ring network;

- the first 12 and second 13 transmitters of clock signals for the second ring network;

- receiver 14 external synchronization;

- configuration interface 15.

Part of CHUR 1, which includes a pair of communication ports 3, a pair of communication ports 4 and two connected data packet switches 2, functions similarly to the QuadBox devices described in the IEC 62439-3 standard. The work of the rest of the CHUR, including unit 5, receivers 6, 7, 10, 11 and 14, transmitters 8, 9, 12 and 13, is described below.

Receivers 6, 7, 10, 11, and 14 receive clock signals from external communication channels and transmit the received signals to block 5. Transmitters 8, 9, 12, and 13 transmit the clock synchronization signal received from block 5 to the corresponding ring networks. Moreover, both receivers 6, 7, 10, 11, and 14, and transmitters 8, 9, 12, and 13 provide an almost deterministic time for the execution of the clock signal translation operation with an uncertainty of the operation time of not more than ± 0.01 μs.

The operation of block 5 clock synchronization depends on the selected operating mode CHUR, which allows you to work in one of two modes: source mode and repeater mode of clock synchronization signals.

When the CHUR is in the source mode of clock synchronization, block 5 as part of device 1 performs the following functions:

- receives the external signal by the receiver 14 and introduces a fixed delay of the output signal for this receiver;

- generates a clock signal synchronized by the delayed output signal of the receiver 14;

- gives the generated signal to the transmitters 8, 9, 12 and 13.

This ensures the continuous formation of the internal time scale, its correction due to synchronization by the delayed signal of the receiver 14, the formation and transmission of the output signal of clock synchronization to transmitters 8, 9, 12 and 13.

The introduction of a fixed delay compensates for the time of delivery of the clock signal from an external synchronization source over the communication channel to the CHUR device. The value of the specified delay can be from zero to several microseconds and must be set with a resolution of not more than 0.25 μs.

When the CHUR is operating in the repeater mode of the clock synchronization signals, the operation of the clock synchronization unit 5 depends on the location of the clock synchronization source, which can be located in both the first and second ring communication networks to which this CHUR device is connected.

When the source of clock synchronization is located in the first ring communication network, block 5 receives the clock signals from receivers 6 and 7, and when the source of clock synchronization is in the second ring communication network, respectively, from receivers 10 and 11.

When the source of clock synchronization is located in the first ring communication network, the clock signal received from receiver 6 is transmitted to the transmitter 9, and the clock signal received from receiver 7 is transmitted to the transmitter 8. When the source of clock synchronization is found in the second ring communication network, the clock is transmitted the signal received from the receiver 10 to the transmitter 13, and the signal received from the receiver 11 to the transmitter 12.

When performing the above-described translations of the clock signal, block 5 provides an almost deterministic time for the execution of individual broadcast operations of the clock signal (with the uncertainty of the time taken to complete the broadcast operation from the receiver to the corresponding transmitter of not more than ± 0.1 μs).

When operating CHUR in repeater mode, block 5 performs the following functions:

- introduces a fixed output delay for receivers 6 and 7 or receivers 10 and 11;

- generates a clock signal synchronized by the delayed output signals of the respective receivers;

- provides the generated signal to the respective transmitters.

This ensures the continuous formation of the internal time scale, its correction due to synchronization by delayed signals of receivers 6 and 7 or receivers 10 and 11, the formation and transmission of the output clock synchronization signal to transmitters 12 and 13 or transmitters 8 and 9, depending on which ring network is the source of clock synchronization.

The introduction of a fixed delay of the signals of the receivers in this mode also provides compensation for the time of delivery of the clock signal from the external synchronization source via the communication channel to the CHUR device.

The configuration interface 15 enables the external workstation to be connected to the CHUR to perform device configuration, in particular, to configure the operation parameters of the clock synchronization unit 5. When configuring CHUR via interface 15, it is provided:

- setting the operating mode of the CHUR — the source mode or the repeater mode of the clock synchronization signals, and also in the case of selecting the repeater mode — setting the location of the clock synchronization source (in the first or second ring communication network);

- setting the values of the fixed delay of the output signals for each of the receivers 6, 7, 10, 11 and 14.

In the case of setting the operation of the CHUR in the source mode, one receiver 14 is set as the receiver of the synchronization signal, signal transmission between all pairs of receivers and transmitters connected to the first and second ring communication networks (receiver-transmitter pairs 6–9, 7–8, 10 is prohibited -13, 11-12).

In the case of setting the operation of the CHUR in the repeater mode and setting the location of the clock synchronization source in the first ring communication network, receivers 6 and 7 are installed as synchronization signal receivers, the resolution of synchronizing signal transmission between pairs of receivers and transmitters 6-9 and 7-8 is set, and broadcast prohibition between pairs of receivers and transmitters 10-13 and 11-12. In the case of setting the operation of the CHUR in the repeater mode and setting the location of the clock synchronization source in the second ring communication network, receivers 10 and 11 are installed as synchronization signal receivers, the synchronization signals broadcast resolution is set between pairs of receivers and transmitters 10-13 and 11-12 and broadcast prohibition between pairs of receivers and transmitters 6-9 and 7-8;

The receivers 6, 7, 10, 11 and 14 and the transmitters 8, 9, 12 and 13 in the CHUR device can be implemented on the basis of standard optical receivers and transmitters, for example, HFBR-24 × 6Z and HFBR-1712TZ from the manufacturer Avago Technologies. Block 5 clock synchronization can be performed on the basis of a programmable logic integrated circuit (FPGA) and highly stable crystal oscillator. The configuration interface 15 can be performed on the basis of a standard Ethernet interface (IEEE 802.3).

Figure 2 shows an example of building a communication network using the proposed device. The communication network shown in FIG. 2 includes two ring communication networks connected by CHUR. Figure 2 shows:

- external source 16 clock synchronization signals;

- single-wire segments 17 and 18 for data transmission in the first and second ring network, respectively;

- two-wire segments 19 and 20 for bi-directional transmission of clock signals in the first and second ring network, respectively;

- a four-port backup device 1 connected to segments 17, 19 of the first ring network and to segments 18 and 20 of the second ring network and, therefore, included in each ring network as its node;

- intelligent electronic devices 21 that support the inclusion of a ring communication network directly (without using intermediate backup devices);

- intelligent electronic devices 22 that do not support inclusion in a ring communication network and are included in the rings 17 and 18 through nodes 23.

The network shown in FIG. 2, in terms of data transmission, operates in accordance with IEC 62439-3, and in terms of transmission of clock signals, as follows.

The clock synchronization signal enters the first ring network (with segments 19) from an external source 16 (which, for example, can be a system for providing a single time of an energy object) through one of the nodes 23, which operates in the source mode, generating and sending a clock signal synchronization with other devices of the first ring network connected by segments 19, as well as with an intelligent electronic device 22 connected to the first ring network through this node 23. Other nodes 23 in the first ring network with the study of the clock synchronization signal from the neighboring node 23 relay the specified signal to another neighboring node 23, thus providing bidirectional transmission of the clock signal over the segments 19.

CHUR 1 retransmits clock synchronization signals from the first ring network, to which the source of clock signals 16 is connected, to the second network, the nodes of which are connected by segments 20. At the same time, ring transmission of both data and clock synchronization signals is provided in the integrated network.

Segments 19 and 20 for bi-directional transmission of clock signals can be implemented, for example, on the basis of fiber-optic signal transmission networks 1PPS ("one-pulse-per-second"). At the same time, if the nodes 22 and CHUR fulfill the compensation of the time of delivery of the clock signal from the signal source to the receiver with the discreteness of the task, the values of the time compensation are not more than 0.25 μs and taking into account the above allowable values of the uncertainties of the delays provided by the nodes 22 and the ChUR during clock signals (± 0.01 μs is the delay uncertainty introduced by the receiver or transmitter, ± 0.1 μs is the delay uncertainty introduced by the device clock synchronization unit when broadcasting from the receiver to the feeder) ensures the accuracy of the clock synchronization of devices in the communication network is not worse than ± 1 μs.

Claims (1)

A four-port redundancy device containing two interconnected data packet switches, each of which is connected to two data transmission ports, and a clock synchronization unit, characterized in that four receivers, four clock transmitters and an external synchronization signal receiver, and receiver outputs and the inputs of the clock transmitters are connected to the clock synchronization unit, which is configured to generate a clock signal synchronized with the output signal receivers with the introduction of a fixed delay of the signal of each of the receivers, issuing the generated clock signal to the inputs of the transmitters and with the possibility of broadcasting clock signals from the outputs of at least two clock receivers to the inputs of the respective transmitters, while the device is equipped with a configuration interface with the ability to set modes receivers and transmitters of clock signals, delay values of receiver signals and enable or disable the broadcast of clock signals.

Images