RU2461957C1 - Differential stage with increased voltage gain - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: differential stage with increased voltage gain contains input parallel-balancing stage, output transistor, buffer amplifier, resistor of collector load, subsidiary power source, subsidiary resistor, subsidiary transistor.

EFFECT: increase of limit values of voltage gain ratio of DS at low-voltage supply.

3 cl, 5 dwg

Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying analog signals in the structure of analog microcircuits for various functional purposes (for example, SiGe-operational amplifiers (op amps), microwave amplifiers, comparators, continuous voltage stabilizers, etc. )

In modern microelectronics, classic cascode differential cascades (DC) with resistors in the collector circuit of input transistors are used [1-13]. This architecture is the basis of a wide class of analog and digital devices and is basic for both existing and fundamentally new nanotechnologies [10].

Closest to the technical nature of the claimed device is the input differential stage in the device according to the patent US 5.568.092 fig.1.

A significant drawback of the known DC, the architecture of which is also present in other amplification stages [1-13], is that under restrictions on the supply voltage (E _p ) characteristic of SiGe technological processes (E _p ≤2.0 ÷ 2.5 _C ), its voltage gain (K _y ) is small (K _ymax = 10 ÷ 20). This is primarily due to restrictions on the resistances of the collector load resistors, which, due to small E _p, cannot be selected high. Therefore, to increase K _{y, the} so-called dynamic loads (DNs) are used, for example, on bipolar transistors, which require a static voltage between the power source and the output of the DN to provide a linear operating mode U _DN = 0.8 ÷ 1.6 V. Moreover, the numerical values of U _ДН are equal to 0.8 V for the simplest dynamic loads, which, unfortunately, have a low output impedance:

where U _Earley - voltage Earley output rnp transistor Nam;

I _e = I ₀ is the static current of the emitter pnp output transistor DN.

For integral transistors U _airlie = 20 ÷ 30 V. Therefore, when I ₀ = 1 mA, the use of classical dynamic loads does not allow to obtain K _y > 200 ÷ 300. Higher output resistances R _days are realized in Wilson current mirrors or cascode circuits. However, they only work if the static voltage U _bottom between the terminals of such a dynamic load is more than 2U _eb ≥1.6 V. With a low-voltage power supply this is unacceptable. In addition, not all technological processes (for example, SGB25VD, introduced in Russia) allow the use of pnp transistors. For other technologies (NPO Integral, Minsk), the use of pnp transistors is not recommended under conditions of radiation exposure to a microelectronic product.

Thus, at low supply voltages, and especially in cases where it is necessary to obtain more or less significant amplitudes of the output voltage, the well-known circuitry solutions of the DC are inefficient.

The main objective of the invention is to increase the limit values of the gain in DC voltage at low voltage power.

The problem is solved in that in a differential cascade with increased voltage gain (Fig. 1) containing an input parallel-balanced stage 1 with first 2 and second 3 current outputs, the output transistor 4, the emitter of which is connected to the first 2 current output of the input in parallel -balance stage 1, and the collector is connected to the input of the buffer amplifier 5 and through the collector load resistor 6 is connected to the bus of the power supply 7, an auxiliary voltage source 8, new elements and communications are provided - the base of the output trans the source 4 is connected to the second 3 current output of the input parallel-balanced stage 1 and through an additional resistor 9 is connected to the bus of the power supply 7, the emitter of the output transistor 4 is connected to the emitter of the additional transistor 10, the base of which is connected to the auxiliary voltage source 8, and the collector is connected to power supply bus 7.

The drawing of figure 1 shows a diagram of a DC prototype.

A diagram of the inventive device corresponding to claim 1 and claim 3 of the claims is shown in the drawing of figure 2.

The drawing of figure 3 shows a diagram of a recreation center in accordance with paragraph 2 of the claims.

The drawing of figure 4 presents a diagram of the DC (figure 2) in a computer simulation environment PSpice on models of integrated transistors of FSUE NPP Pulsar.

The graph of Fig. 5 characterizes the frequency dependence of the voltage gain (K _y ) of the DC (Fig. 4) for the output of the buffer amplifier 5.

The differential stage (Fig. 1) contains an input parallel-balanced stage 1 with the first 2 and second 3 current outputs, an output transistor 4, the emitter of which is connected to the first 2 current output of the parallel-input stage 1, and the collector is connected to the input of the buffer amplifier 5 and through the collector load resistor 6 is connected to the bus of the power source 7, the auxiliary voltage source 8. In this case, the base of the output transistor is connected 4 to the second 3 current output of the input parallel-balanced stage 1 and through additional resistor 9 is connected with the power source bus 7, the emitter output of the transistor 4 is connected to the emitter of the additional transistor 10, whose base is connected to the auxiliary voltage source (8), and whose collector is connected to the supply bus 7.

In the drawing of figure 2, the input parallel-balanced stage 1 contains input transistors 11, 12 and a current source 13, which sets their static modes.

In the circuit of FIG. 2, the buffer amplifier 5 is implemented in a particular case on a transistor 13, a zener diode 14 and a current source 15, and a correction capacitor 19 is connected in parallel with the additional resistor 9.

In the drawing of Fig. 3, in accordance with claim 2, the collector of the additional transistor 10 is connected to the bus of the power source 7 through an additional load resistor 16 and is connected to the auxiliary 17 output of the device through the auxiliary 18 buffer amplifier. This allows you to implement the second antiphase output 17 and thus solve the problem of constructing a DC with a paraphase output.

Consider the operation of the circuit of figure 2.

The change in u _I leads to an increase in emitter (i _e ) and collector (i _k ) currents of transistors 11, 12, 4:

where φ _T ≈25 mV is the temperature potential;

- сопротивления эмиттерных переходов транзисторов 11 и 12 при статическом токе эмиттера I_э=2I₀.

- resistance of the emitter junctions of transistors 11 and 12 with a static emitter current I _e = 2I ₀ .

The voltage U ₃ at the current output 3 (u ₃ = u _кl2 ≈i _к12 R ₉ ), which is the input voltage for the cascade on transistors 4 and 10, creates the first i _e4.10 component of the current increment of the emitter current of transistor 4:

.Where

.

Therefore, the total increment of the collector current i _{k4 of the} transistor 4 and the output voltage of the DC

where K _y is the voltage gain DC (Fig. 2).

ДК-прототипа в N-раз.Thus, the voltage gain K _{y of the} claimed remote control exceeds

DC prototype N-times.

Where

- коэффициент усиления по напряжению ДК (фиг.1).

- gain voltage DC (figure 1).

These findings are confirmed by the results of computer simulation (figure 5). The inventive DC has more than an order of magnitude high voltage gain and a two-channel architecture — transmission of the signal to the output via high-frequency (transistors 11, 4) and relatively high-frequency (transistors 12, 4) channels, which positively affects the stability of the DC in circuits with negative feedback allows, in accordance with paragraph 3 of the claims, to provide the correction of the amplitude-frequency characteristics by shunting an additional resistor 9 with a special capacitor.

Thus, the claimed differential cascade has several advantages in comparison with the DC prototype.

Literature

1. US Patent Application 2010/007419, fig. 3.

2. US patent No. 7.737.783.

3. US Patent No. 5.568.092, fig. 1.

4. US Patent No. 6,100.759, fig. 3.

5. US Patent Application 2002/0093380, fig. 1.

6. US Patent Application 2009/0195312, fig. 1.

7. US Patent No. 3,541,465, fig. 3.

8. US Patent No. 5,440.271.

9. US Patent No. 6,262.628, fig. 14B.

10. US Patent Application 2006/0181347, fig. 2.

11. US Patent Application 2006/0044064, fig. 2.

12. US Patent No. 6.011.431, fig. 3.

13. England patent GB 1520085, fig. 2.

Claims (3)

1. Differential stage with increased voltage gain, containing an input parallel-balanced stage (1) with first (2) and second (3) current outputs, an output transistor (4), the emitter of which is connected to the first (2) current output of the input parallel -balance cascade (1), and the collector is connected to the input of the buffer amplifier (5) and is connected to the bus of the power source (7) through the collector load resistor (6), an auxiliary voltage source (8), characterized in that the base of the output transistor is connected ( 4) with a second (3) current input input one parallel-balanced stage (1) and through an additional resistor (9) connected to the bus of the power source (7), the emitter of the output transistor (4) is connected to the emitter of the additional transistor (10), the base of which is connected to the auxiliary voltage source (8), and the collector is connected to the bus of the power source (7). 2. The differential cascade with increased voltage gain according to claim 1, characterized in that the collector of the additional transistor (10) is connected to the bus of the power source (7) through an additional load resistor (16) and connected to the auxiliary (17) output of the device through the auxiliary (18) buffer amplifier. 3. The differential cascade with increased voltage gain according to claim 1, characterized in that a correction capacitor (19) is connected in parallel with the additional resistor (9).

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