RU2414740C1 - Electric power supply of electromagnetic compensators - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: electric power supply (IP) of electromagnetic compensators (EMK) consists of DNVS (1), IZV (2), the first (3) and the second (4) adders, phase-shifting pulse-width modulation converter (5), HF filter (6), VK (7), comparator (8), DPVN (9), inverter (10), FSI (11), DTI (12), DVT (13) and load (14). Connection of the above elements of IP circuit of EMK forms two feedback loops: one for current and the other one for voltage. Such circuit provides the possibility of suppressing the pulsations of output current and interference of the network for arbitrary types of load, active and reactive, without reducing the efficiency of the device.

EFFECT: reaching deeper suppression of appearing current pulsations and providing protection against pulse interference.

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Description

The invention relates to electrical engineering and is intended for use as part of the devices of the demagnetization of ships, in particular as a power source of electromagnetic compensators (EMC).

Known power sources EMC.

So, the well-known EMC power supply is implemented as a phase-shifting modulator (PWM) converter, based on the phase-shifting resonant controller UC3875 (domestic analogue 1156 E1) and described in the Reference Chips for switching power supplies and their application. M .: ed. the house of "Dodeca XXI", 2001, p.248. Such a power source (IP) EMC provides control of IP with a capacity of up to tens of kW.

The disadvantage of this analogue is the narrow scope of its application due to its unipolarity, which excludes its use for powering the demagnetization windings.

A device is also known to demagnetize a vessel (RF patent No. 2095277, 1997), which contains the power source of the EMC. The circuit includes a series-connected current regulator, a power source and a winding system, a comparison unit and an adder connected to strain gauges. This scheme provides a reduction in power consumption. A disadvantage of the known analogue is the relatively low stability of the power source to possible ripple current in the load.

The closest analogue (prototype) in its technical essence to the claimed object is the "Power source of electromagnetic compensators" according to the patent of the Russian Federation No. 2289192, IPC Н02М 7/04, publ. December 10, 2006

IP EMK-prototype consists of a source of the driving action (WPI), equipped with a signal input, phase-shifting wide-pulse modulator (PWM) converter, EMC, which is the load of the device, the first and second adders implemented on operational amplifiers, summing the operational amplifier, comparator, output which, through a capacitor and inductor and using a transformer, is connected to a current sensor and a rectifier, an analog switch, an inverter, an inverting operational amplifier and a measuring opera radio amplifier. The listed elements and the corresponding order of their connection during the operation of the IP EMC provide an increase in the reliability of the device and reduce its overall dimensions.

The disadvantage of the closest analogue is the relatively shallow current ripple suppression and insufficient protection from the effects of impulse noise, due to the need to reduce its gain in the feedback circuit in order to prevent the excitation of the power source at the moment the current passes through zero values due to its delay, since the EMC represents inductance. In addition, in the closest analogue, due to the use of transformers in the circuit of its inverter, the device does not provide operation with a quasi-constant control function of a hertz fraction.

The aim of the invention is the development of IP EMC, providing a deeper suppression of the arising current ripple and protection against impulse noise.

The declared IP EMK expands the arsenal of funds for this purpose.

In the declared IP EMC, the goal is achieved by the fact that in a known power source of electromagnetic compensators containing IZV, equipped with a signal input, and the first output of which is connected to the first inputs of the first and second adders (SUM), the outputs of which are connected respectively to the first and second inputs of the phase-shifting A PWM converter, the output and the second input of which are connected respectively to the input of the converter rectifier (VK) and the input of a comparator equipped with an inverse input, an inverter current sensor (DTI), an input and a second output which are connected respectively to the output of the inverter and to the input of the load, the output of which is connected to the first input of the inverter, an additional rectifier voltage sensor (DNVS), an output current detector (DVT), an inverter signal conditioner (FSI), an output voltage ripple sensor (DPVN) are additionally introduced and a high pass filter (HPF).

The DNVS output is connected to the second input of the first SUM. The input and output of the DWT are connected respectively to the first output of the DTI and the second input of the second SUM. The first, second inputs and outputs of the FSI are connected respectively to the output of the comparator, the second output of the SIS and the second input of the inverter, the input and output of the DPVN are connected respectively to the first output of the VC and the input of the HPF, the output of which is connected to the third input of the first SUM. The first and second outputs of the VK are connected respectively to the third and fourth inputs of the inverter.

Thanks to the new set of essential features, one current feedback loop and a second voltage feedback loop are formed in the EMC IP, which makes it possible to suppress output current ripples and network noise for arbitrary types of load: active and reactive, without reducing the efficiency of the device and, therefore, ensure the achievement of the goal - a deeper suppression of ripple current.

The claimed IP EMC is illustrated by drawings, which show:

figure 1 is a General diagram of IP EMC;

figure 2 - diagram of the inventory.

The power supply of electromagnetic compensators, shown in figure 1, consists of DNVS 1, WPI 2, the first 3 and second 4 adders, phase shifting PWM converter 5, high-frequency filter 6, VK 7, comparator 8, DPVN 9, inverter 10, FSI 11, DTI 12, DVT 13 and load 14.

The first output of WPI 2 is connected to the first input 3.1 of the first SUM 3 and to the first input 4.1 of the second SUM 4. Additionally, the SPM 2 is equipped with a signal input. The outputs of the first 3 and second 4 SUM are connected respectively to the first 5.1 and second 5.2 inputs of the phase-shifting PWM converter 5. The output and the second input 5.2 of the PWM converter 5 are connected respectively to the input of VK 7 and the input of the comparator 8, equipped with an additional inverse input (I _pore ) . The input and the second output 12.2 DTI 12 are connected respectively to the output of the inverter 10 and the input of the load 14, the output of which is connected to the first input (input 1) of the inverter 10.

The output of DNVS 1 is connected to the second input 3.2 of the first SUM 3. DNVS 1 is additionally equipped with a voltage rectifier voltage input. In figure 1, the rectifier network is not shown. The input and output of the DVT 13 are connected respectively to the first output 12.1 of the DTI 12 and the second input 4.2 of the second SUM 4. The first 11.1, second 11.2 inputs and outputs of the FSI 11 are connected respectively to the output of the comparator 8, the second output 2.2 of CVI 2 and the second input (input 2 ) of the inverter 10. The input and output of the DPVN 9 are connected respectively to the first output (7.1) of VK 7 and the input of the HPF 6, the output of which is connected to the third input 3.3 of the first adder. The first 7.1 and second 7.2 outputs of VK 7 are connected respectively to the third (input 3) and fourth (input 4) inputs of the inverter 10.

DNVS 1 is designed to highlight the ripple voltage and can be implemented according to the capacitive divider.

WPM 2 is designed to receive a signal from an external current control system in the EMC (in the demagnetization windings) and is an operational amplifier with galvanic isolation, for example, type AD215A, described on the website www.analog.com.

The first SUM 3 is designed to generate a control signal of the load current through the voltage feedback loop and can be implemented on an operational amplifier according to the standard “addition – subtraction” scheme described in L. Falkenberry's book “The Use of Operational Amplifiers and Linear ICs”. - M .: Mir, 1985, p. 110.

The second SUM 4 is designed to generate a control signal of the load current through the current feedback circuit and can be implemented on an operational amplifier according to the standard scheme described in the book of L. Falkenberry, p.110.

Phase shifting PWM converter 5 is designed to control the load current in amplitude and can be performed according to the well-known scheme described, for example, in the book "Microcircuits for switching power supplies and their application." - M .: ed. DODEKA, 1997, p. 179.

The high-pass filter 6 is designed to isolate the ripple voltage with a frequency of up to 300 Hz or more and can be performed according to the standard scheme.

VK7 is designed to rectify the voltage of the PWM converter 5 of the inverter 10 with a frequency of 20 kHz or more and can be performed according to a standard bridge or half-wave circuit.

The comparator 8 is designed to generate a signal about the zero current in the load, which can be implemented according to the well-known scheme "zero - an organ with hysteresis" described in the book of L. Falkenberry, p.235.

DPVN 9 is designed to reduce the voltage level. As such a sensor, a resistive divider can be used.

FSI 11 is designed to change the direction of flow of the load current and it can be implemented according to the scheme of the operational amplifier "addition - subtraction" described in the book of L. Falkenberry, p.110.

DTI 12 is designed to receive a signal about the magnitude of the current in the load. As DTI 12, a typical shunt (low resistance calibrated resistor) can be used.

DVT 13 is designed for rectification and scaling of the current amplitude and can be implemented according to a standard scheme with a time constant of a few hertz units.

The load 14 in General terms represents the outer windings with sectioning, which are made of a conductive cable, and are predominantly inductance L up to 600 mH with resistance R from units of Ohms to 30 Ohms.

Inverter 10 is designed to change the polarity of the current in the load. Schemes for constructing such inverters are known and, in particular, can be implemented according to the circuit shown in figure 2.

The inverter 10 shown in figure 2, is made according to a bridge circuit with transistors and consists of the first 10.1 and second 10.2 gate power sources (IPZ) of the first 10.5 and second 10.7 transistors of the upper half-bridge arms, the third 10.10 gate power source, the third 10.6 and fourth 10.8 transistors of the lower shoulders of the half-bridge, the first 10.3 and second 10.4 half-bridge drivers and logical inverter (LI) 10.9.

The output of the first IP3 10.1 is connected to the first input of the first driver 10.3, the second input of which is connected to the first output of the third IPZ 10.10. The first and second outputs of the first 10.3 and second 10.4 drivers are connected respectively to the first inputs of the first 10.5, second 10.7 and third 10.6, fourth 10.8 bridge transistors. The output of the second 10.2 and the second output of the third 10.10 IPZ are connected respectively to the first and second inputs of the second driver 10.4. The gate inputs of the first 10.5 and second 10.7, third 10.6 and fourth 10.8 transistors are paired and are respectively the fourth (input 4) and third (input 3) inputs of the inverter 10. The outputs of the first 10.5 and third 10.6, as well as the second 10.7 and fourth 10.8 transistors are paired and are respectively the output and the first input (input 1) of the inverter 10. The third input of the second driver 10.4 is connected to the output of the logical inverter 10.9, the input of which is connected to the third input of the first driver 10.3 and is the second input (input 2) of the inverter 10 .

The claimed device operates as follows.

WPI 2 generates a direct current signal I _s , the magnitude and polarity of which depend on the current control signal at load 14 (in particular, in the demagnetization windings of the ship) received at the input of WPI 2. The signal at the first output 2.1 of WPI 2, corresponding to the value of the current magnitude module | I _s |, arrives simultaneously at the first inputs 3.1 and 4.1 of the first 3 and second 4 adders. At the second output 2.2 of CVI 2, the signal corresponding to the sign of the direction of the current "plus" or minus "is fed to the second input 11.2 of the FSI 11. Serially connected to the current inputs / outputs of the first SUM 4, phase shifting PWM converter 5, VK 7, inverter 10, DTI 12 and DVT 13 form a current feedback circuit, with which the output current (I _n ) in the load is monitored.

The resulting current error signal ΔI = I _s -I _n at its negative value, i.e. ΔI <0, is additionally fed to the input of the comparator 8, which compares it with a predetermined threshold level I _then supplied to the inverse input of the comparator 8. From the input of the comparator 8, the difference signal is fed to the first input 11.1 of the FSI 11. Provided that the second input 11.2 of the FSI 11 of the signal from the second output 2.2 of the WPI 2, the differential signal from the output of the FSI 11 is fed to the first input 10.1 of the inverter 10, which generates a signal through DTI 12 to change the direction of the current in the load 14.

In addition, the DPVN 9, HPF 6 and the first SUM 3 connected at the input / output voltages 3 connected to the VK 7 output form a voltage feedback circuit whose output (output of the first SUM 3) is connected to the first input of the 5.1 phase-shifting PWM converter 5. This ensures the required depth of suppression of the arising ripples and interference of the network of fixed DVNS 1 and arriving at the second input 3.2 with a frequency band of several kHz.

In the claimed device, the control of the inverter 10 is carried out both directly by the input signal, and by the signal generated under the condition ΔI <0, which avoids the excitation of the PM when working on an inductive load and, therefore, expand the dynamic range of adjustment of the current in it.

A voltage from VK 7 is applied to one diagonal of the inverter 10 bridge circuit, and a load 14 is included in the second diagonal. Transistors 10.5-10.8 are controlled using the drivers 10.3 and 10.4 of the corresponding half-bridges, the power to the first inputs of which is supplied respectively from isolated power sources 10.1 and 10.2 .

The change in the direction of the current flow in the load 14 is produced by switching transistors 10.5 and 10.8 or 10.6 and 10.7. The inverter 10, implemented according to this scheme, remains operational when controlling direct current.

The introduction of a voltage feedback loop provides the ability to suppress ripple current in the load. In this case, the passband of the voltage feedback loop is 3-5 kHz with ripple suppression with a frequency of 300 Hz. This possibility was realized by introducing DNVS 1, the output of which is connected to the second input 3.2 of the first SUM 3.

Thus, thanks to a new set of essential features when using the claimed IP EMC, the specified technical result is achieved.

Claims (1)

The power supply of electromagnetic compensators, containing a source of a driving action, equipped with a signal input, and the first output of which is connected to the first inputs of the first and second adders, the outputs of which are connected respectively to the first and second inputs of the phase-shifting PWM converter, the output and second input of which are connected respectively to the input converter rectifier and a comparator input equipped with an inverse input, an inverter current sensor, the input and second output of which are connected respectively to the inverter output to the input of the load, the output of which is connected to the first input of the inverter, characterized in that an additional voltage rectifier voltage sensor is introduced, the output of which is connected to the second input of the first adder, an output current detector, the input and output of which are connected respectively to the first output of the inverter current sensor and the second the input of the second adder, the driver of the inverter signal, the first, second inputs and the output of which are connected respectively to the output of the comparator, the second output of the source of the set action and the second input an inverter, an output voltage ripple sensor, the input and output of which are connected respectively to the first output of the converter rectifier and the input of a high-pass filter, the output of which is connected to the third input of the first adder, the first and second outputs of the converter rectifier connected to the third and fourth inputs of the inverter, respectively.

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