RU2397552C1 - Liquid-crystal display (lcd) panel and pixel control device - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: pixel control device (120) for the liquid-crystal display (LCD) panel (1) includes first and second transistors (Ta, Tb) and first and second storage capacitors (CstA, CstB). The second transistor (Tb) has a gate electrode (G) which is connected to the gate electrode (G) of the first transistor (Ta), and a drain electrode (D) which is connected to the drain electrode (D) of the first transistor (Ta). The first storage capacitor (CstA) has a terminal (104) which is connected to the source electrode (S) of the first transistor (Ta). The second storage capacitor (CstB) has a first terminal (107) which is connected to the source electrode (S) of the second transistor (Tb), and a second terminal (103) which is connected to the gate electrode (G) of the first transistor (Ta) of a pixel control device (120) in another pixel row of the LCD panel (1).

EFFECT: reduced colour shift, wider viewing angle, simple design.

23 cl, 12 dwg

Description

FIELD OF THE INVENTION

This invention relates to a liquid crystal display panel (LCD), and more particularly, to a pixel control device for an LCD panel.

State of the art

1 illustrates a conventional liquid crystal display panel (LCD), such as an LCD with a twisted nematic structure (TN, CH), which includes a substrate 10 of thin film transistors (TFT, TFT), a substrate 20 of a color filter 20 and a layer 30 of liquid molecules crystals between the TPT substrate 10 and the color filter substrate 20. During operation, when the voltage (V) is applied through the pixel electrode layer 11 on the TFT substrate 10 and the common electrode layer 12 on the color filter substrate 20, the liquid crystal molecules in the layer 30 of liquid crystal molecules are aligned in a certain direction, thereby controlling the phase delay of the layer 30 liquid crystal molecules relative to a ray of light. In this state, when a pair of light rays (LI, L2), between which there is an angle θ, passes through a layer 30 of liquid crystal molecules, light rays (LI, L2) receive different phase delays and therefore have different brightness levels. In this case, when the angle at which the conventional LCD panel is viewed changes, the brightness displayed in the conventional LCD panel also changes, resulting in a color shift problem.

As can be seen in figure 2, a conventional LCD panel has different γ-curves of the coefficient (A, B, C) at zero degrees, forty-five degrees and sixty degrees of the viewing angle. This means that a conventional LCD panel has a color shift problem at tilted viewing angles, and therefore has a narrow viewing angle.

To expand the viewing angle, LCD panels with switching in the plane (IPS, PVP) and LCD panels with multi-domain vertical alignment (MVA, MVV) were developed.

As shown in FIGS. 3 and 4, a conventional MVV LCD panel includes a TPT substrate 31 and a color filter substrate 32, on each of which a transparent conductive electrode 33, 38 is formed. A transparent conductive electrode 33 on the TPT substrate 31 is formed with a gap of 34 mute, by means of which a transparent conductive electrode 33 is divided into a pair of electrode elements 35, 36. A transparent conductive electrode 38 on a color filter substrate 32 is formed with a rib 37 on it. This design also allows the orientation of liquid crystal molecules in different directions and, thus, extends the viewing angle of a conventional LCD panel. However, since an electric field 39 is generated between the transparent conductive electrodes 33, 38, which undesirably affects the orientation of the liquid crystal molecules, the color-shift problem of the LCD LCD panel is also inherent when viewed at relatively wide viewing angles.

Various conventional pixel control devices have been proposed to reduce color shift of a conventional MVV LCD panel. One of the conventional pixel control devices, as shown in FIG. 5, includes a TFT 51, a storage capacitor 52, a separation capacitor 53, and first and second liquid crystal capacitors 54, 55. Each of the storage capacitor 52 and the separation capacitor 53 controls a respective one of the first and second liquid crystal capacitors 54, 55. Elements 35, 36 of the electrodes, a transparent conductive electrode 38, and liquid crystal molecules in FIG. 3 comprise the first and second liquid crystal capacitors 54, 55. During operation, when the TFT 51 is turned on, the storage capacitor 52 is charged and, in turn, charges the isolation capacitor 53. As a result, the first and second liquid crystal capacitors 54, 55 provide different γ-curves, thus providing color shift compensation. However, since the separation capacitor 53 needs to be charged using the storage capacitor 52, appropriate color shift compensation cannot be provided. In addition, a conventional pixel control device may result in image retention on the MVV LCD panel.

Another conventional pixel control device, as shown in FIG. 6, includes a first and second TFT 61, 62, first and second storage capacitors 63, 64, and first and second liquid crystal capacitors 65, 66. Each of the first and second storage capacitors 63, 64 is connected to the corresponding one of the common lines (VcomA, VcomB). Alternatively, as shown in FIG. 7, each of the first and second TFT 61, 62 may be connected to a respective one of the scan lines (GateA, GateB). During operation, when different voltages are applied to common lines (VcomA, VcomB), the first and second storage capacitors 63, 64 generate different voltages. As a result, the first and second liquid crystal capacitors 65, 66 provide different gamma curves. Although this solution reduces the problem of color shift, an increased number of common lines (VcomA, VcomB) or scan lines (GateA, GateB) complicates the design of a conventional pixel control device.

SUMMARY OF THE INVENTION

Therefore, the main objective of the present invention is to provide a liquid crystal display panel (LCD) that overcomes the above-described disadvantages of the prior art.

Another objective of the present invention is to provide a pixel control device that overcomes the above-described disadvantages of the prior art.

In accordance with an aspect of the present invention, pixel control devices for a liquid crystal display panel (LCD) comprise first and second transistors and first and second storage capacitors. The LCD panel includes a plurality of first liquid crystal capacitors and a plurality of second liquid crystal capacitors. The first transistor has a gate electrode, a drain electrode and a source electrode, configured to connect them to the corresponding one of the first liquid crystal capacitor. The second transistor has a gate electrode connected to a gate electrode of the first transistor, a drain electrode connected to a drain electrode of the first transistor, and a source electrode configured to connect it to a corresponding one of the second liquid crystal capacitor. The first storage capacitor has a capacitor terminal connected to the source electrode of the first transistor. The second storage capacitor has a first capacitor terminal connected to the source electrode of the second transistor, and a second capacitor electrode configured to connect a pixel control device in a different row of pixels of the LCD panel to the gate electrode of the first transistor.

In accordance with another aspect of the present invention, a liquid crystal display panel (LCD) comprises a plurality of first liquid crystal capacitors, a plurality of second liquid crystal capacitors, and a plurality of pixel row control devices. Each of the pixel row control devices includes first and second transistors and first and second storage capacitors. The first transistor has a gate electrode, a drain electrode and a source electrode connected to a respective one of the first liquid crystal capacitors. The second transistor has a gate electrode connected to a gate electrode of the first transistor, a drain electrode connected to a drain electrode of the first transistor, and a source electrode connected to a corresponding one of the second liquid crystal capacitors. The first storage capacitor has a capacitor terminal connected to the source electrode of the first transistor. The second storage capacitor has a first capacitor terminal connected to a source electrode of the second transistor and a second capacitor terminal. The second terminal of the capacitor of the second storage capacitor of each of the pixel control devices in one of the rows is connected to the gate electrode of the first transistor of the pixel control devices in another one of the rows.

In accordance with another aspect of the present invention, the transistor substrate comprises a transparent substrate element, an electrode layer, a plurality of first transistors, a plurality of second transistors, a plurality of first storage capacitors and a plurality of second storage capacitors. The transparent backing element defines a plurality of rows consisting of pixel regions. The electrode layer is divided into a plurality of first electrode regions, each of which is located in a respective one of the pixel regions, and a plurality of second electrode regions, each of which is located in a corresponding one of the pixel regions. Each of the first transistors is located in one of the pixel regions and has a gate electrode, a drain electrode, and a source electrode connected to the first region of the electrode in a corresponding one of the pixel regions. Each of the second transistors is located in a respective one of the pixel regions and has a gate electrode connected to a gate electrode of the first transistor in a corresponding one of the pixel regions and a source electrode connected to a second region of the electrode in a corresponding one of the pixel regions. Each of the first storage capacitors is located in the corresponding one of the pixel regions, connected to the first electrode region in the corresponding one of the pixel regions and has a capacitor terminal connected to the source electrode of the first transistor in the corresponding one of the pixel regions. Each of the second storage capacitors is located in the corresponding one of the pixel regions, connected to the second electrode region in the corresponding one of the pixel regions and has a first capacitor terminal connected to the source electrode of the second transistor in the corresponding one of the pixel regions and a second capacitor terminal. The second capacitor terminal of the second storage capacitor in each of the pixel regions in one of the rows is connected to the gate electrode of the first transistor in one of the pixel regions in another one of the rows.

In accordance with another aspect of the present invention, a liquid crystal display panel (LCD) comprises a transistor substrate and a color filter substrate. The transistor substrate includes a transparent substrate element, an electrode layer, a plurality of first transistors, a plurality of second transistors, a plurality of first storage capacitors and a plurality of second storage capacitors. The transparent backing element defines a plurality of rows of pixel regions. The electrode layer is divided into a plurality of first electrode regions, each of which is located in a respective one of the pixel regions, and a plurality of second electrode regions, each of which is located in a corresponding one of the pixel regions. Each of the first transistor is located in a respective one of the pixel regions and has a gate electrode, a drain electrode, and a source electrode connected to the first region of the electrode in a corresponding one of the pixel regions. Each of the second transistors is located in one of the pixel regions and has a gate electrode connected to the gate electrode of the first transistor in the corresponding one of the pixel regions and a source electrode connected to the second region of the electrode in the corresponding one of the pixel regions. Each of the first storage capacitors is located in the corresponding one of the pixel regions, connected to the first electrode region in the corresponding one of the pixel regions and has a capacitor terminal connected to the source electrode of the first transistor in the corresponding one of the pixel regions. Each of the second storage capacitors is located in the corresponding one of the pixel regions, connected to the second electrode region in the corresponding one of the pixel regions and has a first capacitor terminal connected to the source electrode of the second transistor in the corresponding one of the pixel regions and a second capacitor terminal. The second capacitor terminal of the second storage capacitor in each of the pixel regions in one of the rows is connected to the gate electrode of the first transistor in one of the pixel regions in another one of the rows. The color filter substrate is located on the transistor substrate.

Brief Description of the Drawings

Other features and advantages of the present invention will be apparent from the following detailed description of a preferred embodiment of the invention with reference to the accompanying drawings, in which:

figure 1 shows a diagram of a conventional panel liquid crystal display (LCD);

figure 2 is a graph illustrating the γ-curves of a conventional LCD panel;

figure 3 - diagram of a conventional LCD panel with multi-domain vertical alignment (MVV);

4 is a diagram illustrating a slot formed in a transparent conductive electrode of a conventional MVV LCD panel;

5-7 are diagrams of conventional pixel control devices;

8 is a schematic diagram of a preferred embodiment of an LCD panel in accordance with the present invention;

Fig.9 is a fragment with a private section illustrating a pixel control device of a preferred embodiment;

figure 10 is a fragment with a partial section along the line aa in figure 9;

11 is a schematic diagram of a pixel control device in accordance with a preferred embodiment; and

12 is a graph illustrating gamma curves of a preferred embodiment.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 8-10 show a preferred embodiment of a liquid crystal display panel (LCD) 1 according to the present invention, which includes a thin film transistor (TFT) substrate 100 and a color filter substrate 200.

In this embodiment, the LCD panel 1 is a multi-domain vertical alignment (MVV) LCD panel

The TFT substrate 100 includes a transparent substrate element 101, an electrode layer 500, and a plurality of pixel control devices 120.

The LCD panel 1 further includes a plurality of parallel scan lines (Gate1-GateN) that are located on the transparent substrate element 101, a plurality of parallel data lines (Data1-DataN) that are located on the transparent substrate element 101 and which intersect the scan lines (Gate1- GateN), thus defining a plurality of rows of pixel regions and a plurality of common lines (Vcom1-VcomN) that are located on the transparent substrate element 101.

The electrode layer 500 of the TFT substrate 100 is divided into a plurality of first electrode regions 502, each of which is located in a respective one of the pixel regions, and a plurality of second electrode regions 503, each of which is located in a corresponding one of the pixel regions. In this embodiment, the layer 500 of the substrate electrode 100 of the TPT is made of indium tin oxide (ITO, OIO).

Each of the pixel control devices 120 is located in a respective one of the pixel regions. Since the pixel control devices 120 are identical in design, only the pixel control device 120 in one of the pixel regions, for example, in the pixel region (Pn), in the Nth row of pixel regions will be described here.

With further reference to FIG. 11, it can be seen that the pixel control device 120 includes first and second transistors (Ta, Tb) and first and second storage capacitors (CstA, CstB).

The first transistor (Ta) is located proximally to the junction of the scan line (GateN) and the data line (DataN) and has a gate electrode (G) connected to the scan line (GateN), a drain electrode (D) connected to the data line (DataN) and the electrode (S) a source connected to the first region 502 of the electrode in the region (Pn) of the pixel.

The second transistor (Tb) has a gate electrode (G) connected to the scan line (GateN), a drain electrode (D) connected to the data line (DataN), and a source electrode (S) connected to the second electrode region 503 in the region ( Pn) pixels.

In this embodiment, each of the first and second transistors (Ta, Tb) is a TFT. In an alternative embodiment, each of the first and second transistors (Ta, Tb) is a complementary metal oxide semiconductor (CMOS, CMOS) transistor when the LCD panel is a reflective type panel.

The first storage capacitor (CstA) has a first capacitor terminal 104 connected to a source electrode (S) of a first transistor (Ta), and a second capacitor terminal 102 connected to a common line (VcomN).

It should be noted that the first terminal 104 of the capacitor of the first storage capacitor (CstA) is connected to the source electrode (S) of the first transistor (Ta) through the conductive wire module 108, as best shown in FIG. 9. The design also reduces the resistance between the first storage capacitor (CstA) and the first transistor (Ta) without affecting the degree of transfer of the layer 500 of the substrate electrode 100 TFT.

In an alternative embodiment, the first capacitor terminal 104 of the first storage capacitor (CstA) is connected to the source electrode (S) of the first transistor (Ta) through a conductive hole module.

The second storage capacitor (CstB) is located at a distance from the first storage capacitor (CstA) and is located proximally to the scan line (GateN-1). In such an embodiment, the second storage capacitor (CstB) has a first capacitor terminal 107 connected to a source electrode (S) of a second transistor (Tb), and a second capacitor terminal 103 connected to a scan line (GateN-1).

In an alternative embodiment, the second storage capacitor (CstB) is located proximally to the scan line (GateN + 1) and its second capacitor terminal 103 is connected to the scan line (GateN + 1).

The first terminal 107 of the capacitor of the second storage capacitor (CstB) is connected to the source electrode (S) of the second transistor (Tb) through the conductive hole port module 105, as best shown in FIG.

The color filter substrate 200 includes a transparent substrate element 210, and an electrode layer 201 located on the transparent substrate element 210. In such an embodiment, the layer 201 of the electrode of the color filter substrate 200, as well as the layer 500 of the electrode of the TPT substrate 100, is made of indium tin oxide (OIO).

The color filter substrate 200 is located on the TFT substrate 100 so that a portion of the liquid crystal layer is located between the electrode layer 201 of the color filter substrate 200 and the first electrode region 502 of the layer 500 of the TFT substrate 100, so that a first liquid crystal capacitor (ClcA) is formed between them, and so that the remaining portion of the layer of liquid crystal molecules is located between the layer 201 of the electrode of the color filter substrate 200 and the second electrode region 503 of the layer 500 of the substrate electrode 100 of the TFT, so that in between a second capacitor (ClcB) of liquid crystals is formed.

The first liquid crystal capacitor (ClcA) is connected to the source electrode (S) of the first transistor (Ta), while the second liquid crystal capacitor (ClcB) is connected to the source electrode (S) of the second transistor (Tb).

The LCD panel 1 further includes a shutter control circuit 300 and a data control circuit 400. The gate control circuit 300 is connected to the scan line (Gate1-GateN) and controls, that is, activates, the scan lines (Gate1-GateN) in series. The data management circuit 400 is connected to the data lines (Data1-DataN) and controls, i.e. sequentially controls, the pixels of the data line (Data1-DataN).

It should be noted that during operation, a voltage of 0 volts is applied to the common line (Vcoml-VcomN). In addition, a voltage of 5 volts is applied to the data line (Data1-DataN) when the data line (Data1-DataN) is activated. In addition, a voltage of 15 volts / 1 volt is applied to the scan line (Gate1-GateN) when the scan line (Gatel-GateN) is activated / deactivated.

During operation, when the scan line (GateN) and the data line (DataN) are activated, each of the first and second transistors (Ta, Tb) is in the open state and each of the first and second storage capacitors (CstA, CstB) is charged with a voltage of 5 volts on the data line (DataN) through the corresponding one of the first and second transistors (Ta, Tb). In this state, since the common line (VcomN) has a voltage of 0 volts, the first storage capacitor (CstA) may have a voltage of 5 volts. At the same time, since the scan line (GateN-1) is deactivated and has a voltage of 1 volt, the second storage capacitor (CstB) can have a voltage of 4 volts. Moreover, since the voltages of the first and second storage capacitors (CstA, CstB) are different from each other, as shown in Fig. 12, the first and second capacitors (C1cA, C1cB) of liquid crystals have different γ-curves (La, Lb), when summing which yields the γ-curve Lc. This means that in the LCD panel 1 in accordance with the present invention, the problem of color shift (or color washout) is reduced.

Thus, it has been shown that the pixel control device 120 in accordance with the present invention reduces the color shift problem that is usually observed at wide viewing angles without increasing the number of scan lines or data lines, and therefore has a relatively simple construction.

Although the present invention has been described in connection with what is considered to be the most practical and preferred embodiment, it should be understood that the present invention is not limited to the disclosed embodiment, but is intended to cover the various arrangements included in the essence and scope of the broadest interpretation that encompass all such modifications and equivalent arrangements.

Claims (23)

1. A pixel control device (120) for a liquid crystal display (LCD) panel (1), wherein the LCD panel (1) includes a plurality of first liquid crystal capacitors (ClcA) and a plurality of second liquid crystal capacitors (ClcB), said device (120) the pixel control comprises a first transistor (Ta) having a gate electrode (G), a drain electrode (D) and a source electrode (S) configured to connect liquid crystals to one of the first capacitors (ClcA);
a second transistor (Tb) having a gate electrode (G) connected to said gate electrode (G) of said first transistor (Ta), a drain electrode (D) connected to said drain electrode (D) of said first transistor (Ta), and a source electrode (S) configured to be connected to a respective one of the second liquid crystal capacitors (ClcB); a first storage capacitor (CstA) having a capacitor terminal (104) connected to said source electrode (S) of said first transistor (Ta); and
a second storage capacitor (CstB) having a first capacitor terminal (107) connected to said source electrode (S) of said second transistor (Tb), and a second capacitor terminal (103) configured to connect a gate of said gate to said electrode (G) the first transistor (Ta) of said pixel control device (120) in another row of pixels of the LCD panel (1). 2. The pixel control device (120) according to claim 1, wherein said second capacitor terminal (103) of said second storage capacitor (CstB) is configured to connect to said gate electrode (G) of said first transistor (Ta) of said device ( 120) managing pixels in one of the previous row of pixels and the next row of pixels of the LCD panel (1). 3. The pixel control device (120) according to claim 1, wherein at least one of said first and second transistors (Ta, Tb) is one of a thin film transistor (TFT) and a complementary metal oxide semiconductor (CMOS) transistor. 4. The pixel control device (120) according to claim 1, wherein a high level voltage is applied to said gate electrode (G) of said first transistor (Ta), and a low level voltage is applied to it in other cases, said the first storage capacitor (CstA) further has a second capacitor terminal (102) to which a voltage other than a low level voltage is applied. 5. The panel (1) of a liquid crystal display (LCD), containing
a plurality of first liquid crystal capacitors (ClcA);
a plurality of second liquid crystal capacitors (ClcB); and
a plurality of rows of pixel control devices (120), each of which pixel control devices (120) includes
a first transistor (Ta) having a gate electrode (G), a drain electrode (D) and a source electrode (S) connected to a respective one of said first liquid crystal capacitors (ClcA),
a second transistor (Tb) having a gate electrode (G) connected to said gate electrode (G) of said first transistor (Ta), a drain electrode (D) connected to said drain electrode (D) of said first transistor (Ta), and a source electrode (S) connected to a respective one of said second liquid crystal capacitors (ClcB),
a first storage capacitor (CstA) having a capacitor terminal (104) connected to said source electrode (S) of said first transistor (Ta), and
a second storage capacitor (CstB) having a first capacitor terminal (107) connected to said source electrode (S) of said second transistor (Tb), and a second capacitor terminal (103),
said second capacitor terminal (103) of said second storage capacitor (CstB) of each of said pixel control devices (120) in one of the rows is connected to said gate electrode (G) of said first transistor (Ta) of said pixel control devices (120) in another one of the rows. 6. The LCD panel (1) according to claim 5, wherein said another one of the rows of said pixel control devices (120) precedes said one of the rows of said pixel control devices (120). 7. The LCD panel (1) according to claim 5, wherein said another one of the rows of said pixel control devices (120) follows said one of the rows of said pixel control devices (120). 8. The LCD panel (1) according to claim 5, in which at least one of the first and second transistors (Ta, Tb) is one of a thin film transistor (TFT) and a complementary metal oxide semiconductor (CMOS) transistor. 9. The LCD panel (1) according to claim 5, in which a high level voltage is applied to said gate electrode (G) of said first transistor (Ta), and a low level voltage is applied to it in another case,
said first storage capacitor (CstA) further has a second capacitor terminal (102) to which a voltage other than a low level voltage is applied. 10. The substrate (100) of the transistors containing
a transparent substrate element (101) defining a plurality of rows of pixel regions;
an electrode layer (500) divided into a plurality of first electrode regions (502), each of which is located in a respective one of said pixel regions, and a plurality of second electrode regions (503), each of which is located in a corresponding one of said pixel regions;
a plurality of first transistors (Ta), each of which is located in a respective one of said pixel regions, each of said first transistors (Ta) having a gate electrode (G), a drain electrode (D) and a source electrode (S) connected to said first region (502) of the electrode in a corresponding one of said pixel regions;
a plurality of second transistors (Tb), each of which is located in a respective one of said pixel regions, of each of said second transistors (Tb) having a gate electrode (G) connected to said gate electrode (G) of said first transistor (Ta) in a corresponding one of said pixel regions, and a source electrode (S) connected to said second electrode region (503) in a corresponding one of said pixel regions;
a plurality of first storage capacitors (CstA), each of which is located in a respective one of said pixel regions and connected to said first electrode region (502) in a corresponding one of said pixel regions, each of said first storage capacitors (CstA) has an output (104 ) a capacitor connected to said source electrode (S) of said first transistor (Ta) in a corresponding one of said pixel regions; and
a plurality of second storage capacitors (CstB), each of which is located in a respective one of said pixel regions and connected to said second electrode region (503) in a corresponding one of said pixel regions, each of said second storage capacitors (CstB) has a first output ( 107) a capacitor connected to said source electrode (S) of said second transistor (Tb) in a corresponding one of said pixel regions, and a second capacitor terminal (103), said second terminal (103) a capacitor of said second storage capacitor (CstB) in each of said pixel regions in one of the rows is connected to said gate electrode (G) of said first transistor (Ta) in one of said pixel regions in another one of the rows. 11. The transistor substrate (100) of claim 10, wherein said another one of the rows of said pixel regions precedes said one of the rows of said pixel regions, and each of said second storage capacitors (CstB) is located proximally to said other one of the rows of said regions pixels. 12. The transistor substrate (100) of claim 10, wherein said another one of the rows of said pixel regions follows after said one of the rows of said pixel regions, and each of said second storage capacitors (CstB) is located proximally to said other one of the rows of said pixel areas. 13. The substrate (100) of the transistors of claim 10, wherein at least one of the first and second transistors (Ta, Tb) is one of a thin film transistor (TPT) and a complementary metal oxide semiconductor (CMOS) transistor. 14. The substrate (100) of the transistors of claim 10, further comprising a module (105) of an electrically conductive passage through which a connection is established between said source electrode (S) of each of said second transistors (Tb) and said first capacitor terminal (107) of the corresponding one of said second storage capacitors (CstB). 15. The panel (1) of a liquid crystal display (LCD) containing a substrate (100) of transistors, including
a transparent substrate element (101) defining a plurality of rows of pixel regions,
an electrode layer (500) divided into a plurality of first electrode regions (502), each of which is located in a respective one of said pixel regions, and a plurality of second electrode regions (503), each of which is located in a corresponding one of said pixel regions,
a plurality of first transistors (Ta), each of which is located in a respective one of said pixel regions, each of said first transistors (Ta) has a gate electrode (G), a drain electrode (D) and a source electrode (S) connected to said first area (502) of the electrode in the corresponding one of the mentioned areas of the pixel,
a plurality of second transistors (Tb), each of which is located in a respective one of said pixel regions, each of said second transistors (Tb) has a gate electrode (G) connected to said gate electrode (G) of said first transistor (Ta) in a corresponding one of said pixel regions, and a source electrode (S) connected to said second electrode region (503) in a corresponding one of said pixel regions,
a plurality of first storage capacitors (CstA), each of which is located in a respective one of said pixel regions and connected to said first electrode region (502) in a corresponding one of said pixel regions, each of said first storage capacitors (CstA) has an output (104 ) a capacitor connected to said source electrode (S) of said first transistor (Ta) in a corresponding one of said pixel regions, and
a plurality of second storage capacitors (CstB), each of which is located in a respective one of said pixel regions and connected to said second electrode region (503) in a corresponding one of said pixel regions, each of said second storage capacitors (CstB) has a first output ( 107) a capacitor connected to said source electrode (S) of said second transistor (Tb) in a corresponding one of said pixel regions, and a second capacitor terminal (103), said second terminal (103) a capacitor of said second storage capacitor (CstB), in each of said pixel regions in one of the rows, connected to said gate electrode (G) of said first transistor (Ta) in one of said pixel regions in another one of the rows; and
a color filter substrate (200) located on said transistor substrate (100). 16. The LCD panel (1) according to claim 15, wherein said transistor substrate (100) further includes a conductor module (108), said capacitor terminal (104) of each of said first storage capacitors (CstA) being connected to said electrode (S) the source of the corresponding one of said first transistors (Ta) through said conductor module (108). 17. The LCD panel (1) according to claim 15, further comprising a layer of liquid crystal molecules located between said transistor substrate (100) and said color filter substrate (200). 18. The LCD panel (1) according to claim 17, wherein said color filter substrate (200) includes a transparent substrate element (210) and an electrode layer (201) located on said transparent substrate element (210),
a portion of said layer of liquid crystal molecules is located between said electrode layer (201) of said color filter substrate (200) and said first electrode regions (502) of said electrode layer (500) of said transistor substrate (100) to form first liquid crystal capacitors (ClcA) connected to said electrodes (S) of the source of said first transistors (Ta), respectively,
the remaining portion of said layer of liquid crystal molecules is located between said electrode layer (201) of said color filter substrate (200) and said second electrode regions (503) of said electrode layer (500) of said transistor substrate (100) to form second liquid capacitors (ClcB) crystals connected to said source electrodes (S) of said second transistors (Tb), respectively. 19. The LCD panel (1) according to claim 15, wherein said first storage capacitor (CstA) is located under said first electrode region (502) in a respective one of said pixel regions of said electrode layer (500), and said second storage capacitor ( CstB) is located under said second electrode region (503) in a corresponding one of said pixel regions of said electrode layer (500). 20. The LCD panel (1) according to Claim 15, wherein said other one of the rows of said pixel regions precedes said one of the rows of said pixel regions, and each of said second storage capacitors (CstB) is located proximally to said other one of the rows of said regions pixels. 21. The LCD panel (1) according to claim 15, wherein said another one of the rows of said pixel regions follows after said one of the rows of said pixel regions, and each of said second storage capacitors (CstB) is positioned proximally to said other one of the rows of said pixel areas. 22. The LCD panel (1) according to claim 15, wherein at least one of the first and second transistors (Ta, Tb) is one of a thin film transistor (TFT) and a complementary metal oxide semiconductor (CMOS) transistor. 23. The LCD panel (1) according to claim 15, wherein said transistor substrate (100) further includes a conductive hole port module (105) through which a connection is established between said source electrode (S) of each of said second transistors (Tb ) and said first output (107) of the capacitor of the corresponding one of said second storage capacitors (CstB).

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