RU2353053C1 - Digit-to-analogue conversion method for sub-sampling bandpass signals and associated device (versions) - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: invention relates to signal processing systems where digit-to-analogue conversion is used. The specific feature of digit-to-analogue conversion method for sub-sampling bandpass signals is that input binary values are replaced with zero values or binary signal values corresponding to the difference between the maximum nominal value of output signal and input binary signal value valid for the first half of sampling period when bit signals are summed in single-step weighted manner with weights serially decreased with 1/2 factor for each next low-order bit of the input n-bit binary code of signal sampling during the second half of each sampling period.

EFFECT: reduced distortions during digit-to-analogue conversion.

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Description

The invention relates to the so-called hybrid signal processing systems that use the transition from an analog waveform to digital (analog-to-digital conversion) and the reverse transition from a digital waveform to analog (digital-to-analog conversion).

There are many implementations of these transformations, but for the conversion of broadband or strip signals, as a rule, a parallel analog-to-digital conversion circuit is used, in which an analog signal is fed simultaneously to many comparators, each of which is configured to one of the possible signal levels, and logic outputs comparators are subjected to appropriate processing to obtain binary codes expressing the instantaneous value of the signal. An analog-to-digital converter (ADC) essentially performs three processing operations — sampling, or taking samples of the input analog signal, quantizing them by level, and expressing these quantized values as binary words (codes).

Digital-to-analogue signal conversion is known and widely used, carried out by weighted summation of bit currents turned on (or not turned on) by input binary codes supplied in parallel form, i.e. simultaneously to all digital (bit) inputs of the converter. In this way, all modern integrated digital-to-analog converters (DACs) are implemented, although they may vary by specific circuitry. The general circuits of the described ADCs and DACs are given in [1-3].

As follows from the sampling theorem of V.A. Kotelnikov, the necessary sampling frequency of the signal should be no less than twice the value of the upper frequency in its spectrum. In practice, a sampling frequency that exceeds the theoretical value by at least 20% is used.

During digital-to-analog conversion, the values of digital codes expressing the values of successive samples of a signal are stored for a period of samples and converted to analog voltage, and a step-shaped signal is generated at the output of the DAC, i.e. the so-called interpolation of the zero order of the reference values of the signal is carried out. Thus, digital-to-analog conversion is performed with distortion. To eliminate this distortion, the resulting step-by-step analog signal should be subjected to low-pass filtering and amplitude-frequency correction (the so-called sine correction).

When sampling strip signals, which include almost all radio signals, a special form of the sampling theorem can be used, which can significantly reduce the required sampling frequency, and thereby reduce the requirements for the converter and, accordingly, reduce the output digital stream. Such sub-sampling of band signals is described in [4].

Sub-sampling of band signals is used, in particular, in analog-to-digital conversion of intermediate frequency signals of microwave and satellite communication systems, which in many cases is 70 MHz with a frequency band of up to ± 20 MHz. For direct sampling of such signals, a frequency of about 200 MHz is required, while for downsampling, it is sufficient to use a frequency of 93.3 MHz. For smaller frequency bands, an even lower oversampling rate can be selected. Thus, a reduction in the requirements for analog-to-digital conversion is achieved and the resulting digital stream is significantly reduced.

However, as the analysis shows, when restoring an analog signal from digital signals obtained as a result of downsampling, unacceptable distortions of the analog signal occur due to the properties of a conventional digital-to-analog conversion that interpolates the zero order of the signal readout values. Thus, the restoration of sub-sampled band signals becomes problematic, which could entail the rejection of subsample and a return to “direct” sampling of band signals.

As a prototype of the invention, a digital-to-analog conversion method and a device for its implementation are described in the book [3]. It describes a method of digital-to-analog conversion, which includes beat-by-weighted weighted summation of bit signals with weights gradually decreasing with a factor of 1/2 for each of the next least significant bit of the input n-bit binary code code of the signal, and the corresponding digital-to-analog conversion devices having n digital inputs are presented and analog output. Also described is a device that implements the described method of digital-to-analog signal conversion, comprising an n-bit digital-to-analog converter having n digital inputs and an analog output to which a band-pass filter is connected.

The method and device, adopted as a prototype, have very significant disadvantages. When restoring a sub-sampled band signal, its unacceptable frequency distortions arise, caused by storing the values of the restored signal for the period of the sampling frequency. These distortions manifest themselves as a sharp change in the magnitude of the reconstructed signal with frequencies that cannot be compensated using the usual frequency correction technique.

The technical result of the present invention (options) is the elimination or significant reduction of distortion of the restored sub-sampled band signal arising from its digital-to-analog conversion.

A method for digital-to-analog conversion of sub-sampled band signals is proposed, which includes step-by-step storing of digital input signals for a reference period (clock period), weighted summation of bit signals with weights gradually decreasing by a factor of 1/2 for each next least significant bit of an input n-bit binary code reference signal, in which according to the invention during the second half of each reference period, the values of the input binary signal is replaced to zero.

A method for digital-to-analog conversion of sub-sampled band signals is also proposed, which includes step-by-step storing of digital input signals for a reference period (clock period), weighted summation of bit signals with weights gradually decreasing by a factor of 1/2 for each next least significant bit of an input n-bit binary the signal reference code, in which according to the invention during the second half of each reference period the values of the input binary signal are They use the values of the binary signal corresponding to the difference between the highest nominal value of the output signal and the value of the input binary signal operating in the first half of the reference period.

A device for digital-to-analog conversion of subsampled band signals for implementing the first embodiment of the proposed method is proposed, comprising an n-bit digital-to-analog converter having n digital inputs, a clock input and an analog output, to which a band-pass filter is connected, into which n logic elements “I” are inserted according to the invention, the outputs of which are connected to the digital inputs of the digital-to-analog converter, n digital signals are supplied to their first inputs, and symmetric ith rectangular clock signal.

A device for digital-to-analog conversion of subsampled band signals for implementing the second variant of the proposed method is also proposed, comprising an n-bit digital-to-analog converter having n digital inputs, a clock input and an analog output to which a band-pass filter is connected, into which, according to the invention, n logical elements are introduced “Exclusive OR ", The outputs of which are connected to the digital inputs of the digital-to-analog converter, n digital signals are fed to their first inputs, and to the second inputs a symmetrical rectangular clock signal is applied.

Further description is explained using the following figures.

Figure 1 - frequency spectrum of a strip signal.

Figure 2 - frequency spectrum of a subsampled band signal.

Figure 3 - signals obtained by digital-to-analog conversion.

Figure 4 - frequency characteristics of digital-to-analog converters.

Figure 5 - the formation of signals at the output of the DAC.

6 is a structural diagram of the proposed digital-to-analog conversion device (option 1).

7 is a structural diagram of the proposed device digital-to-analog conversion (option 2).

Figure 1 presents an example of the frequency spectrum of a strip signal. Such an intermediate frequency signal is typical for radio relay and satellite transmission systems. The intermediate frequency (IF) is 70 MHz with a frequency band of up to ± 20 MHz. With “direct” sampling, the required sampling frequency is selected based on the upper signal frequency, which in this case is 90 MHz, which gives 90 × 2 × 1.2 = 216 MHz (here 1, 2 is a coefficient that takes into account the limitations of technical implementation.

According to the theory set forth in the mentioned book by N.K. Ignatiev, for this example, the minimum frequency of subsampling is determined by the following rules.

First, it is required that the sampling frequency f _d ≥4V, where B is half the frequency band of the downsampled band signal. Thus, 4B constitutes the full frequency band of the signal, taking into account both side bands, as well as the positive and negative parts of the frequency axis. In the example shown in figure 1, B = 20 MHz and, therefore, f _d ≥80 MHz.

Further calculation comes to the following. We determine the coefficient N * = f ₀ : B, where

f ₀ is the carrier frequency. For our example, N * = 70: 20 = 3.5. We find the coefficient N, rounding N * to the nearest smaller odd number, and we get N = 3. We find the maximum allowable frequency band as B _max = f ₀ : N and get B _max = 70: 3 = 23, 33 MHz. We determine the frequency of subsampling as f _d = 4 V _max and get f _d = 93.3 MHz.

For the case B = 12 MHz, we find f _d = 56 MHz.

For the case B = 9 MHz, we find f _d = 40 MHz.

In a similar way, the value of f _d can be determined for any given f ₀ and B.

On figa shows the analog signal obtained by the known method of digital-to-analog conversion. Here, the input digital signals are stored unchanged until the digital code of the next sample arrives, and accordingly, the output analog signal is also stored until the next digital code is received, forming a step function shown in the diagram. The process leading to obtaining a step function is described using an equivalent impulse response in the form of a rectangle, the duration of which is equal to the sampling period (determined by the clock frequency of the conversion process).

It is convenient to evaluate the resulting signal distortions in the frequency domain. The equivalent amplitude-frequency (hereinafter referred to as the frequency) characteristic of the process has the form (sin x) / x. Its first lobe in the region of positive frequencies is shown in figa. In the case of a sub-sampled band signal, the spectrum of the restored band signal undergoes very noticeable frequency distortions, which manifest themselves as strong transmission unevenness within the frequency band, so that the original signal (and its spectrum) is almost irreversibly distorted.

The described distortions can be significantly attenuated by two variants of the proposed method.

The first option is that in the known method of digital-to-analog conversion of sub-sampled band signals, which includes step-by-step storing of digital input signals for a reference period (clock frequency period), weighted summation of bit signals with weights decreasing successively with a coefficient of 1/2 for each of the following the least significant bit of the input n-bit binary code of the signal reference, an operation is introduced that provides replacement during the second half of each reference period input binary signal to zero (figb).

In this case, the equivalent rectangular impulse response is shortened to half the reference period, and the corresponding frequency response is doubled, as shown in Fig.4b. In this case, the frequency distortions of the spectrum of the strip signal are significantly reduced, and the residual distortions can be compensated using known methods of amplitude-frequency correction.

What happens as a result of zeroing the signal values in the second half of each reference period, a twofold decrease in the value of the output analog signal can be compensated by a corresponding increase in its gain.

The second variant of the proposed method consists in the fact that into the known method of digital-to-analog conversion of sub-sampled band signals, which includes beat-by-bit storing of input digital signals for a reference period (clock frequency period), weighted summation of bit signals with weights gradually decreasing by a factor of 1/2 for of each next least significant bit of the input n-bit binary code of the signal reference, an operation is introduced that provides during the second half of each reference replacement period of the input binary signal into a binary value signal values corresponding to the difference between the maximum nominal output value and the value of the input binary signal acting on the first half of the period measuring indicator (Figure 3B).

The equivalent impulse response for this variant of the method is an antisymmetric rectangular impulse, i.e. pulse consisting of two adjacent pulses of different polarity and the same duration equal to half the duration of the reference period. These adjacent pulses have the same amplitude, which is determined by the input digital signal.

To determine the equivalent frequency response of this variant of digital-to-analog conversion, we will take into account that the described impulse response can be represented as a mathematical operation of convolution of two functions. Denote the equivalent impulse response by g (t). Then

g (t) = g ₁ (t) ☐ g ₂ (t).

Here ☐ means the convolution operation, T is the reference period.

g ₁ (t) = δ (t + T / 4) -δ (tT / 4),

g ₂ (t) = P (T / 2).

The function δ (t) means a δ-function having a nonzero value only at the point t = 0, and P (T) means a rectangular function, symmetric with respect to the point t = 0, having a duration T and a constant unit amplitude. As a result of the convolution operation, antisymmetric U-shaped pulses are obtained, the sequence of which is formed at the output in the second variant of digital-to-analog conversion, as shown in Fig. 3c.

The equivalent frequency response for this option is defined as the Fourier transform of the equivalent impulse response. Since this characteristic g (t) is a convolution, the sought frequency characteristic k (f) will be the product of the Fourier transforms of the functions g ₁ (t) and g ₂ (t). In this way,

k (f) = k ₁ (f) × k ₂ (f),

where k ₁ (f) is the Fourier transform (spectrum) of the function g ₁ (t), ak ₂ (f) is the Fourier transform (spectrum) of the function g ₂ (t). These spectra are known from the reference literature and have the form:

k ₁ (f) = sin (πfT / 2) (accurate to the imaginary factor j)

k ₂ (f) = sin (πfT / 2) / (πfT / 2)

The resulting frequency response is shown in FIG. Its advantages compared with the characteristic in Fig. 46 are that, firstly, it does not reduce the amplitude of the output signal, secondly, it provides low-frequency suppression and thereby weakens interfering spectral components and, thirdly, it also has less uneven transmission in the frequency band of the strip signal, so in most cases, the use of amplitude-frequency correction will not be required.

To implement the described variants of the method, accordingly, two variants of the device are proposed.

The first embodiment of the device is presented in Fig.6. The device contains n logic circuits "And", three of which are shown in the figure under the numbers 1, 2 and 3. The signals of n binary bits of the input digital code are supplied to the first inputs of these logic circuits. The second inputs of the AND circuits connected together are supplied with a symmetrical rectangular signal (meander) of the clock frequency. The outputs of the circuits "And" are connected to the corresponding inputs of the n-bit digital-to-analog converter (DAC) 4. The output of the DAC is connected to the input of the bandpass filter 5, and the output of the latter is the output of the device from which the analog signal U is taken.

The device operates as follows. The signals of the input digital code are fed to the "And" circuits, to the second inputs of which a symmetrical rectangular signal (meander) of the clock frequency is received, in which the logical "1" and "0" values alternate in time.

The truth table of the And circuit has the following form:

0 × 0 = 0

0 × 1 = 0

1 × 0 = 0

1 × 1 = 1

It follows that when "1" is fed to the combined second inputs of the "And" circuits, the signals of binary bits supplied to their first inputs pass to the outputs without change and go to the inputs of the DAC. In this case, the reference values of the signal are restored at the output of the DAC. When “1” is applied to the combined second inputs of the “AND” circuits, the signals of binary bits supplied to their first inputs do not pass to the outputs, and zero signals are received at the DAC inputs, so zero reference values are formed at the output of the DAC. In other words, there is a twofold shortening of the counting pulses, which was required to implement the first variant of the method. Bandpass filter 5 completes the restoration of the bandpass signal.

The second variant of the device is presented in Fig.7. The device contains n Exclusive OR logic circuits (Exclusive OR), three of which are shown in the figure under the numbers 6, 7 and 8. At the first inputs of these logic circuits, n binary bits of the input digital code are supplied. The second inputs of the exclusive-OR circuits connected together are supplied with a symmetrical rectangular signal (meander) of the clock frequency. The outputs of the circuits "And" are connected to the corresponding inputs of the n-bit digital-to-analog converter (DAC) 9. The output of the DAC is connected to the input of the bandpass filter 10, and the output of the latter is the output of the device from which the analog signal U is taken.

The device operates as follows. The signals of the input digital code are fed to the exclusive-OR circuits, to the second inputs of which a symmetrical rectangular signal (meander) of the clock frequency is received, in which the values of logical "1" and "0" alternate in time.

The truth table of the XOR scheme is as follows:

0 × 0 = 0

0 × 1 = 1

1 × 0 = 1

1 × 1 = 0

It follows that when "0" is applied to the combined second inputs of the exclusive-OR circuits, the signals of binary bits supplied to their first inputs pass to the outputs without change and go to the inputs of the DAC. In this case, the reference values of the signal are restored at the output of the DAC. When "1" is applied to the combined second inputs of the exclusive-OR circuits, the signals of the binary bits supplied to their first inputs are inverted, i.e. replacing “1” and “1” by “0”. As a result, the inversion of the reconstructed reference signals also occurs.

In this case, this inversion is necessary for the implementation of the second variant of digital-to-analog conversion. The process and signal ratios are illustrated in FIG. Here, the solid horizontal line indicates the maximum voltage U _max at the output of the DAC, and the dashed horizontal line indicates the average value of this voltage. The reconstructed strip signal does not contain a constant component and, therefore, has a symmetrical character with respect to the average voltage value at the output of the DAC. Solid vertical lines show the reference values of the signal U _n , which are valid during the first half of each reference period. The dashed vertical lines show the values of the reference signals that operate during the second half of each reference period.

The reference values relative to the average value are expressed as

U _n -U _max / 2.

To implement the second variant of the proposed method, it is required that in the second half of each reference period an inverse reference value is formed relative to the average value. It has the form

- (U _n -U _max / 2).

Therefore, the absolute value of the reference in the second half of each reference period should be equal to

U _{n (inv)} = U _max / 2- (U _n -U _max / 2) = U _max -U _n .

If we go to the binary form of writing, we get (for example, for an 8-bit DAC)

U _max = 11111111

The values of U _n can vary from 00000000 to 11111111. Let, for example, U _n = 10110100. Then U _{n (inv)} will matter

those. is a binary inversion of the value of U _n , which can be obtained using the exclusive OR circuits, to the combined second inputs of which in the second half of each reference period a signal "1" should be given. Thus, in the first half of the reference period, “0” is supplied to the second inputs of the Exclusive OR circuits, and “1” in the second half. For this, a symmetrical rectangular signal (meander) of the clock frequency is needed, in which the values of logical "1" and "0" alternate in time.

The bandpass filter 5 at the output of the DAC completes the restoration of the bandpass signal according to the second variant of the method.

As can be seen from the previous description, both variants of the device are implemented very simply using sets of well-known simple logic circuits.

A symmetrical rectangular signal (meander) of the clock frequency is in many cases present in the equipment. If necessary, for its formation, well-known technical means may be needed, for example, a clock frequency doubler, made in the form of a PLL (phase locked loop) with a subsequent binary divider by 2, performed, for example, on a D-trigger. At the output of such a circuit, the required symmetrical rectangular signal is formed.

Information sources

1. Kester Walt. - Analog-Digital Conversion. - Analog Devices, 2004, p.134-138.

2. Digital and analog integrated circuits: Reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshov and others; Ed. S.V.Yakubovsky. - M .: Radio and communications, 1989, p. 424-432.

3. Volovich G.I. Circuitry of analog and analog-digital devices. - M .: Dodeka, 2007, p. 388-392.

4. N.K. Ignatiev. Discretization and its applications. - M .: Communication, 1980, p. 90-93.

Claims (4)

1. The method of digital-to-analog conversion of sub-sampled band signals, which includes beat-by-clock weighted summation of bit signals with weights gradually decreasing by a factor of 1/2 for each next least significant bit of the input n-bit binary code of the signal sample, characterized in that during the second half of each of the reference period, the values of the input binary signal are replaced with zero. 2. A method for digital-to-analog conversion of sub-sampled band signals, which includes beat-by-clock weighted summation of bit signals with weights gradually decreasing with a factor of 1/2 for each of the next least significant bit of the input n-bit binary code of the signal sample, characterized in that during the second half of each of the reference period, the values of the input binary signal are replaced by the values of the binary signal corresponding to the difference between the highest nominal value of the output signal and the value of the input binary signal, acting on the first half of the reference period. 3. A device for digital-to-analog conversion of subsampled band signals, comprising an n-bit digital-to-analog converter having n digital inputs and an analog output, to which a band-pass filter is connected, characterized in that n logical elements "I" are inserted into it, the outputs of which are connected to digital inputs n-bit digital-to-analog converter, n digital signals are supplied to their first inputs, and a symmetrical rectangular clock signal is supplied to the second inputs. 4. A device for digital-to-analog conversion of sub-sampled band signals, comprising an n-bit digital-to-analog converter having n digital inputs and an analog output to which a band-pass filter is connected, characterized in that n "EXCLUSIVE OR" logic elements are inserted into it, the outputs of which are connected to digital the inputs of an n-bit digital-to-analog converter, n digital signals are supplied to their first inputs, and a symmetrical rectangular clock signal is supplied to the second inputs.

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