RU2334370C1 - Stereoscopic television system - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: stereoscopic television system containing transmitting and receiving site, including corresponding number of receiving paths and code processing chains, within its each R, G, B code processing channel comprises series-connected first and second shot codes memories and first and second driving signal shaping unit. Screens are presented with flat panel light-emitting diode screens.

EFFECT: use of carrier frequency in transmitter; receiving site screen imaging reception without horizontal and frame scanning; higher image brightness.

25 dwg

Description

The invention relates to radio communications technology, can be used for television broadcasting in terrestrial TV networks and via satellite communication lines.

A digital television system [1] was adopted as a prototype, including a transmitting side containing a photoelectric converter / photoelectric converter / two images in the right and left frames of a stereo pair, from the first to the sixth ADC of a video signal, two ADCs of a sound signal, a master oscillator and a frequency synthesizer, three code shapers, two self-propelled pulse distributors and a three-channel transmitter of radio signals, and a receiving side containing an antenna, a control unit, three paths for receiving and processing codes, a channel for generating control signals and two channels sound accompaniment. From the first to the third paths, the reception and processing of codes are identical, each includes a radio signal receiving unit, a radio frequency amplifier, a bipolar amplitude detector, and a code processing channel including the first and second pulse generators, the first and second registers, the first and second codes processing units. The receiving side contains six blocks of pulse amplifiers, horizontal and vertical scanning blocks, a viewer helmet, in which there are two radiation modulation blocks, electron-optical scanning elements of the right and left stereo pair images and two matte screens.

The channel for generating control signals includes blocks for selecting horizontal sync pulses / SSI / and frame sync pulses, a frequency synthesizer, a key, a pulse counter, and a decoder. The sound channels are identical, each includes a block consisting of a digital-to-analog converter / DAC /, a power amplifier and a loudspeaker. The disadvantages of the prototype are: information transfer through three channels using two carrier frequencies, insufficient image brightness on a matte screen that does not have an afterglow, electron-optical scanning leads to an increase in the size and weight of the viewer's helmet and complicates its design.

The purpose of the invention is the reduction of the third transmission channel, simplifying the process of obtaining images on screens and increasing their brightness. The technical result is the use of a single carrier frequency in the transmitter, achieved by transmitting two color signals R _P , G _P and R _L , G _{L of a} stereo pair through one channel and a second color channel of a single color signal of a stereo pair V _P , V _L , receiving images on screens without using horizontal and vertical scans achieved by introducing R, G, B codes into each channel for processing frame codes and a block for generating control signals, and increasing the brightness of images by introducing flat panel LEDs single screens. The essence of the invention is that in a stereo television system containing a transmitting side and a receiving side including an appropriate number of code reception and processing paths, serial frame drive and a control signal generating unit are introduced into each of its R, G, B code processing channels, and screens are made by flat-panel LED screens / LED screens /.

The photoelectric converter uses a video mode of 600 lines × 400 samples × 50 Hz: 600 is the number of encoded lines in a frame, 400 is the number of encoded samples in a line, 50 Hz is the frame rate, 25 frames are right + 25 frames are left. Stereo frame from the right and left frames. The stereo pair frequency is 25 Hz, each includes sequentially going right frame, followed by the left frame. The code information is transmitted by the upper and lower side frequencies of one carrier frequency. The scanning of lines on the transmitting side is progressive without reverse moves both in rows and frames. The sampling frequency on the transmitting side: f _d = 600 × 400 × 50 Hz = 12 MHz.

длительность кадра 20 мс

Частота колебаний пьезодефлектора на передающей стороне при развертке строк

за один период колебания пьезодефлектора развертываются две строки: первая слева направо, вторая справа налево. Период следования кодов 83 нс

Line frequency f _c = 600 × 50 Hz = 30 kHz, line duration 33 μs

frame duration 20 ms

Piezo-deflector oscillation frequency on the transmitting side when scanning lines

in one period of oscillation of the piezoelectric deflector, two lines are developed: the first from left to right, the second from right to left. Codes 83 ns

Clock frequency: f _t = 12 MHz × 8 bits = 96 MHz.

The carrier frequency of the transmitter is taken f = 96 MHz × 15 = 1440 MHz,

upper side frequency f _in = 1440 MHz + 96 MHz = 1536 MHz,

the lower side frequency f _n = 1440 MHz - 96 MHz = 1344 MHz.

On the receiving side, the number of samples per line is doubled and the video mode is played 600 _lines × 800 _samples × 50 Hz. The sampling frequency of the codes f _d = 600 × 800 × 50 Hz = 24 MHz. The frame duration is 20 ms, the stereo pair duration is 40 ms / 25 Hz /. The transmitting side in figure 1, the raster of the frame in figure 2, the shape of the control voltage in figure 3, the structure of the digital streams on the air in figure 4, the ADC of the video signal in figure 5, the design of the piezoelectric deflector in figure 6, the code generator R, G in Fig. 7, the second code generator / B / in Fig. 8, the receiving side in Fig. 9, the bipolar amplitude detector in Fig. 10, the code processing unit in Fig. 11, the frequency spectra of the signals in Fig. 12, the key block in Fig. 13, the frame code accumulator in Fig. 14, the register block in Fig. 15, 16, the control signal generating unit in Fig. 17, the SD cell in Fig. 18, with becoming and the shape of the matrix element in Fig. 19, the arrangement of the matrix elements in the screen in Fig. 20, the block for selecting the horizontal sync pulses of the SSI in Fig. 21, the block for isolating the clock pulses of stereo pairs / SIS / in Fig. 22, the frame pulse block in Fig. 23, helmet circuit in Fig.24, timing diagrams of the system in Fig.25.

The transmitting side includes / Fig. 1 / photoelectric converter / FEP / 1, which is a sensor of video signals of two images of the same space, and generates three video signals of the right frame R _P , G _P , V _P and three video signals of the left frame R _L , G _L , V _L and contains the first / right / lens 2, connected in series to the first amplifier 3 and the first piezoelectric deflector 4 with a reflector at the end located in the focal plane of the right lens 2, the first source 5 of positive reference voltage, the second source 6 of negative reference voltage connected in series to the second amplifier 7 and the second piezoelectric deflector 8, the end of which has two faces located at an appropriate angle to each other and with a reflector on each face, a third source of positive reference voltage, fourth source 10 of negative reference voltage, second / left / the lens 11, connected in series with the third amplifier 12 and the third piezoelectric deflector 13 with a reflector at the end located in the focal plane of the left lens 11, the fifth source 14 of the positive reference voltage, w a standstill source of negative reference voltage 15, a horizontal scanning unit 16 from a driving generator 17 and an output stage 18, a vertical scanning unit 19 comprising a series-connected element And 20, a driving generator 21 and a summing amplifier 22, the first 23 and second 24 dichroic mirrors arranged in series one after another and against the first reflector of the second piezoelectric deflector 8, first 25, second 26, third 27 micro lenses, first 28, second 30, third 29 photodetectors, first 31, second 33, third 32 pre-amplifiers, third 3 4 and fourth 35 dichroic mirrors located one after the other and against the second piezoelectric reflector 8, fourth 36, fifth 38, sixth 37 micro-lenses, fourth 39, fifth 41, sixth 40 photodetectors, fourth 42, fifth 44, sixth 43 pre-amplifiers.

The second lens 11 is located to the left of the lens 2, the optical axis of the lens 11 is parallel to the optical axis of the lens 2, the distance between the axes of the lenses corresponds to the optimal stereoscopic effect for human vision. The transmitting side includes a first key 45, a trigger 46, a second 47 and a third 48 keys, a first 49, a second 50, a third 51 ADC video signals, respectively, R _P , G _P , V _P , fourth 52, fifth 53, sixth 54 ADC video signals, respectively R _L , G _L , V _L , serially connected to a master oscillator 55 and a frequency synthesizer 56, a first code generator 57, a second code generator 58, a first 59 and a second 61 self-propelled pulse distributors, a pulse counter 60, a first 62 and a second 63 ADC sound signal, the inputs of which are sound signals Sv1 and Sv2, and the transmitter is 64 rad and signals from two channels. The first channel contains a serially connected carrier frequency amplifier 65, a single-band signal shaper 66 and an output amplifier 67, the second channel contains a single-band signal shaper 68 and an output amplifier 69. Each single-band signal shaper 66, 68 includes a ring modulator and a bandpass filter connected in series [2, p .234], filtering out the unnecessary side frequency in the spectrum of the amplitude-modulated carrier, the ring modulator suppresses the carrier frequency. From the first 49 to the sixth, 54 ADCs are identical (Fig. 5/), each includes an amplifier 70 and a piezoelectric deflector 71 with a reflector at the end, a source of positive reference voltage 72, a source of negative reference voltage 73, an emitter from a pulsed LED 74, aperture diaphragm 75, and a micro lens 76 and includes a series-connected array of multi-element photodetector 77 and an encoder 78. The piezoelectric deflectors 4, 8, 13, 71 are end bimorph piezoelectric elements, are structurally executed / Fig. 6/ equally [3, p.118] from the first 79 and second 80 piezoelectric plates, inside the front electrode 81, the first 82 and the second 83 external electrodes. One end of the piezoelectric plates is fixed in the holder 84, a reflector 85 is fixed on the free end. The free end of the piezoelectric deflector 8 is made of two faces located at an appropriate angle to each other, each face has its own reflector, they separate the rays of the right 2 and left 11 lenses in different directions . ADCs 62 and 63 of the sound signal are identical [1, p. 9, Fig. 7], they are applied without changes, they convert sound signals into 16-bit codes, which are sent in parallel to the second information input of the shaper 58 codes and the third information input of the shaper 57. The first generator 57 codes contains / Fig.7/ four channels. The first channel includes series-connected the first block of 86 AND elements, the first 87 and second 88 OR elements, the first output switch 89 and the first self-propelled pulse distributor 90, the second channel includes the second block 91 of the AND elements, the third 92 and the fourth 93 OR, and the second an output switch 94 and a second self-propelled pulse distributor 95. The third channel includes a third block of 96 AND elements, the fifth 97 OR element, and a third self-propelled pulse distributor 98, the fourth channel includes a fourth block 99 of AND elements, the sixth 100 OR element and the fourth self-propelled pulse distributor 101, the first 102 and the second 103 are included in the code generator 57 keys and series-connected pulse counter 104 and decoder 105. The information inputs are: the first are the first inputs of the AND elements of the block 86, the second are the first inputs of the AND elements of the block 91, the third are the first inputs of the blocks 96 and 99 of the AND elements, and the fourth - the third inputs of the second 88 and fourth 93 elements OR connected to the output of the self-propelled distributor 59 pulses. The first output of the code generator 57 is the combined outputs of the output keys 89, 94, the second output is the third output of the decoder 105 connected to the second control input of the key 103. The first output of the decoder 105 is connected to the first control input of the first key 102, the second output is connected in parallel to the second the control input of the first key 102 and to the first control input of the second key 103. The control inputs are: the first is the combined inputs of the first 102 and second 103 keys and the counting input of the pulse counter 104, the second is about the combined signal inputs of the output keys 89, 94, the third is the control input of the pulse counter 104. The second generator 58 codes contains / Fig.8/ three channels. The first channel includes series-connected the first block of AND elements 106, the first 107 and second 208 OR elements and the first output switch 109 and the first self-propelled pulse distributor 110, the second channel includes the second block of elements AND 111 and the third OR element 112 and the second self-propelled distributor 113 pulses, the third channel includes series-connected third block 114 of AND elements, fourth 115 and fifth 116 OR elements, and a second output switch 117, and a third self-propelled pulse distributor 118. Block 58 includes the first 119 and second 120 keys and series-connected pulse counter 121 and decoder 122. Information inputs are: the first are the first inputs of the first block 106 of AND elements, the second are the first inputs of the second 111 and third 114 blocks of AND elements, the third is the third input second 108 OR element, fourth - the second input of the fifth 116 OR element. The output of block 58 is the combined outputs of the output keys 109, 117. The control inputs are: the first is the combined inputs of the first 119, second 120 keys and the counting input of the pulse counter 121, the second is the combined signal inputs of the output keys 109, 117, and the third is the control input of the counter 121 pulses. The outputs of the decoder 122 are connected: the first to the first control input of the first key 119, the second to the second control input of the key 119 and to the first control input of the second key 120, the third to the second control input of the key 120.

The receiving side includes / FIG. 9/ antenna, control unit 123, first and second paths for receiving and processing codes, a channel for generating control signals and two sound channels. The first path for receiving and processing codes receives and processes the codes of video signals R _P , G _P and R _L , G _L and contains a series-connected radio signal receiving unit 124, a radio frequency amplifier 125, a bipolar amplitude detector 126, a channel for processing R codes, and a channel for processing G codes The R code processing channel includes, in series, a first pulse generator 127, an R signal register 128, a code processing unit 129, a key block 130, a first 132 and a second 131 frame code stores, a first 134 and a second 133 control signal generating units in. The G code processing channel includes a second pulse shaper 135, a G register 136, a code processing unit 137, a key block 138, a first 140 and a second 139 frame code stores, a first 142 and a second 141 control signal generating units, connected in series. The second path for receiving and processing codes receives and processes the codes of video signals V _P , V _L , contains a series-connected radio signal reception unit 143, a radio frequency amplifier 144, a bipolar amplitude detector 145, and a code processing channel B including a third pulse shaper 146 connected in series, register 147 signal B, code processing unit 148, key block 149, first 151 and second 150 frame code stores, first 153 and second 152 control signal generating units. The second receiving and processing path includes a fourth pulse shaper 154. The receiving side includes a right 155 and a left 156 flat-panel LED screens / LED screens / and a viewer helmet 157 in which the LED screens 155, 156, key blocks 130, 138, 149, drives 131, 132, 139, 140 are respectively located 150, 151 frame codes and blocks 133, 134, 141, 142, 152, 153 generating control signals. The control signal generating channel includes a serially connected horizontal sync / SSI / 30 kHz separation block 158, a frequency synthesizer 159, a key 160, a pulse counter 161 and a decoder 162, and a stereo pair / SIS / 25 Hz sync pulse extraction block 163 and a frame pulse block 164 connected in series. Code processing blocks 129, 137, 148 are identical (Fig. 11/), each includes trigger 167, first 168, second 169 key blocks, first 170, second 171, third 172, fourth 173 registers, fifth 174 and sixth 175 registers, block 176 delay elements, the adder 177 and 16 diodes. The information input is the bitwise combined inputs of the blocks 168, 169 of the keys, the control input is the input of the trigger 167, the output is the bitwise combined outputs of the registers 174, 175 and the block 176 of the delay elements.

Blocks 130, 138, 149 keys are identical / Fig.13/, each includes the first 178 and second 179 blocks of keys, each key in the number of bits in the code of 8 pieces. Information inputs of blocks 130, 138, 149 are bitwise combined from 1 to 8 inputs of the first 178 and second 179 key blocks. The control inputs are: the first is the control input / 50 Hz / block 178, the second is the control input / 50 Hz / block 179. The first output of the block 130/138, 149 / are outputs 1 to 8 of the first block 178 keys, the second are the outputs from 1 to 8 of the second block 179 keys.

с генератора 185 импульсов, коду 00000010 - два импульса 156 мкс, коду 00000011 - три импульса 234 мкс и т.д., коду 11111110 соответствует длительность излучения в 254 импульсов 18,942 мс и коду 11111111 - 255 импульсов, т.е. 19,922 мс. Инерционность срабатывания микросветодиода должна быть не более 1 мкс. По окончании накопления кодов накопителями кодов кадра сигнал 50 Гц U_к с первого выхода блока 164 открывает все первые ключи 186, вторые 189 ключи в блоках 132, 140, 151, и коды кадра синхронно и в параллельном виде поступают с блоков 132, 140, 151 /фиг.9/ на информационные входы вычитающих счетчиков 187 с первого по 480000. Открытые ключи 186 пропускают импульсы 12,8 кГц с генератора 185 на счетные входы счетчиков 187, а через открытые ключи 189 напряжение питания с источников 190 питания запитывает микросветодиоды в СД-ячейках экрана 155. Процесс вычитания в счетчиках длится до появления в них кода 00000000. При этом коде сигнал U_з с дешифратора 188 закрывает оба ключа 186, 189. Питание светодиода перекрывается, излучение его заканчивается. Таким образом, длительность излучения микросветодиода прямо пропорционально величине кода цветового сигнала. Плоскопанельные светодиодные экраны 155, 156 идентичны, каждый представляет совокупность элементов матрицы соответственно /фиг.20/ разрешению кадра 480000 /800×600/. Каждый элемент матрицы содержит три светодиодных ячейки /СД-ячейки/, каждая из которых включает три микросветодиода, излучающих три основных цвета R, G, В. СД-ячейка /фиг.18/ содержит микросветодиод 191 белого свечения и расположенный на излучающей его стороне цветной светофильтр 192 одного из основных цветов. Три СД-ячейки составляют один элемент матрицы /фиг.19/, формирующий изображение одного пиксела на экране. Расположение элементов матрицы в экране на фиг.20. СД-ячеек в экране 1440000 /800×600×3/.The drives 131, 132, 139, 140, 150, 151 frame codes are identical, each includes / Fig. 14/ blocks of 180 registers according to the number of lines in the frame 180 _1-600 . The information input of the frame code storage device is bitwise integrated from 1 to 8 inputs of six hundred / 600 / blocks of 180 registers. The information inputs of the frame code storage devices are connected: 132, 131, respectively, to the first and second outputs of the key block 130, 140, 139 to the first and second outputs of the key block 138, 151, 150 to the first and second outputs of the key block 149. The control inputs are: the first is the first control input of the first block 180 ₁ registers / 50 Hz /, the second is the combined second control inputs / 30 kHz U _output / blocks of 180 registers, the third is the combined third control inputs / 24 MHz U _d / blocks of 180 registers . Each control output of the previous block 180 registers is the first control input of each subsequent block 180 registers. The control output of the last / 600th / block of 180 registers is connected in parallel to the fourth control inputs of all blocks of 180 registers. The outputs of the drive code frame are the outputs of all blocks 180 _1-600 registers. The blocks 180 of the registers are identical (Fig. 15, 16), each includes the first 181 and second 182 keys, the distributor 183 pulses and eight registers 184. The information input of the block 180 are bitwise combined from 1 to 8 third inputs of the bits of eight registers 184. The outputs are parallel the outputs of all bits of eight registers, a total of 6400 outputs / 800 × 8 /. And the outputs of 600 blocks of registers 180 are the outputs of each drive code codes, total outputs 3840000/6400 × 600 /. Control inputs are as follows: first - the first control input / 50 Hz / first switch 181, second - signal input / 30kHz U _vyd / second switch 182, the third - the signal input / 24 MHz U _d / a first key 181, the fourth - the first control input the second key 182. The last output of the / 800th / pulse distributor 183 is connected to the second control input of the first key 181 and is the control output of the block 180 registers connected to the first control input of the next block 180 ₂ registers. The output of the first key 181 is connected to the input of the pulse distributor 183, the outputs of which are connected in series from the first to the 800th to the first inputs of the bits in parallel to eight registers 184. The output of the second key 182 is connected in parallel to the second inputs of the bits of eight registers 184 and to the second control input of the second key 182, the transmitted impulse U _vy closes the key 182. The outputs of the frame code storage devices are connected respectively: 131 to the information inputs of the control signal generation unit 133, 132 to the inputs of the block 134, 139 to the inputs of the block 141, 140 to the input block 142, 150 to the inputs of block 152, 151 to the inputs of block 153. Blocks 133, 134, 141, 142, 152, 153 of the formation of control signals are identical, each contains / Fig. 17/ a generator of 185 pulses and 480000/800 × 600 / converters "code - duration of radiation", which are identical and each includes / Fig.17/ series-connected first key 186, subtracting counter 187 pulses, decoder 188 and second key 189 and power source 190/3 V /. The output of each second key is connected to the input of its micro-LED in the screen 155/156 /. The signal input of the second key 189 is connected to the output of its power source 190. The initial state of the keys 186, 189 is closed. The pulse generator 185 is a frequency multiplier of 50 Hz × 256 = 12.8 kHz and provides 12.8 kHz pulses in parallel to the signal inputs of the first keys 186. The output of each first key 186 is connected to the counting input of its subtractive counter 187 pulses, the output of the decoder 188 is connected to the second control inputs of the first 1P6 and second 189 keys, the first control inputs of all keys 186, 189 and the input of the pulse generator 185 are combined and are the control input / 50 Hz U _to / connected to the corresponding output of block 164. Code-to-duration converters exercises "work identically. With a frame duration of 20 ms / 50 Hz / code 00000001, the duration of the LED emission in one pulse corresponds to 78 μs

from the generator 185 pulses, code 00000010 - two pulses 156 μs, code 00000011 - three pulses 234 μs, etc., code 11111110 corresponds to a radiation duration of 254 pulses 18.942 ms and code 11111111 - 255 pulses, i.e. 19.922 ms. The inertia of operation of the micro-LED should be no more than 1 μs. Upon completion of the accumulation of codes by the drive of the frame codes, a signal of 50 Hz U _k from the first output of block 164 opens all the first keys 186, the second 189 keys in blocks 132, 140, 151, and the frame codes synchronously and in parallel come from blocks 132, 140, 151 / Fig. 9/ to the information inputs of the subtracting counters 187 from the first to 480000. The public keys 186 pass 12.8 kHz pulses from the generator 185 to the counting inputs of the counters 187, and through the public keys 189, the supply voltage from the power sources 190 feeds the micro LEDs in the SD- cells of the screen 155. The process of subtraction in the counters lasts I until the code 00000000 appears in them. With this code, the signal U _s from the decoder 188 closes both keys 186, 189. The power of the LED is cut off, its radiation ends. Thus, the duration of the emission of the micro LED is directly proportional to the value of the color signal code. Flat-panel LED screens 155, 156 are identical, each representing a set of matrix elements, respectively / Fig. 20/, frame resolution 480000/800 × 600 /. Each matrix element contains three LED cells / LED cells /, each of which includes three micro-LEDs emitting three primary colors R, G, B. The LED cell / Fig. 18/ contains a white LED micro-LED 191 and a color LED located on its radiating side filter 192 of one of the primary colors. Three LED cells make up one element of the matrix (Fig. 19), which forms an image of one pixel on the screen. The arrangement of the matrix elements in the screen of FIG. SD cells in the screen are 1440000/800 × 600 × 3 /.

As micro-LEDs, super-bright white LEDs are used, for example, Nichia, Ledtronics, Kingbright companies [4, p. 47], which are made by microelectronic technology without micro-LEDs directly in the screen material. The size of the micro-LED is 0.025 × 0.025 mm, the size of the matrix element is 0.05 × 0.05 mm / Fig. 19/.

With a resolution of 800 × 600, the screen sizes 155, 156 will be:

horizontal 800 × 0.05 mm = 40 mm, vertical 600 × 0.05 mm = 30 mm, diagonal 50 mm, 1.97 ". The brightness level of the SD cell in the frame period is determined by the value of the color signal code: the larger the code, the longer the micro-LED emits during the frame period, the brighter the level of brightness perceives vision. The brightness and color tone of a pixel are determined by the duty cycle of the radiation of three micro-LEDs in the matrix element. The duration of each micro-LED is determined by the duration of its power from the power source 190 / 17.17, formed convert I eat “code - radiation duration.” Synchronous flashing by all screen matrix elements of all the pixels of the frame together makes a picture of the frame. The result of the process of acquiring the image on the screen is the use of traditional line and frame scans. The uniformity of the applied electronic circuits allows each code storage device to be executed. frame and each control signal generating unit in a single chip.

Block 158 line synchronization selection / SSI / includes / Fig.21 / first 193, second 194, third 195 pulse counters, first 196, second 197, third 198 elements NOT, the first 199 and second 200 elements And and a diode. The inputs of block 158 are the counting inputs of three pulse counters, the output is the output of the second And 200 element. The block 163 of the stereo pair synchronization pulse / SIS / includes / Fig. 22/ first 201 and second 202 pulse counters, the first 203 and second 204 elements are NOT, the first 205 and the second 206 elements And and a diode. The inputs of block 163 are the first, second inputs of counters 201, 202 pulses and the second input of the second element And 206, the output is the output of the second element And 206. The outputs of the counter 201 and counter 202 pulses are connected to the inputs of the first element And 205, the output of which and the third input of the block 163 are connected to the inputs of the second element And 206, the outputs of the elements NOT and the output of the element And 206 through the diode are combined and connected in parallel to the control inputs of both pulse counters 201, 202. Block 164 frame pulses includes / Fig.23 / connected in series key 207 and trigger 208. The information input is the signal input of the key / 50 Hz / connected to the seventh output of the synthesizer 159 frequencies, the control input is the control input of the key 207/25 Hz /, connected to the output of block 163. The outputs of block 164 are the first and second outputs of trigger 208. The first output is connected to the first control inputs of key blocks 130, 138, 149, the first control inputs of drive codes 132, 140, 151 of the frame codes and the first control inputs of blocks 134, 142, 153 ormirovaniya control signals, the second output latch 208 is connected to second control inputs of blocks 130, 138, 149 keys, a first control input of the second storage devices 131, 139, 150 block codes and to the control inputs of blocks 133, 141, 152 generating control signals.

FEP 1 generates six analog video signals of two images from the right 2 and left 11 lenses. Lens 2 creates the right image in the focal plane in which the reflector of the piezoelectric deflector 4 is located. Its reflector has a width of 0.01 mm, a length of 6 mm / 0.01 mm × 600 lines /. The dimensions of the deploying element are 0.01 × 0.01 mm. According to the control voltages (Fig. 3/) of the amplifier 3, the piezoelectric deflector 4 vibrates the end face with the reflector relative to the first reflector of the piezoelectric deflector 8, performing a horizontal scan of the right image. The lens 11 creates a left image in the plane of the reflector of the piezoelectric deflector 13, which has the same dimensions: a width of 0.01 mm and a length of 6 mm, oscillates the end relative to the second reflector of the piezoelectric deflector 8, scanning horizontally - the left image. Block 16 produces a linearly varying voltage in the form of an isosceles triangle / 3 /. The control voltage period is equal to the duration of two lines. For a 600-pixel raster at 50 Hz frames, piezo-deflectors 4 and 13 oscillate synchronously and in phase with a frequency of 15 kHz. For the period of one oscillation, two lines are scanned / from left to right and from right to left, Fig. 2 /. Line frequency 30 kHz. Line scanning is progressive, without reverse moves. The piezoelectric deflector 8 performs a frame scan of two frames: when scanning downward, the ADCs 49-51 give codes of the right frame, and when scanning upwards, the ADCs 52-54 give codes of the left frame. The piezoelectric deflector 8 oscillates at a frequency of 25 Hz, which is 50 frames per second. Frame scan without reverse moves. The width of the reflector at the end of the piezoelectric deflector is 8 0.01 mm, the length of each reflector is 4 mm / 0.01 mm × 400 /. From the output of the summing amplifier 22, the amplifier 7 receives a linearly varying and step voltage / 3 / amplified to the required value by the amplifier 7 [3, p.122]. The summing amplifier 22 performs the summation of the line voltage from the master oscillator 21 with pulses of 30 kHz line frequency. Each line impulse moves the line at the end of its move by one line step, 600 lines are obtained, all active. Mixed color beams reflected from the first reflector of the piezoelectric deflector 8 are sent to their micro-lenses, which collect them into their photodetectors 28, 29, 30. From the photodetectors, analog video signals are fed to the pre-amplifiers 31, 32, 33. Similar processes are transmitted from the second reflector of the piezoelectric deflector 8, analog video signals are supplied respectively to the pre-amplifiers 42, 44, 43. From the pre-amplifiers 31, 33, 32, the video signals are fed to the ADC inputs 49, 50, 51, and from the pre-amplifiers 42, 44, 43 are fed to the input ADCs 52, 53, 54. The alternate issuance of stereo pair codes with ADCs 49-51 and 52-54 is performed by trigger 46 and keys 47, 48. The 50 Hz pulses from the sixth output of the 56 frequency synthesizer are sent through public key 45 to trigger 46. Key 45 performs a 50 Hz pass synchronization with the beginning of the period of the right frame of the stereo pair. The signal U _{from the} key 45 comes from the output of the element And 20 at the moment of arrival of a pulse of 25 Hz / beginning of the right frame / and a pulse of frequency of the lead 30 kHz. Key 45 remains open at all times. During the period of the right frame, 12 MHz sampling pulses from the second output of block 56 pass the public key 47 and are sent to the control / clock / ADC inputs 49-51; converting analog video signals R _P , G _P , V _{P of the} right frame into 8-bit codes. In the period of the left frame, 12 MHz pulses from key 48 are fed to the ADC 52-54 clock inputs, which convert the analog video signals of the left frame R _L , G _L , V _L into 8-bit codes. A frequency synthesizer 56 provides 25 Hz stereo frequency pulses from the first output to the second input of the frame scanning unit 19 and to the control input / U _o / of the pulse counter 60, from the fifth output - 30 kHz line frequency pulses to the first input of the block 19, to the third control inputs shapers 57, 58 codes to the second control inputs of the ADC 62, 63, from the second output - 12 MHz pulses to the inputs of the keys 47, 48, to the first control inputs of the blocks 57, 58 and to the first control inputs of the ADC 62, 63, from the sixth output - pulses of 50 Hz frame rate to the signal input of the key 45, from the fourth - 96 MHz clock pulses to the second control inputs of blocks 57, 58, from the third output of 90 kHz to the third control inputs of the ADC 62, 63, about the seventh output of 15 kHz to the input of the horizontal block 16, from the eighth output - sinusoidal oscillations of the carrier frequency of 1440 MHz to the input of the transmitter 64 radio signals. The master oscillator 55 generates sine waves with a stability of 10 ^-7 . The ADCs 62, 63 convert the sound signals into 16-bit codes, which are sent in parallel to the third information input of the code generator 57 from the ADC 62 and to the second information input of the code generator 58 from the ADC 63. Self-propelled pulse distributor 59 with the arrival of the signal U _P with the second output of block 57 / at the time 400 of the line sampling pulse, Fig. 4 / gives a code of eight units 11111111, which is the horizontal sync pulse code / SSI /, to the fourth information input of block 57 and the third information input of block 58. Self-propelled distributor 61 pulse with the arrival at its input a start signal U _f from the second discharge pulse counter 60 outputs a code of eight units 11111111, which sync stereopair / SIS /, to the fourth informational input of the block 58. The SIS code is the first code of the first line of each of the right frame, FIG. four. The counter 60 pulses two-bit determines the sequence in a stereo pair of the first right frame, the second left. After zeroing the counter 60 with a pulse U _about 25 Hz, the first pulse of the end of the right frame comes from the second output of block 57 / from the third output of the decoder 105 /, then the second pulse of the end of the left frame of the stereo pair, and from the output of the second discharge of the counter to the input of block 61 the signal U _p , by which the block 61 issues to the fourth input of the block 58 the clock pulse of the stereopair SIS, which is the first code of the first line of the right frame. The ADCs 49-54 are identical (Fig. 5/), have one conversion principle, which consists in scanning the beam from the LED 74 with a piezoelectric reflector 71 along the plane of the entrance pupils of the photodetector line 77. The light pulse is converted into an electrical signal that excites the corresponding encoder bus 78, which gives code of the instantaneous value of the input signal. Discretization of the conversion of 12 MHz. The radiation source is a pulsed LED AL402A with a response time of 25 ns. Line 77 includes 255 photodetectors for encoding signals with an 8-bit code. Photodetectors are avalanche photodiodes of the APD with a response time of 10 ns. The encoder from the K155IV1 chip with a response time of 20 ns. Conversion time 30 ns, satisfying the frequency of 12 MHz / 83 ns /. The encoder generates codes from 00000001 to 11111111. The first sneaker of the photodetector in line 77 corresponds to the code 00000001, the second to code 00000001, the third to 00000011, and the 255th to code 11111111.

The work of the shapers codes 57, 58, Fig.7, 8.

выходной ключ 89. На сигнальный вход выходного ключа 89 поступают синусоиды моночастоты 96 МГц. Первый выходной ключ 89 в открытом состоянии пропускает одну положительную полусинусоиду на выход. Аналогичный процесс проходит и код, поступающий на первые входы элементов И блока 91, импульсы с которого открывают на время 10,4 нс выходной ключ 94, который в открытом состоянии пропускает одну отрицательную полусинусоиду 96 МГц на выход. Выходы ключей 89, 94 объединены, на выходе блока 57 выходной сигнал представляется полными или неполными синусоидами частоты частоты 96 МГц и со стабильностью колебаний 10^-7. Единицы в кодах R_П, R_Л представляются положительными полусинусоидами, единицы в кодах G_П, G_Л представляются отрицательными полусинусоидами. Нули представляются отсутствием и тех и других. Эти сигналы и модулируют несущую частоту в формирователе однополосного сигнала 66 передатчика 64. Очередность получения сигналов ССИ, кодов отсчетов строки и кодов звука определяется выходными сигналами с дешифратора 105. В исходном состоянии ключ 102 закрыт. Счетчик 104 9-разрядный, ведет счет импульсов 12 МГц, цикл счета 400. При коде 00000001 импульс с первого выхода дешифратора 105 открывает ключ 102, пропускающий импульсы 12 МГц в качестве сигнала U_п в самоходный распределитель 90 и 95, и со второго отсчета строки формируются коды видеосигналов R_п, G_п. Коды видеосигналов формируются с второго по 397 отсчеты строки. При 397 отсчете в счетчике 104 код 110001101 /397/, дешифратор 105 при этом коде выдает сигнал со второго выхода, который закрывает ключ 102 и открывает ключ 103. Импульс U_п с ключа 103 запускает самоходные распределители 100, 101 импульсов, на вторые входы элементов ИЛИ 88, 93 поступают с 1 по 8 и с 9 по 16 импульсы кодов звука. Ключ 103 открыт на время прохода трех кодов звука во время 398, 399, 400 импульсов дискретизации строки /фиг.4/. При поступлении в счетчик 104 последнего /400-го/ импульса строки с третьего выхода дешифратора 105 импульс закрывает ключ 103, он же является вторым выходным сигналом с блока 57, который запускает самоходный распределитель 59, который в момент первого отсчета строки подает на третьи входы элементов ИЛИ 88, 93 код ССИ. Этот код является первым кодом в каждой строке. Далее процессы повторяются. В кодах звука единицы в разрядах с 1 по 8 представляются положительными полусинусоидами, единицы в разрядах с 9 по 16 представляются отрицательными полусинусоидами. На первый информационный вход формирователя 58 кодов /фиг.8/ поступают коды с АЦП 51, 54 /В_П, В_Л/. С выходов блока 106 импульсы кодов последовательно через элементы ИЛИ 107, 108 открывают на время своей длительности 10,4 нс первый выходной ключ 109, на сигнальный вход которого поступают синусоиды частотой 96 МГц. Ключ 109 в открытом состоянии пропускает одну положительную полусинусоиду. Единицы кодов В_П, В_Л представляются положительными полусинусоидами. С приходом в дешифратор 122 кода 397 отсчета строки сигнал со второго выхода дешифратора 122 закрывает ключ 119, открывает ключ 120, и с выходов элементов И блоков 111, 114 на второй вход элемента ИЛИ 108 и на первый вход элемента ИЛИ 116 поступают три кода сигнала звука. Сигналы с 1 по 8 разряды кодов поступают последовательно через элементы ИЛИ 112, 108 на управляющий вход первого выходного ключа 109, сигналы разрядов с 9 по 16 поступают через элементы ИЛИ 115, 116 на управляющий вход второго выходного ключа 117. С приходом в счетчик 121 импульса 400 дискретизации строки сигнал с третьего выхода дешифратора 122 закрывает ключ 120. Начинается период следующей строки, в котором с блока 59 первым кодом строки является код ССИ, в первой строке каждого правого кадра первым кодом строки является с блока 61 код СИС. Единицы в коде ССИ представляются положительными полусинусоидами, единицы в коде СИС представляются отрицательными полусинусоидами. С приходом первого импульса дискретизации строки в счетчик 121 с первого выхода дешифратора 122 сигнал открывает первый ключ 119, и со второго по 397 отсчеты строки формируются коды сигналов В_П /B_Л/. Далее процессы повторяются. Спектр амплитудно-модулированного сигнала передатчика 64 /фиг.12/ состоит из несущей 1440 МГц и двух боковых частот. Сама несущая и одна из боковых частот в информационном смысле являются избыточными, поэтому в каждом формирователе 66, 68 однополосного сигнала подавляется несущая частота и отфильтровывается ненужная боковая частота. Формирователь 66 выдает в выходной усилитель 67 верхнюю боковую частоту 1536 МГц, формирователь 68 выдает в выходной усилитель 69 нижнюю боковую частоту, 1344 МГц. Первый канал передатчика 64 излучает верхнюю боковую частоту с информацией кодов R_П, G_П /R_Л, G_Л/ и при стабильности несущей 10^-7 займет полосу в эфире ±154 Гц, или 308 Гц. Второй канал излучает нижнюю боковую частоту с информацией кодов В_П /В_Л/ и займет в эфире полосу ±134,4 Гц, или 268 Гц.Timing diagrams of the operation of blocks 57, 58 in Fig.25. Shapers 57, 58 codes convert incoming parallel codes into sequential ones and replace the representation of units from pulses with positive and negative half-sinusoids of the 96 MHz monofrequency in them. Codes in a parallel form with a frequency of 12 MHz are received from the ADC 49, 52 to the first information input of block 57 (Fig. 7/), codes from the ADC 50, 53 come to its second information input, codes from the ADC come to the third information input of block 57 , the fourth input receives the SSI signal code in serial form from block 59. The codes are fed to the first inputs of the AND elements of block 86, the second inputs of which receive 8 pulses sequentially from block 90, the starting signal to which comes from the first key 102. From the outputs of the block 86 code pulses sequentially through an element OR 87, 88 open at the time of its duration of 10.4 ns

output key 89. The signal input of the output key 89 receives a sinusoid of a single frequency of 96 MHz. The first output switch 89 in the open state passes one positive half-sine wave to the output. A similar process takes place and the code arrives at the first inputs of the AND elements of block 91, the pulses from which open the output switch 94 for 10.4 ns, which in the open state passes one negative half-sine wave of 96 MHz to the output. The outputs of the keys 89, 94 are combined; at the output of block 57, the output signal appears to be full or incomplete sinusoids of a frequency of 96 MHz and with an oscillation stability of 10 ^-7 . Units in codes R _P , R _{L are} represented by positive half-sine waves, units in codes G _P , G _{L are} represented by negative half-sines. Zeros appear to be the absence of both. These signals modulate the carrier frequency in the shaper of the single-band signal 66 of the transmitter 64. The order of receipt of the SSI signals, code samples of the line and sound codes is determined by the output signals from the decoder 105. In the initial state, the key 102 is closed. The counter 104 is 9-bit, counts pulses of 12 MHz, the counting cycle is 400. With the code 00000001, the pulse from the first output of the decoder 105 opens the key 102, which transmits pulses of 12 MHz as a signal U _p to the self-propelled distributor 90 and 95, and from the second sample of the line codes of video signals R _p , G _p . Codes of video signals are generated from the second to 397 samples of the line. With 397 counts in the counter 104, code 110001101/397 /, the decoder 105 gives a signal from the second output, which closes the key 102 and opens the key 103. The pulse U _p from the key 103 starts the self-propelled distributors 100, 101 pulses to the second inputs of the elements OR 88, 93 are received from 1 to 8 and from 9 to 16 pulses of sound codes. The key 103 is open at the time of passage of the three sound codes during 398, 399, 400 pulses of line sampling / Fig. 4/. When the last / 400th / pulse of the line arrives at the counter 104 from the third output of the decoder 105, the pulse closes the key 103, it is the second output signal from block 57, which starts the self-propelled distributor 59, which at the time of the first counting of the line supplies the third inputs of the elements OR 88, 93 SSI code. This code is the first code on each line. Next, the processes are repeated. In sound codes, units in digits 1 through 8 appear to be positive half sine waves, units in digits 9 through 16 appear to be negative half sine waves. At the first information input of the shaper 58 codes (Fig. 8/), codes are received from the ADC 51, 54 / _VP , V _L /. From the outputs of block 106, the code pulses sequentially through the OR elements 107, 108 open for the duration of 10.4 ns the first output switch 109, to the signal input of which sine waves with a frequency of 96 MHz are received. The key 109 in the open state passes one positive half-sine wave. The code units B _P , B _{L are} represented by positive half-sine waves. When the code 397 reads the line into the decoder 122, the signal from the second output of the decoder 122 closes the key 119, opens the key 120, and from the outputs of the AND elements of the blocks 111, 114, the three input of the sound element OR 108 and the first input of the OR element 116 receive three sound signal codes . Signals from 1 to 8 bits of the codes are fed sequentially through the elements of OR 112, 108 to the control input of the first output key 109, signals from bits 9 to 16 are sent through the elements of OR 115, 116 to the control input of the second output key 117. With the pulse 121 coming to the counter 400, line sampling, the signal from the third output of decoder 122 closes the key 120. The period of the next line begins, in which the first code of the line is the SSS code from block 59, in the first line of each right frame the first line code is the SIS code from block 61. Units in the SSI code are represented by positive half-sine waves, units in the SIS code are represented by negative half-sine waves. With the arrival of the first pulse of line sampling to the counter 121 from the first output of the decoder 122, the signal opens the first key 119, and from the second to 397 samples of the line, signal codes B _П / B _Л / are generated. Next, the processes are repeated. The spectrum of the amplitude-modulated signal of the transmitter 64/12 / consists of a carrier of 1440 MHz and two side frequencies. The carrier itself and one of the side frequencies in the information sense are redundant, therefore, in each shaper 66, 68 of a single-band signal, the carrier frequency is suppressed and the unnecessary side frequency is filtered out. Shaper 66 provides the upper side frequency 1536 MHz to the output amplifier 67, a shaper 68 provides the lower side frequency 1344 MHz to the output amplifier 69. The first channel of the transmitter 64 emits an upper side frequency with information of codes R _P , G _P / R _L , G _L / and with carrier stability of 10 ^{-7 it} will occupy the broadcast band ± 154 Hz, or 308 Hz. The second channel emits a lower side frequency with the information of codes V _P / V _L / and will take on the air the band ± 134.4 Hz, or 268 Hz.

On the receiving side, two radio signals are received by blocks 124, 143 (Fig. 9/), which are channel selectors of the corresponding ranges with electronic tuning, each block includes an input circuit, a radio frequency amplifier, and a mixer [5, p. 132]. The band-pass filter of the radio frequency amplifier is tuned by the bias voltage from the control unit 123 / channel selection /. The radio frequency signal through the communication loop enters the mixer, it is also fed from the synthesizer 159 frequencies / output 5 / frequency equal to the carrier frequency of the transmitter 64, which is necessary for detecting a single-band signal [6, p.146].

The signal from the mixer, which is the output signal of the block 124/143 /, is fed to the input of the amplifier 125/144 / radio frequency, where it is amplified to the required value and fed to the input of the bipolar amplitude detector 126/145 /. The second inputs of the frequency synthesizer 159 are connected to the second group of outputs of the control unit 123. When the transmission channel is turned on, the signal from the corresponding output of block 123 enters block 159 and determines the output of the required carrier frequency to the third inputs of blocks 124, 143. The bipolar amplitude detectors 126, 145 are made according to the scheme in FIG. 10. Diode D1 selects the positive envelope of the modulating signal / 25 /. The diode D2 from the modulating one selects the envelopes of the positive half-sine waves, the diode D3 from the modulating one selects the envelopes of the negative half-sine waves / symbols of units of codes G _П and G _Л /. Similarly, in block 145 for signals V _P and V _L. From the first output of the bipolar amplitude detector 126, the detected positive half-sine waves with a frequency of 96 MHz are fed to the input of the driver 127/146 / pulses, from the second output, the detected negative half-sinusoids are fed to the input of the second driver 135/154 / pulses. The pulse shapers are made according to a symmetric trigger circuit with emitter coupling [7, p.209], which forms rectangular pulses from harmonically changing signals. The pulses have the same polarity and duration equal to the pulse duration in the codes on the transmitting side. Units in codes are now represented by the presence of momentum, zeros by their absence. When the power of the receiving side is turned on, all keys are in the closed state. The operating procedure is determined by control signals from the channel for generating control signals. The decisive role belongs to block 158 allocation of sync pulses. A condition for the appearance of an SSI pulse from block 158 is the simultaneous arrival of three codes of eight units at the counting inputs of block 158, with the arrival of which block 158 generates an SSI / 30 kHz / horizontal sync pulse. The pulses of the SSI are fed to the first input of the frequency synthesizer 159, according to them, the frequency is tuned in the frequency synthesizer 159 to the frequency and phase of the master oscillator 55 on the transmitting side. Own frequency stability of the synthesizer 159 frequencies 10 ^-6 . Synthesizer 159 produces: 96 MHz clock pulses from the first output, 90 kHz sound sampling pulses from the second output, 12 MHz code sampling pulses from the third output, 24 MHz code double sampling pulses from the fourth output, carrier sinusoidal oscillations from the fifth output frequencies, from the sixth - pulses of a frequency of lines of 30 kHz, from the seventh output - pulses of 50 Hz of a frame frequency. The codes of the video signals from the pulse generators 127, 135, 146 are sequentially supplied to the information inputs of the registers 128, 136, 147, respectively, to the first control inputs of which 96 MHz clock pulses are received. Filled eight bits in the registers, the codes take on a parallel form, in which they are further used. In the second control registers inputs receives pulses of 12 MHz, they are signals U _vyd issuing codes into respective blocks 129, 137, 148 codes processing that perform doubling of samples per line from 400 to 800 give the intermediate / secondary / codes between each passing code and following him. Blocks add up the previous and subsequent codes and divide the sum code in half / by two /. Division is performed without time expenditures - by discarding the least significant digit in the sum code, as is done when dividing the decimal number by ten. To do this, the corresponding connection of the outputs of the adder 177/11 / to the inputs of the block 176 elements of delays:

adder outputs 177 0 one 2 3 four 5 6 7 8 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Block Inputs 176 one 2 3 four 5 6 7 8

Bit 0 means transfer to the high bit when the sum of codes.

т.е. 24 МГц. Поэтому процесс сложения занимает 41,5 нс: от поступления кодов в сумматор до появления результата на выходе блока 176. Сумматор из микросхем К555ИМ6 [8, с.258] с временем сложения 24 нс, остающееся 17,5 нс /41,5 нс - 24/ приходится на задержку в блоке 176. С приходом первого импульса 12 МГц в триггер 167 /фиг.11/ с его первого выхода сигнал U_{выд 1} одновременно /синхронно/ выдает: из регистра 171 "код 0" /из одних нулей/ на первые входы сумматора 177, из регистра 172 выдает "код 0" на вход регистра 175 и через диоды на вторые входы сумматора 177 /сигналы выдачи и обнуляют разряды регистров/ и открывает на время своей длительности ключи в блоке 168, через которые "код 1" поступает в освободившиеся регистры 170, 171. Сумматор 177 выполняет сложение код 0 + код 0. С приходом второго импульса 12 МГц в триггер 167 код суммы из сумматора выдается в блок 176, при этом соответственно подключению идет деление кода суммы на два и с выхода блока 176 идет на выход код №1

А сигнал U_выд2 со второго выхода триггера одновременно выдает с регистра 175 "код 0" на выход, который является кодом №2, следующий за кодом №1 через 41,5 нс, из регистра 170 выдается "код 1" в регистр 174 /на хранение 83 нс/ и через диоды в сумматор 177, из регистра 173 выдается в сумматор "код 0", открывает ключи в блоке 169, и "код 2" заполняет разряды регистров 172, 173. Регистры 174, 175 выполняют хранение поступающих в них кодов 83 нс, а так как первая половина времени хранения 41,5 нс приходится на время сложения в сумматоре 177 и задержку в блоке 176, то после второй половины /41,5 нс/ хранения с регистров 174, 175 коды выдаются соответствующими сигналами U_выд. С приходом третьего импульса в триггер 167 из сумматора 177 выдается код №3

на выход. А сигнал U_выд3 с первого выхода триггера одновременно выдает: с регистра 174 код №4 "код 1", с регистра 171 "код 1" в сумматор 177, с регистра 172 "код 2" в регистр 175 и через диоды в сумматор, открывает ключи в блоке 168, и "код 3" заполняет регистры 170, 171. Сумматор выполняет сложение "код 1 + код 2". С приходом четвертого импульса в триггер 167 он выдает из сумматора код суммы в блок 176, и с него на выход идет код №5

а сигнал U_выд4 со второго выхода триггера одновременно выдает: с регистра 175 код №6 "код 2", с регистра 173 "код 2" в сумматор и с регистра 170 "код 3" в регистр 174 и через диоды в сумматор, открывает ключи в блоке 169, и следующий "код 4" заполняет регистры 172, 173. Сумматор выполняет сложение "код 2 + код 3". С приходом 5-го импульса в триггер 167 из сумматора 177 выдается код суммы в блок 176 и с него идет на выход код №7

а сигнал U_выд5 с первого выхода триггера выдает: из регистра 174 код №8 "код 3" на выход, с регистра 171 "код 3" в сумматор 177, с регистра 172 "код 4" в регистр 175 и через диоды в сумматор, открывает ключи в блоке 168, регистры 170, 171 заполняются кодом "код 5". Сумматор выполняет сложение "код 3 + код 4". С приходом 6-го импульса в триггер он выдает из сумматора код суммы в блок 176, следует деление кода суммы на два, и на выход блока 176 идет код №9

А сигнал U_выд6 со второго выхода триггера одновременно выдает: из регистра 175 код №10 "код 4", из регистра 170 "код 5" в регистр 174 и через диоды в сумматор, из регистра 173 "код 4" в сумматор, открывает ключи в блоке 169, и регистры 172, 173 заполняются следующим кодом "код 6". Сумматор 177 выполняет сложение "код 4 + код 5". С приходом седьмого импульса 12 МГц в триггер 167 процессы повторяются. Выходы блока 176 элементов задержек и выходы регистров 174, 175 поразрядно объединены и являются выходами блока 129. Коды с блоков 129, 137, 148 с частотой 24 МГц поступают на входы соответственно блоков 130, 138, 149 ключей. Коды с блока 129 поступают в блоке 130 ключей параллельно на входи первого 178 и второго 179 блоков ключей. При правом кадре стереопары сигнал с первого выхода блока 164 открывает ключи в блоке 178 /фиг.13/ и коды правого кадра через открытые ключи блока 178 поступают на информационный вход первого накопителя 132 /140, 151/ кодов кадра. При левом кадре стереопары сигнал со второго выхода блока 164 /фиг.13, 23/ открывает ключи в блоке 179 и коды в параллельном виде поступают на информационный вход второго накопителя 131 кодов кадра. Коды правого кадра поступают: сигнала R в первый накопитель 132 кодов кадра, сигнала G в первый накопитель 140 кодов кадра и сигнала В в первый накопитель 151 кодов кадра. Коды левого кадра поступают: сигнала R во второй накопитель 131 кодов кадра, сигнала G во второй накопитель 139 кодов кадра, сигнала В во второй накопитель 150 кодов кадра.Doubling the samples in the row reduces the code period by half and amounts to 41.5 ns

those. 24 MHz Therefore, the addition process takes 41.5 ns: from the receipt of codes in the adder until the result appears at the output of block 176. The adder from K555IM6 microcircuits [8, p. 258] with the addition time of 24 ns, remaining 17.5 ns / 41.5 ns - 24 / there is a delay in block 176. With the arrival of the first 12 MHz pulse in trigger 167/11 / from its first output, the signal U output ₁ simultaneously / synchronously / outputs: from register 171 "code 0" / from one zeros / to the first inputs of the adder 177, from the register 172 gives a "code 0" to the input of the register 175 and through the diodes to the second inputs of the adder 177 / output signals and reset the bits histr / and opens for the duration of its keys in block 168, through which the "code 1" enters the freed-up registers 170, 171. Adder 177 performs addition of code 0 + code 0. With the arrival of a second pulse of 12 MHz in trigger 167, the sum code from the adder issued in block 176, while the connection accordingly is the division of the sum code into two and from the output of block 176 goes the output code number 1

And the signal U _vy2 from the second trigger output simultaneously outputs from register 175 "code 0" to the output, which is code No. 2, following code No. 1 after 41.5 ns, from register 170, "code 1" is issued to register 174 / on storage is 83 ns / and through diodes to the adder 177, from the register 173 “code 0” is issued to the adder, opens the keys in block 169, and “code 2” fills the bits of the registers 172, 173. Registers 174, 175 carry out the storage of the codes coming into them 83 ns, and since the first half of the storage time 41.5 ns falls on the addition time in the adder 177 and the delay in block 176, then after the second half n / 41.5 ns / storage from registers 174, 175 codes are issued by the corresponding signals U _vyd . With the arrival of the third pulse in the trigger 167 from the adder 177 issued code number 3

to the exit. And the signal U _iss3 from the first output of the trigger simultaneously produces: from register 174 code No. 4 "code 1", from register 171 "code 1" to the adder 177, from register 172 "code 2" to the register 175 and through diodes to the adder, opens keys in block 168, and "code 3" fills the registers 170, 171. The adder performs the addition of "code 1 + code 2". With the arrival of the fourth pulse in the trigger 167, he issues the sum code from the adder to block 176, and code No. 5 is output from it

and the signal U _vy4 from the second trigger output simultaneously gives: from register 175 code No. 6 "code 2", from register 173 "code 2" to the adder and from register 170 "code 3" to register 174 and through diodes to the adder, opens the keys in block 169, and the next "code 4" fills the registers 172, 173. The adder performs the addition of "code 2 + code 3". With the arrival of the 5th pulse in trigger 167 from the adder 177, the sum code is issued to block 176 and code No. 7 is output from it

and the signal U _vyd5 from the first output of the trigger produces: from register 174 code No. 8 "code 3" to the output, from register 171 "code 3" to the adder 177, from register 172 "code 4" to the register 175 and through diodes to the adder, opens the keys in block 168, registers 170, 171 are filled with the code "code 5". The adder performs the addition of "code 3 + code 4". With the arrival of the 6th pulse in the trigger, it gives the sum code to block 176 from the adder, the code is divided by two, and code No. 9 goes to the output of block 176

And the signal U _vyd6 from the second output of the trigger simultaneously produces: from register 175 code No. 10 "code 4", from register 170 "code 5" to register 174 and through diodes to the adder, from register 173 "code 4" to the adder, opens the keys in block 169, and the registers 172, 173 are filled with the following code "code 6". The adder 177 performs the addition of "code 4 + code 5". With the arrival of the seventh pulse of 12 MHz in the trigger 167, the processes are repeated. The outputs of block 176 of the delay elements and the outputs of registers 174, 175 are bitwise combined and are outputs of block 129. Codes from blocks 129, 137, 148 with a frequency of 24 MHz are received at the inputs of the blocks 130, 138, 149 of the keys, respectively. Codes from block 129 are received in block 130 keys in parallel to the inputs of the first 178 and second 179 blocks of keys. With the right frame of the stereo pair, the signal from the first output of block 164 opens the keys in block 178 / Fig. 13/ and the codes of the right frame through the public keys of block 178 are fed to the information input of the first drive 132/140, 151 / frame codes. With the left frame of the stereo pair, the signal from the second output of block 164 (Fig. 13, 23) opens the keys in block 179 and the codes are sent in parallel to the information input of the second drive 131 of the frame codes. Codes of the right frame are received: signal R to the first drive 132 of the frame codes, signal G to the first drive 140 of the frame codes and signal B to the first drive 151 of the frame codes. Codes of the left frame are received: signal R to the second drive 131 of the frame codes, signal G to the second drive 139 of the frame codes, signal B to the second drive 150 of the frame codes.

The work of blocks 180 registers, Fig, 16.

The signals of the bits of the codes are sent in parallel to the third inputs of the bits of the registers 184. The filling of the registers with the line codes begins with the opening of the first key 181 with a 50 Hz pulse, which transmits 24 MHz sampling pulses to the input of the pulse distributor 183. The pulses from the outputs of block 183 are sequentially fed to the first inputs of the bits of eight registers 184. Upon completion of the registers 184 from the last output / 800 / of block 183, the signal closes the key 181 and opens the first key 181 in the second block 180 ₂ as a control output signal, the registers of which are filled second line codes. For a frame period of 20 ms, the registers 184 of all blocks 180 _1-600 in the first drives 132, 140, 151 / second 131, 139, 150 / frame codes will be sequentially filled. By filling the storage registers in frame with the last block of codes 180 ₆₀₀ opens register control signal in all blocks 180/4 input / second keys 182, which are passed one pulse _vyd U / 30 kHz / synchronous issuing from all 180 blocks all registers _1-600 the frame codes in parallel to their blocks 134, 142, 153/133, 141, 152 / of the shapers of the control signals and zero the bits of the registers 184. Each drive of the frame codes has 3840000 outputs / 800 × 8 × 600 /, which are connected to the same inputs in each from blocks of control signal conditioners, each of which has 480000/800 × 600 / converters "code - the duration of the radiation." The outputs of blocks 134, 142, 153, of which 1440000/480000 × 3 /, are connected to the same inputs of the right screen 155, similarly the outputs of blocks 133, 141, 152, which are also 1440000, are connected to the same inputs of the left screen 156. In connection with With a large number of connections, the best option for reliable operation will be the execution of these blocks on the back side of your screen in a single case with it and in a non-separable design.

System operation.

The photoelectric Converter 1 generates analog video signals of the right and left frames of the stereo pair, which are converted by the 49-54 ADC into 8-bit codes with a sampling rate of 12 MHz. Shapers 57, 58 codes convert parallel codes into sequential ones, the last three samples in each line are three sound codes Sv1 and Sv2. The units in the codes are replaced with positive and negative half-sinusoids of the 96 MHz monofrequency. The information of the codes of the right and left frames is transmitted by the upper 1536 MHz side frequency and the lower 1344 MHz side frequency of one carrier 1440 MHz. The receiving side simultaneously receives two radio signals by two paths for receiving and processing codes, performs detection, extracts the clock signal of the SSI and SIS, the frequency synthesizer 159 reproduces the corresponding carrier frequency. Representation of units in codes returns to impulses. Codes of signals R, G, In stereo pairs are sent through their channels. Blocks 129, 137, 148 double the number of samples in each lad. Playable video mode 800 samples × 600 lines × 50 Hz. Discretization of 24 MHz codes. In the drives / first / frame codes 132, 140, 151, the right frame codes are concentrated, in the second drives of frame codes 131, 139, 150 the left frame codes are concentrated. With the arrival of the control signal from the first output of block 164, codes from the first drives 132, 140, 151 are issued to blocks 134, 142, 153, generating control signals from them for powering the micro-LEDs in the screen 155. Codes of the left frame go through a similar process. The viewer simultaneously watches the image on the right screen 155 with the right eye, the image on the left screen 156 with the left eye. The right and left images are received alternately after 20 ms. The image is formed on the screen by flashing synchronously all the pixels of the frame, which eliminates the need for line and frame scans.

The first 165 and second 166 sound channels reproduce stereo sound. Sound codes are converted into analog signals, amplified and reproduced by loudspeakers. The receiving side should be made of two parts. The first includes the paths for receiving and processing codes in blocks 124, 125, 126, 127, 135/143, 144, 145, 146, 154 /, 128, 136, 147, 129, 137, 148, 130, 138, 149, channel for generating control signals and sound channels, in the second part include the first and second drives of frame codes, blocks for generating control signals and LED screens 155, 156. The second part is appropriately placed in the helmet 157 of the viewer in a single design.

Information sources

1. Patent No. 2256298, cl. H04N 11/24, bull. 19 from 07/10/05, a prototype.

2. Shumilin and other radio transmitting devices. M., 1981, p. 234-235.

3. Fridland I.V., Soshnikov V.G. Automatic control systems in video recorders. M., 1988, p.118, p.122, fig. 5.10.

4. "Radio" No. 9, p. 47, 2004

5. Brodsky M.A. TVs color image. Minsk, 1988, p.132, fig. 4.2.

6. Radio communications, broadcasting and television. Ed. A.D. Fortushenko, M., 1981, p. 146.

7. Barkan V.F., Zhdanov V.K. Amplification and impulse technology. M., 1984, p. 209.

8. Digital integrated circuits. Minsk, 1991, p. 258.

Claims (1)

Stereo TV system,  containing the transmitting side,  including photoelectric converter (PEC),  first through sixth analog-to-digital converters (ADCU),  the inputs of which are connected to the corresponding outputs of the solar cells,  the first and second ADCs of the sound signal,  to the information inputs of which sound signals are given,  serially connected sine oscillation generator and frequency synthesizer,  first and second code generators,  first and second self-propelled pulse distributors and a radio signal transmitter,  including two channels  the first channel contains a serially connected carrier frequency amplifier,  first shaper of a single-band signal,  the second input of which is connected to the first output of the first code generator,  and an output amplifier,  the second channel includes serially connected a second shaper of a single-band signal,  the second input of which is connected to the output of the second code generator,  and an output amplifier,  the first,  the second and third information inputs of the first code generator are connected to the outputs of the first, respectively,  the second ADC and to the output of the first ADC sound signal,  the input of the first self-propelled pulse distributor is connected to the second output of the first code generator,  and its outputs are combined and connected to the fourth information input of the first code generator,  the first,  the second and third information inputs of the second code generator are connected respectively to the outputs of the third ADC,  to the output of the second ADC of the sound signal and to the output of the first self-propelled pulse distributor,  the outputs of the second self-propelled pulse distributor are combined and connected to the fourth information input of the second code generator,  Frequency synthesizer outputs are connected:  the second - to the first control inputs of the first and second code generators,  to the first control inputs of the first and second ADC sound signal,  the third output is to the third control inputs of the first and second ADCs of the sound signal,  the fourth - to the second control inputs of the first and second code generators,  the eighth - to the input of the amplifier of the carrier frequency of the radio signal transmitter,  FEP contains the first (right) lens,  connected in series to the first amplifier and the first piezoelectric deflector with a reflector at the end,  located in the focal plane of the first lens,  the first source of positive reference voltage  the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector,  a second source of negative reference voltage,  the output of which is connected to the third inputs of the pen amplifier and the first piezoelectric deflector,  connected in series to a second amplifier and a second piezoelectric deflector,  the free end of which is made of two faces at an appropriate angle to each other,  each face has its own reflector,  the first reflector of the second piezoelectric deflector is optically connected to the reflector of the first piezoelectric deflector,  a third source of positive reference voltage,  the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector,  a fourth source of negative reference voltage,  the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector,  contains a second (left) lens,  located to the left of the right lens at an appropriate distance and whose optical axis is parallel to the optical axis of the right lens,  connected in series with a third amplifier and a third piezoelectric deflector with a reflector at the end,  located in the focal plane of the second lens and optically connected to the second reflector of the second piezoelectric deflector,  fifth source of positive reference voltage  the output of which is connected to the second inputs of the third amplifier and the third piezoelectric deflector,  sixth source of negative reference voltage,  the output of which is connected to the third inputs of the third amplifier and the third piezoelectric deflector,  line scan unit  the input of which is connected to the seventh output of the frequency synthesizer,  and the output is connected in parallel to the inputs of the first and third amplifiers,  frame scan unit  including a series-connected element And,  the first and second inputs of which are connected to the corresponding outputs of the frequency synthesizer,  master oscillator and summing amplifier,  the second input of which is connected to the first input of the AND element,  the control input of the summing amplifier is connected to the output of the element And,  and the output is the output of the frame scan unit and is connected to the first input of the second amplifier,  FEP includes the first and second dichroic mirrors,  located one after another and against the first reflector of the second piezoelectric deflector,  the first,  second,  third micro lenses  the first,  second,  third photodetectors,  the first,  second,  third preamplifiers,  the input window of the first photodetector is optically connected through the first micro lens and the first dichroic mirror with the first reflector of the second piezoelectric deflector,  input window of the second photodetector,  optically connected through the second micro lens and through both dichroic mirrors to the first reflector of the second piezoelectric deflector,  the input window of the third photodetector through the third micro lens,  the second dichroic mirror and through the first dichroic mirror is optically connected to the first reflector of the second piezoelectric deflector,  the outputs from the first to third photodetectors are connected to the inputs respectively of the first,  second  third preamplifiers,  whose outputs are the first,  second  FEP third outputs,  which contains the third and fourth dichroic mirrors,  located one after another and against the second reflector of the second piezoelectric deflector,  fourth,  fifth,  sixth micro lens,  fourth,  fifth,  sixth photodetectors,  fourth,  fifth,  sixth preamplifiers,  the input window of the fourth photodetector is optically connected through the fourth micro-lens and the third dichroic mirror to the second reflector of the second piezoelectric deflector,  the input window of the fifth photodetector is optically connected through the fifth micro-lens and through both dichroic mirrors to the second reflector of the second piezoelectric deflector,  the input window of the sixth photodetector is optically connected through the sixth micro lens,  a fourth dichroic mirror and through a third dichroic mirror with a second reflector of the second piezoelectric deflector,  the outputs of the fourth to sixth photodetectors are connected to the inputs of the fourth to sixth pre-amplifiers,  whose outputs are fourth,  fifth and sixth outputs of the solar cells,  the first through sixth ADCs are identical,  each includes a series-connected amplifier and a piezoelectric deflector with a reflector at the end,  source of positive reference voltage  the output of which is connected to the second inputs of the amplifier and piezoelectric deflector,  negative reference voltage source  the output of which is connected to the third inputs of the amplifier and piezoelectric deflector,  emitter from a pulsed LED,  slit diaphragm and micro lens,  series-connected multi-element photodetector line and encoder,  the inputs of the multi-element photodetector line are optically connected through the piezoelectric reflector to the emitting side of the LED,  and the encoder outputs are ADC outputs,  whose control input is the pulse LED input,  the first code generator contains four channels,  the first channel includes a series-connected first block of AND elements,  the first and second elements OR and the first output key,  and the first self-propelled pulse distributor,  the outputs of which are connected to the second inputs of the block of elements AND,  the second channel includes a series-connected second block of elements AND,  the third and fourth elements OR and the second output key,  and a second self-propelled pulse distributor,  the outputs of which are connected to the second inputs of the second block of AND elements,  the third channel includes a series-connected third block of AND elements and a fifth OR element,  the output of which is connected to the second input of the second OR element,  and includes a third self-propelled pulse distributor,  the outputs of which are connected to the second inputs of the third block of AND elements,  the fourth channel includes a fourth block of AND elements and a sixth OR element, connected in series  and a fourth self-propelled pulse distributor,  the outputs of which are connected to the second inputs of the fourth block of AND elements,  the output of the sixth OR element is connected to the second input of the fourth OR element,  the first code generator contains the first and second keys,  and series-connected pulse counter and decoder,  the first output of which is connected to the first control input of the first key,  the output of which is connected to the inputs of the first and second self-propelled pulse distributors,  the second output of the decoder is connected to the second control input of the first key and to the first control input of the second key,  the output of which is connected to the inputs of the third and fourth self-propelled pulse distributors,  the third output of the decoder is the second output of the first code generator,  whose first output is the combined outputs of the first and second output keys,  information inputs of the first code generator are:  the first and second are the first inputs of the first and second blocks of AND elements, respectively  third - the first inputs of the third and fourth blocks of elements And,  the fourth is the third input of the second OR element,  control inputs are:  the first is the combined inputs of the first and second keys and the counting input of the pulse counter,  the second is the combined signal inputs of the first and second output keys,  the third is the control input of the pulse counter,  the second code generator comprises three channels,  the first channel includes a series-connected first block of AND elements,  the first and second elements OR and the first output key,  and the first self-propelled pulse distributor,  the outputs of which are connected to the second inputs of the first block of AND elements,  the second channel includes a series-connected second block of elements AND,  third element OR  the output of which is connected to the second input of the second OR element in the first channel,  and a second self-propelled pulse distributor,  the outputs of which are connected to the second inputs of the second block of AND elements,  the third channel includes a series-connected third block of elements AND,  fourth,  fifth elements OR and a second output key,  and a third self-propelled pulse distributor,  the outputs of which are connected to the second inputs of the third block of AND elements,  the second code generator includes the first and second keys,  and series-connected pulse counter and decoder,  the first output of which is connected to the first control input of the first key,  the output of which is connected to the input of the first self-propelled pulse distributor,  the second output of the decoder is connected to the second control input of the first key and to the first control input of the second key,  the output of which is connected to the inputs of the second and third self-propelled pulse distributors,  information inputs are:  first - the first inputs of the first block of AND elements,  second - the first inputs of the second and third blocks of elements And,  the third is the third input of the second OR element,  the output is the combined outputs of the first and second output keys,  control inputs are:  the first is the combined inputs of the first and second keys and the counting input of the pulse counter,  the second is the combined signal inputs of the output keys,  the third is the control input of the pulse counter,  and containing the receiving side,  including antenna  two paths for receiving and processing codes,  the outputs of which are connected to the antenna,  the second inputs are connected to the first group of outputs of the control unit,  viewer's helmet  a channel for generating control signals and two sound channels,  the first path for receiving and processing codes contains serially connected unit for receiving a radio signal,  whose first input is connected to the antenna,  the second group of inputs is connected to the first group of outputs of the control unit,  radio frequency amplifier,  bipolar amplitude detector,  code processing channel R,  comprising a series-connected first pulse shaper,  the input of which is connected to the first output of a bipolar amplitude detector,  signal register R and code processing unit,  and a second channel for processing G codes,  comprising a series-connected second code generator,  connected to the second output of a bipolar amplitude detector,  signal register G and code processing unit,  the second path for receiving and processing codes contains serially connected unit for receiving a radio signal,  whose first input is connected to the antenna,  the second group of inputs is connected to the first group of outputs of the control unit,  radio frequency amplifier,  bipolar amplitude detector and channel processing code B,  comprising a third pulse shaper connected in series,  the input of which is connected to the first output of a bipolar amplitude detector,  signal register B and code processing unit,  the second path for receiving and processing codes contains a fourth pulse shaper,  the input of which is connected to the second output of the bipolar amplitude detector,  the channel for generating control signals includes a sequentially connected block selection horizontal synchronization pulse (SSI),  frequency synthesizer  key,  pulse counter and decoder,  the second output of which is connected to the control input of the pulse counter and to the second control input of the key,  the first input of the SSI isolation block is connected to the output of the first pulse shaper,  the third input is to the output of the third pulse shaper,  the output is connected to the first input of the frequency synthesizer and to the first control input of the key,  the second group of inputs of the frequency synthesizer is connected to the second group of outputs of the control unit,  the first and second information inputs of the first sound channel are connected to the outputs of the first and second pulse shapers, respectively,  the first and second information inputs of the second sound channel are connected to the outputs of the third and fourth pulse shapers, respectively  the first and second control inputs of the sound channels of the same name are combined and connected respectively to the first and second outputs of the decoder,  the same third and fourth control inputs of sound channels are combined and connected respectively to the first and second outputs of the frequency synthesizer,  whose outputs are connected:  clock frequency output (first) - to the first control inputs of the signal registers R,  G  AT,  sampling frequency output (third) - to the second control inputs of the signal registers R,  G  To and to the control inputs of the code processing blocks,  carrier frequency output (fifth) - to the third control inputs of the radio signal receiving units in the first and second paths for receiving and processing codes,  code processing units are identical,  each includes a trigger,  whose input is the control input of the block,  first to fourth registers,  fifth and sixth registers,  adder and delay element block,  the inputs of which are connected to the corresponding outputs of the adder,  sixteen diodes  first and second key blocks,  the inputs of which are bitwise combined and are information inputs of the code processing unit,  the information inputs of the first and second registers are bitwise combined and connected to the outputs of the first block of keys,  the information inputs of the third and fourth registers are bitwise combined and connected to the outputs of the second block of keys,  the outputs of the first register are connected to the inputs of the fifth register and through diodes to the first inputs of the adder,  to which the outputs of the second register are connected,  the outputs of the third register are connected to the inputs of the sixth register and through the diodes are connected to the second inputs of the adder,  to which the outputs of the fourth register are connected,  control inputs of the first key block,  second  fifth and third registers are combined and connected to the first output of the trigger,  control inputs of the second block of keys,  the first  the fourth and sixth registers are combined and connected to the second output of the trigger,  the outputs of the code processing unit are the bitwise combined outputs of the fifth,  sixth registers and outputs of the block of delay elements,  the horizontal sync pulse allocation unit includes first to third pulse counters,  elements one through three are NOT  the first and second elements And and the diode,  the outputs of the first and second pulse counters are connected to the inputs of the first element And,  whose output and the output of the third pulse counter are connected to the inputs of the second AND element,  the output of which is the output of the block,  information from the first to third inputs of the block are the counting inputs of the pulse counters,  inputs from the first to third elements are NOT connected respectively to the counting inputs from the first to third pulse counters,  the outputs of the elements are NOT and the output of the second element AND through the diode are combined and connected in parallel to the control inputs of the pulse counters,  characterized in  that the first key is connected in series on the transmitting side,  the input of which is connected to the sixth output of the frequency synthesizer,  and the control input is connected to the output of the And element in the frame scanning unit of the photomultiplier,  and trigger  second and third keys,  the signal inputs of which are combined and connected to the second output of the frequency synthesizer,  the first control input of the second key and the second control input of the third key are connected to the first output of the trigger,  the second control input of the second key and the first control input of the third key are connected to the second output of the trigger,  the output of the second key is connected in parallel to the control (clock) inputs of the first,  second  third ADC  the output of the third key is connected in parallel to the control (clock) inputs of the fourth,  fifth  Sixth ADC  outputs of the first and fourth ADCs,  the second and fifth ADCs are bitwise integrated and connected respectively to the first and second information inputs of the first code generator,  the outputs of the third and sixth ADCs are bitwise integrated and connected to the first information input of the second code generator,  the first and second inputs of the FEP frame scanning unit are connected respectively to the fifth and first outputs of the frequency synthesizer,  to the fifth output of which the second control inputs of the first and second ADCs of the sound signal are connected,  and a pulse counter is entered,  the counting input of which is connected to the second output of the first code generator,  the output of the second discharge of the pulse counter is connected to the control input of the second self-propelled pulse distributor,  and the control input of the pulse counter is connected to the first output of the frequency synthesizer,  in the first code generator, the second control input of the second key is connected to the third output of the decoder,  the third input of the fourth OR element is connected to the third input of the second OR element,  in the second code generator, the second control input of the second key is connected to the third output of the decoder,  and the fourth information input of the second code generator is the second input of the fifth OR element,  on the receiving side, the second input of the horizontal sync pulse allocation unit (SSI) is connected to the output of the second pulse shaper,  into each of the channels for processing R codes,  G  The key block is connected in series,  first frame code storage,  whose inputs are connected to the first outputs in the key block,  second frame code storage,  the inputs of which are connected to the second outputs in the key block,  a first control signal generating unit,  the inputs of which are connected to the outputs of the first drive frame codes,  a second control signal generating unit,  the inputs of which are connected to the outputs of the second drive frame codes,  on the receiving side, a right flat panel LED screen (SD screen) is introduced,  the corresponding inputs of which are connected to the corresponding outputs of the first control signal generating units in the R code processing channels,  G  AT,  and left flat panel LED screen,  the corresponding inputs of which are connected to the corresponding outputs of the second control signal generating units in the R code processing channels,  G  AT,  key blocks  first and second frame code drives,  first and second blocks for generating control signals,  the right and left LED screens are respectively located in the helmet of the viewer,  key blocks are identical  each includes first and second key blocks,  containing eight keys each,  the information input of the key block are bitwise integrated from the first to eighth inputs of the first and second key blocks,  control inputs are:  the first is the control input of the first key blocks,  the second is the control input of the second block of keys,  the first output is the first to eighth outputs of the first block of keys,  the second - from the first to eighth outputs of the second block of keys,  frame code drives are identical,  each includes blocks of registers by the number of lines (600) in the frame,  information input are bitwise combined inputs of six hundred register blocks,  control inputs are:  the first is the first control input of the first block of registers; the second is the combined second control inputs of the block of registers,  the third is the combined third control inputs of the register blocks,  each control output of the previous block of registers is the control input of each subsequent block of registers,  the control output of the last / 600th / register block is connected in parallel to the fourth control inputs of all register blocks,  the outputs of the drive code frame are the outputs of all blocks of registers,  the second control inputs of the first and second drives code frames are combined and connected to the sixth output of the frequency synthesizer,  to the fourth output of which the combined third control inputs of the first and second drives of the frame codes are connected,  register blocks are identical,  each includes the first and second keys,  pulse distributor and eight registers,  the information input of the block of registers are bitwise combined third inputs of the bits of eight registers,  outputs are parallel outputs of all bits of eight registers (800 × 8),  control inputs are:  the first is the first control input of the first key,  the second is the signal input of the second key,  the third is the signal input of the first key,  fourth - the first control input of the second key,  the output of the first key is connected to the input of the pulse distributor,  the outputs of which are connected in series to the first inputs of the bits in parallel to eight registers,  the last output of the pulse distributor is connected to the second control input of the first key and is the control output of the register block,  the output of the second key is connected in parallel to the second inputs of the bits of the eight registers and to the second control input of the second key,  control signal generating units are identical,  each includes a pulse generator and, according to the number of resolutions in the frame (800 × 600), code-to-radiation-time converters,  which are identical and each includes a series-connected first key,  subtracting pulse counter  decoder and second key,  and power source  the signal input of the second key is connected to the output of its power source,  the output of the first key is connected to the counting input of the subtracting pulse counter,  the decoder output is connected to the second control inputs of the first and second keys,  the information input of the Converter are the first to eighth inputs of a subtracting pulse counter,  and its output is the output of the second key,  the first control inputs of the first and second keys of all converters and the input of the pulse generator are combined and are the control input of the control signal generation unit,  right and left flat panel LED screens (LED screens) are identical,  each contains elements in the matrix by the number of frame resolutions (800 × 600),  the matrix element includes three LED cells (SD cells),  each of which includes a white micro-LED and a color filter of one of the primary colors R,  G  AT,  located on the radiating side of the micro LED,  which are performed by microelectronic technology in the screen material,  the input of each micro LED is connected to the output of its code-to-radiation duration converter in the corresponding control signal generation unit,  a block for separating stereo clock pulses (SIS) and a block of frame pulses are introduced into the channel for generating control signals  the first,  the second and third inputs of the block allocation of the SIS are connected:  the first is to the third input of the horizontal sync pulse allocation block,  the second - to the output of the fourth pulse shaper in the second path of receiving and processing codes,  the third is to the output of the block selection line synchronization pulses,  the first input of the frame pulse block is connected to the seventh output of the frequency synthesizer,  the second input is connected to the output of the ICU allocation unit,  the stereo clock separation unit includes first and second pulse counters,  the counting inputs of which are respectively the first and second information inputs of the block allocation of the SIS,  the first and second elements are NOT,  the inputs of which are connected to the counting inputs of the first and second pulse counters, respectively  the first and second elements And,  the inputs of the first element And are connected to the outputs of the first and second pulse counters,  the output of the first AND element and the third information input of the ICU allocation unit are connected to the inputs of the second AND element,  the output of which is the output of the block allocation of the SIS,  the output of the elements is NOT and the output of the second element AND through the diode are combined and connected in parallel to the control inputs of the pulse counters,  the frame pulse unit includes a series-connected key and trigger,  the information input of the block is the signal input of the key,  connected to the seventh output of the frequency synthesizer,  the control input is the control input of the key,  connected to the output of the block allocation of the SIS,  outputs are:  the first is the first trigger output,  connected in parallel to the first control inputs of the key blocks,  to the first control inputs of the first drive codes of the frame and to the control inputs of the first blocks of the formation of control signals,  the second is the second output of the trigger,  connected in parallel to the second control inputs of the first,  second and third key blocks,  to the first control inputs of the second drive codes of the frame and to the control inputs of the second blocks of the formation of control signals.

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