RU2214043C2 - Frequency synthesizer - Google Patents

Abstract

FIELD: radio engineering; local oscillators for radio receivers and transmitters. SUBSTANCE: frequency synthesizer has direct digital synthesizer; filter; phase-locked loop circuit set up of variable-frequency oscillator, variable-ratio frequency divider, phase-frequency detector, and low-frequency filter, all ring-connected in series; digital adder; and solver that functions to compute fractional part of division ratio of direct digital frequency synthesizer and also to generate signal that changes coarse frequency control code and signal that changes input code of direct frequency synthesizer. EFFECT: reduced level of parasitic components in output signal spectrum. 1 cl, 1 dwg

Description

 The invention relates to radio engineering and can be used in radio receivers and radio transmitting devices as a local oscillator.

 A known frequency synthesizer with phase-locked loop (PLL), excited by a digital synthesizer with direct frequency synthesis (DS), the closest in technical essence to the proposed synthesizer and selected as a prototype.

 The frequency synthesizer comprises a digital signal converter having an input for fine frequency adjustment and an input of synchronizing signals for receiving, respectively, external phase data and external clock signals, and an output at which a reference signal is generated; a filter having an input connected to an output of a digital synthesizer and an output; a PLL with an input connected to the output of the filter, a coarse frequency control input for receiving a code corresponding to a division coefficient N of the frequency divider, and an output on which a synthesizer signal is generated [1].

 DS is used to form small discharges of the frequency of the synthesizer output signal (fraction of hertz). When divided by a fractional coefficient, due to the unevenness of the output sequence, undesirable discrete side components are formed, in which the detuning frequencies from the output signal can be very small (low).

 The disadvantage of the prototype is that low-frequency discrete side components (interference) at the output of the CA, falling into the passband of the PLL, modulate the frequency of the output signal. This is reflected in the spectrum of the output signal, in which there will be discrete side components due to interference at the output of the CA.

 The objective of the present invention is to reduce the level of undesirable discrete side components in the spectrum of the output signal.

 Using the proposed technical solution will reduce the levels of undesirable discrete side components by increasing the frequency of their detuning from the output signal of the CA with subsequent filtering by the PLL.

 The solution to the problem is achieved by the fact that in the frequency synthesizer containing the digital signal converter having an input for fine frequency adjustment and an input of synchronizing signals for receiving respectively external phase data and external clock signals and an output on which a reference signal is generated; a filter having an input connected to an output of a digital synthesizer and an output; PLL circuit, consisting of a tunable oscillator (PG) sequentially connected in a ring, a variable divider frequency divider (DPKD), a frequency-phase detector (ChFD) and a low-pass filter (LPF) having an input connected to the filter output, a coarse input adjusting the frequency for receiving a code corresponding to the division coefficient N of the DPCD, and the output on which the synthesizer signal is generated, a decoding device is introduced that has two inputs for receiving code data of fine and coarse frequency adjustments and two outputs, one of which is connected to the input fine adjustment frequency CA; and a digital adder having a first input for receiving coarse frequency control code data, an output that is connected to a coarse frequency input of the PLL, and a second input that is connected to a second output of the resolver.

 The drawing shows a structural diagram of a synthesizer, which contains built on the basis of the accumulating adder CA 1, having an input 2 of the exact frequency control, which is the information input of the accumulating adder, and an input 3 of synchronizing signals for receiving respectively external phase data and external clock signals and output 4; a filter 5 having an input connected to the output of the CA 1 and output 6; PLL 7, consisting of series-connected PG 7.1, DPKD 7.2, ChFD 7.3 and LPF 7.4, and having an input connected to output 6 of filter 5, input 8 of the coarse frequency control for receiving a code corresponding to the division coefficient N of the DPKD, and the output 9, on which a synthesizer signal is generated; a resolving device (RU) 10 having two inputs and two outputs; a digital adder 11 with two inputs and one output, the first for receiving coded frequency control code data, the second for changing the output code that is fed to the DPKD input, in addition, the first and second RC inputs are connected respectively to inputs 12 of the exact and 13 frequency control, the first output is connected to the input of the fine frequency control of the DS 1, and the second output is connected to the second input of the digital adder 11.

 RU 10 can be implemented on any device that includes data input / output ports, random access memory (RAM), read-only memory (ROM) and can perform arithmetic operations. Such a device may be, for example, a microcontroller, microprocessor, single-chip microcomputer or personal computer. RU 10 performs computational operations according to the program previously recorded in it.

Since the main node of the CA, forming the frequency of the output signal, is the accumulating adder [2], then the output will be the frequency [3, 4]:
f _out = f _in • m / n = f _in / K = f _in / (K _c + K _dr ) (1)
where f _I - the frequency of the input signal of the CA;
n is the capacity of the accumulating adder;
m is the input code of the accumulating adder;
K is the frequency division coefficient of the central nervous system;
To _c is the integer part of the division coefficient;
To _dr - the fractional part of the division coefficient.

After passing through the filter 5, the signal is fed to the reference input of the PFD 7.3 of the PLL 7, the second input of which supplies a signal with PG 7.1 frequency divided by N in DPKD 7.2. As a result of comparing frequencies in ChFD 7.3 through the low-pass filter 7.4, the frequency stability of the output signal of PG 7.1 and the entire synthesizer is ensured, which will be [5]:
f _out.s = f _out • N = f _in • N • m / n, (2)
where N is the division coefficient of the frequency divider of the PLL.

The fractional part (K _dr ) in the division ratio can be up to (1/2) ³² , or even less. When the division by a fractional factor of the unevenness of the output sequence produced undesirable side-discrete components, in which the output signal from the frequency detuning and equal to multiples of f _O • K _etc. or f _O • _{(1-K, etc.).} The most dangerous unwanted discrete side components are those in which K _dr approaches zero or one. Since the frequency of unwanted discrete side components is very low, it is more difficult to filter subsequently.

For normal operation, it is necessary that the detuning of unwanted discrete side components in the output signal of the CA 1 be beyond the passband of the PLL, i.e.
f _O • K _etc. >> f or f _{cf. O} • _{(1-K, etc.)} >> f _cf. (3)
where f _cf is the passband of the PLL.

From the formula (1) K _dr = n / m-K _c , (4)
where K _c = Int [n / m] is the integer part of the division coefficient of the CA 1.

The permissible value of fractional division coefficients K _additional is determined by the formulas
K _dr ≥K _add or (1-K _dr ) ≥K _add (5)
and for which condition (3) is satisfied. K _{additional is} written with a value of n in ROM RU 10.

Upon receipt of the codes m and N at the inputs 12 and 13 RU 10 calculates K _dr according to the formula (4) and compares with K _add . If K _dr satisfies condition (5), then the code m from input 12 enters the input 2 of the CA 1 without change and a signal is supplied to the input of the digital adder 11, according to which the code from the input 13 without change is fed through the digital adder 11 to the PLL 7. If the code does not satisfy condition (5), then RU 10 calculates the new value of the input code CA 1 according to the formula
m1 = m • N / (N + ΔN) or ml = m • N / (N-ΔN), (6)
where ΔN is the change value of the coarse adjustment code, and the calculations are repeated.

If K _dr satisfies condition (5), then from the output of the RU 10 the code ml is fed to the input 2 of the CA 1, and from the second output of the RU 10 to the digital adder 11 the code ΔN or [-ΔN] is supplied. As a result of this, the code arriving at the DPKD 7.2 will be increased or decreased.

 The algorithm of the program is shown in figure 2.

 Comparative analysis shows that the proposed technical solution differs from the prototype in that the introduced solver and digital adder provide a cleaner spectrum of the synthesizer output signal by changing the division coefficient in the PLL of the PLL and setting a new value for the fractional part of the division coefficient of the digital synthesizer.

 Therefore, this technical solution meets the criterion of "novelty."

Literature
1. Pat. U.S. N4965533, H 03 L 7/18, 901023, Volume 1119, N 4, 1989

 2. V. Lobov, V. Steshenko, B. Shakhtarin. Digital synthesizers of direct synthesis frequencies. CHIP NEWS, 1 (10), 1997 pp. 16-21.

 3. A.V. Ryzhkov, V.N. Popov. Frequency synthesizers in radio technology. M .: Radio and communication. 1991.253p.

 4. D.N. Shapiro, A.A. Pain. Fundamentals of the theory of frequency synthesis. M .: Radio and communication. 1981. 179 p.

 5. V. Manasevich. Frequency synthesizers. Theory and design. M., 1979. 33-37 p.

Claims (1)

 A frequency synthesizer comprising a digital synthesizer with direct frequency synthesis (DS), having an input for fine frequency control and an input of synchronizing signals for receiving, respectively, external phase data and external clock signals, and an output on which a reference signal is generated, a filter having an input connected with the output of the DS and the output, a phase-locked loop (PLL), consisting of a tunable oscillator (PG) sequentially connected in a ring, a frequency divider with a variable division coefficient (DPCD), frequency-phase det a vector (ChFD) and a low-pass filter (LPF) having an input connected to the output of the filter, a coarse frequency control input for receiving a code corresponding to the division coefficient of the DPKD, and an output on which a synthesizer signal is generated, characterized in that a decisive a device (RU) having first and second inputs and first and second outputs, and a digital adder that has first and second inputs and an output, the first input of the RU connected to the input of the fine frequency control of the synthesizer, the first output connected to the input of the fine adjustment frequency of the DS, the second input is connected to the second input of the digital adder and to the input of the coarse frequency control of the synthesizer, and the second output of the switchgear is connected to the first input of the digital adder, the output of which is connected to the input of the coarse frequency control of the PLL, while the decider calculates the value of the fractional part of the coefficient division (Cdr) of a digital synthesizer with direct frequency synthesis, generates a signal that changes the coarse frequency control code, and a signal that changes the value of the input code of the digital synthesizer with direct synthesis of frequencies.