RU2183857C1 - Multichannel adapter for analog input-output - Google Patents

Abstract

FIELD: automatics, computing technique, possibly systems for accumulating and processing information, for controlling signal reception of analogue pickups and for outputting analog signals in the form of absolute voltage values, percentage voltage values and sine-cosine signals. SUBSTANCE: adapter includes controller of outer interface main circuit for information exchange, four amplifiers, analog-digital converter, m digital-analog converters, microprocessor, device for controlling analog-digital converter, device for controlling digital-analog converters, four switches for turning on testing mode, four multiplexers, m switches, reference voltage generator, clock device, inner parallel interface main circuit for information exchange, inner successive interface main circuit for information exchange. EFFECT: enhanced accuracy of conversion and noise immunity. 1 dwg

Description

 The invention relates to automation and computer technology and can be used in information collection and processing systems, as well as in control systems for receiving signals from analog sensors and issuing analog signals in the form of absolute voltage values, relative voltage values, and also in the form of sine-cosine signals.

 A device for interfacing a computer with communication channels [1], comprising a switch for input channels, a serial code to parallel conversion unit, a device information bus, a transceiver, an exchange unit, a clock generator, a block of output amplifiers (shapers), a micro memory instruction block, arithmetic logic block, mode register, micro command decoder and exchange acknowledgment block.

 Known multi-channel device for input-output of analog information [2], which is the closest to the proposed. The device comprises first to fourth switches, an inverter, a memory unit, a digital-to-analog converter, an amplifier, a comparator, an interface unit (controller of an external interface data exchange backbone), an arithmetic-logical unit, a register, and a multiplier. The inputs of the first switch are analog inputs of the device, the outputs of the first switch are connected to the first and second inputs of the second switch, the first and second outputs of which are connected respectively to the first and second inputs of the third and fourth switches, the first output of the second switch is connected through the inverter to the third inputs of the third and the fourth switch, the outputs of the fourth switch are connected to the information inputs of the memory block, the outputs of which are the analog outputs of the device, the first the output of the third switch is connected to the first input of the digital-to-analog converter, the output of which is connected to the input of the amplifier, the output of which is connected to the input of the comparator and the third input of the second switch, the fourth input of which is the input of the reference voltage of the device, the first group of inputs and outputs of the interface unit are information inputs and outputs devices, the second group of inputs and outputs of the interface unit is the inputs and outputs of the control device.

 The outputs of the microcommands of the control unit are connected to the information inputs of the arithmetic-logical unit, the group of outputs of the control unit is connected to the control inputs of the arithmetic-logical unit, the group of control inputs of the interface unit and the information inputs of the register, the output of the control unit is connected to the inputs of the register and interface unit, outputs the signs of the arithmetic-logical unit and the output of the comparator are connected to the inputs of the signs of the control unit, the information inputs and outputs of the arithmetic-logical unit are not connected to the information inputs and outputs of the interface unit and the multiplier, to the control inputs of the third and fourth switches and to the inputs of the digital-to-analog converter group, the first output of the register is connected to the control input of the second switch, the second and third outputs of the register are connected respectively to the inputs of the recording and reading of the multiplier, the outputs the first group of the register are connected to the address inputs of the memory block, the outputs of the second group of the register are connected to the address inputs of the multiplier, the second output of the third switch is connected n with a second input of the digital to analog converter.

 The disadvantages of the known devices are insufficient conversion accuracy and insufficient fault tolerance.

 The objective of the invention is to improve the accuracy of conversion and fault tolerance.

 The essence of the invention lies in the fact that the multichannel analog I / O adapter containing a digital-to-analog converter, an external interface controller for information exchange, the first amplifier, further comprises an analog-to-digital converter, m-1 digital-to-analog converters, where m is an integer greater than or equal to four, microprocessor, analog-to-digital converter control device, digital-to-analog converter control device, second amplifier, third amplifier, even the fourth amplifier, the first test mode enable switch, the second test mode enable switch, the third test mode enable switch, the fourth test mode enable switch, the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, m keys, the voltage reference driver, the synchronization unit, internal parallel interface trunk of information exchange, internal serial interface highway of information exchange.

 The interface inputs and outputs of the microprocessor, the control device of the analog-to-digital converter, the control devices of the digital-to-analog converters, the interface output of the analog-to-digital converter are connected to each other and to the first input-output of the controller of the external interface highway of information exchange using the internal parallel interface highway of information exchange, the first output of the analog-to-digital converter control device is connected to the signal input of the start gate the formation of the analog-to-digital converter, the second output of the analog-to-digital converter control device is connected to the input of the chip signal of the analog-to-digital converter, the third output of the analog-to-digital converter control device is connected to the input of the read signal of the analog-digital converter, the second input of the analog-to-digital control device the converter is connected to the output of the busy signal of the analog-to-digital converter.

 The outputs of the first, second, third and fourth switches on the test mode through the first, second, third and fourth amplifiers are connected respectively to the first, second, third and fourth inputs of the analog-to-digital converter, the first inputs of the first, second, third and fourth switches on the test mode connected to the outputs of the first, second, third and fourth multiplexers, respectively, the second input of the first test mode enable switch is connected to the first output of the voltage reference driver, the second the input of the third test mode enable switch is connected to the third output of the reference voltage driver, the second inputs of the second and fourth test mode enable keys are connected to a point with zero potential, the control inputs of the first, second, third and fourth test mode enable keys are connected to the fourth output of the analog control device -digital converter.

 The control inputs of the first, second, third and fourth multiplexers are connected to the fifth output of the analog-to-digital converter control device, the inputs of the first and second multiplexers are inputs of analog signals, the inputs of the third multiplexer are connected to the corresponding outputs of the digital-to-analog converters from the first to the n-th, inputs of the fourth multiplexer connected to the corresponding outputs of digital-to-analog converters from (n + 1) -th to the m-th, the first output of the reference voltage driver is connected to rvymi key inputs of the first to m-th, the third output of reference voltage generator is coupled to second inputs of the keys of the first through m-th, the second output of the reference voltage generator connected to a point at ground potential.

 The outputs of the keys from the first to the mth are connected to the voltage inputs of the corresponding digital-to-analog converters from the first to the m-th, the outputs of which are the outputs of the analog signals from the first to the m-th, the control inputs of the keys from the first to the m-th and the control inputs of the digital-to-analog converters from the first to the mth are connected to the corresponding outputs of the control device of the digital-to-analog converters, the first input of the control device of the analog-to-digital converter and the synchronization input of the digital-control device tax converters are connected to the output of the synchronization unit, the input of which is an AC voltage input, the interface inputs of digital-to-analog converters from the first to the mth are connected using the internal serial interface interface of the information exchange to the output of the serial interface interface of the information exchange of the microprocessor, the second input-output of the external interface controller communication highway is the input-output of an external interface system master whether the information exchange.

The invention is illustrated in the drawing, on which are indicated:
1 - analog-to-digital Converter;
2 ₁ - the first digital-to-analog converter;
2 _m - m-th digital-to-analog converter;
3 - microprocessor;
4 - controller external interface highway information exchange;
5 - control device analog-to-digital Converter;
6 - control device for digital-to-analog converters;
7 - the first amplifier;
8 - second amplifier;
9 - the third amplifier;
10 - the fourth amplifier;
11 - the first key enable test mode;
12 - second key enable test mode;
13 - third key enable test mode;
14 - fourth key enable test mode;
15 - the first multiplexer;
16 - second multiplexer;
17 - the third multiplexer;
18 - the fourth multiplexer;
19 ₁ - the first key;
19 _m - mth key;
20 - voltage reference driver;
21 - block synchronization;
22 - internal parallel interface highway information exchange;
23 - internal serial interface highway information exchange;
24 - input-output of the external interface system highway information exchange;
25 - input AC voltage;
26 ₁ - the first output of the analog signal;
26 _m - m-th output of the analog signal.

The multichannel analog input-output adapter contains m-1 digital-to-analog converters 2 ₂ , ..., 2 _m , where m is an integer greater than or equal to four, the controller 4 of the external interface data exchange highway, the first amplifier 7, the analog-to-digital converter 1 , microprocessor 3, analog-to-digital converter control device 5, digital-to-analog converter control device 6, second amplifier 8, third amplifier 9, fourth amplifier 10, first test mode enable switch 11, second power switch 12 tovogo mode, the third switch 13 starting the test mode, the fourth switch 14 enable test mode, first multiplexer 15, second multiplexer 16, the third multiplexer 17, the fourth multiplexer 18, m keys 19 _1, ..., 19 _m, 20 a reference voltage generator, synchronization unit 21, an internal parallel interface highway 22 information exchange, an internal serial interface highway 23 information exchange.

 In this case, the interface inputs / outputs (I) of the microprocessor 3, the device 5 for controlling the analog-to-digital converter, the device 6 for controlling the digital-to-analog converters, the interface output (I) of the analog-to-digital converter 1 are connected to each other and to the first input-output of the controller 4 of the external interface highway information exchange using the internal parallel interface highway 22 information exchange.

 The first output of the analog-to-digital converter control device 5 is connected to the input of the start signal (ST) signal of the analog-to-digital converter 1, the second output of the analog-to-digital converter control device 5 is connected to the input of the chip selection signal (CS) of the analog-to-digital converter 1, the third the output of the device for controlling the analog-to-digital converter 5 is connected to the input of the read signal (RD) of the analog-to-digital converter 1, the second input of the device for controlling the analog-to-digital converter 5 union of a yield of a busy signal (BS) analog-to-digital converter 1.

 The outputs of the first, second, third and fourth keys 11, 12, 13 and 14 enable the test mode through the first, second, third and fourth amplifiers 7, 8, 9 and 10 are connected respectively to the first, second, third and fourth inputs of the analog-to-digital converter 1.

 The first inputs of the first, second, third and fourth keys 11, 12, 13 and 14 of the inclusion of the test mode are connected to the outputs of the first, second, third and fourth multiplexers 15, 16, 17 and 18, the second input of the first key 11 of the test mode is connected the first output of the voltage reference driver 20, the second input of the third test mode enable switch 13 is connected to the third output of the voltage reference driver 20, the second outputs of the second and fourth test mode enable switches 12 and 14 are connected to a point with zero potential.

 The control inputs (U) of the first, second, third and fourth switches 11, 12, 13 and 14 of the test mode enable are connected to the fourth output of the analog-to-digital converter control device 5, the control inputs of the first, second, third and fourth multiplexers 15, 16, 17 and 18 are connected to the fifth output of the analog-to-digital converter control device 5.

 The inputs of the first and second multiplexers 15 and 16 are inputs of analog signals.

The inputs of the third multiplexer 17 are connected to the corresponding outputs of the digital-to-analog converters 2 ₁ , ..., 2 _n from the first to the n-th, where 1 <n <m. The inputs of the fourth multiplexer 18 are connected to the corresponding outputs of the digital-to-analog converters 2 _{n + 1} , ..., 2 _m from the (n + 1) -th to the m-th.

The first output of the voltage reference driver 20 is connected to the first inputs of the keys 19 ₁ , ..., 19 _m from the first to the mth, the third output of the voltage reference driver 20 is connected to the second inputs of the keys 19 ₁ , ..., 19 _m from the first to m-th, the second output of the driver 20 of the reference voltage is connected to a point with zero potential.

The outputs of the keys 19 ₁ , ..., 19 _m from the first to the mth are connected to the inputs (OD) of the reference voltage of the corresponding digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the mth, the outputs of which are the outputs 26 ₁ , ..., 26 _m analogue signals from first to mth.

The control inputs (Y) of the keys 19 ₁ , ..., 19 _m from the first to the mth and the control inputs (Y) of the digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the m-th are connected to the corresponding outputs of the device 6 control digital to analog converters.

 The first input of the analog-to-digital converter control device 5 and the synchronization input (C) of the digital-to-analog converter control device 6 are connected to the output of the synchronization unit 21, the input of which is an alternating voltage input 25.

The interface inputs (I) of the digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the m-th are connected via an internal serial interface interface 23 of the information exchange with the output of the serial interface interface of the information exchange of the microprocessor 3.

 The second input-output of the controller 4 of the external interface highway information exchange is the input-output 24 of the external interface system highway information exchange.

 The multichannel analog I / O adapter provides reception and output of analog signals in the form of absolute voltage, voltage ratio of two inputs (outputs) and sine-cosine signal transmitted in the form of two signals (signal proportional to the sine of the transmitted value, and a signal proportional to the cosine of the transmitted quantities).

 To receive analog signals, an analog-to-digital converter 1 is used. The analog-to-digital converter 1 is four-channel and contains temporary storage devices, a multiplexer, the analog-to-digital converter itself, and registers for storing the conversion results. The analog-to-digital converter 1 is controlled using the signals of the conversion start gate (ST), the chip select signal (CS), and the read signal (RD). To its output, the analog-to-digital converter 1 outputs a busy signal (BS), and also outputs to its interface output the results of the transformations that are available on the internal parallel interface data exchange highway 22.

 To generate control signals for the analog-to-digital converter 1, generate a control signal for the first, second, third and fourth switches 11, 12, 13 and 14 to turn on the test mode and generate the channel number for the first, second, third and fourth multiplexers 15, 16, 17 and 18, as well as for receiving a busy signal from an analog-to-digital converter 1 and a synchronization signal from a synchronization unit 21, an analog-to-digital converter control device 5 is used.

 It contains an address decoder, input and output registers. The outputs of the corresponding bits of the output register form the first, second, third, fourth and fifth outputs of the analog-to-digital converter 1. The inputs of the corresponding bits of the input register form the first and second inputs of the device 5 for controlling the analog-to-digital converter. Access to the input and output registers of the device 5 for controlling the analog-to-digital converter is carried out through the internal parallel interface line 22 of the information exchange through the interface input (I) of the device 5 for controlling the analog-to-digital converter.

 The first, second, third and fourth amplifiers 7, 8, 9 and 10 are used to convert the levels of incoming analog signals when these signals are fed to the inputs of the analog-to-digital converter 1. The first, second, third and fourth amplifiers 7, 8, 9 and 10 can be implemented based on precision operational amplifiers.

 The first, second, third and fourth switches 11, 12, 13 and 14 of the test mode enable you to apply either analog signals from the outputs of the first, second, third and fourth multiplexers 15, 16, 17 and 18 to the inputs of the analog-to-digital converter 1, or test signals, which are used as signals generated by the driver 20 of the reference voltage (positive reference voltage, negative reference voltage), as well as zero potential.

 Each of the multiplexers 15, 16, 17 and 18 allows you to connect one of its inputs (one of the inputs of the analog signals of the multichannel analog I / O adapter) to the first inputs of each of the keys 11, 12, 13 and 14 of the test mode enable.

To generate control signals for digital-to-analog converters 2 ₁ ,. . ., 2 _m from the first to the mth and key management signals 19 ₁ , ..., 19 _m from the first to the mth, and also for receiving the synchronization signal from the synchronization unit 21, there is a device for controlling digital-to-analog converters 6, which contains a decoder addresses, input and output registers. The outputs of the corresponding bits of the output register of the device 6 control digital-to-analog converters form the outputs of the device 6 control digital-to-analog converters. The input of the corresponding category of the input register of the device for controlling digital-to-analog converters is the synchronization input (C) of the device 6 for controlling digital-to-analog converters. Access to the input and output registers of the device 6 for controlling digital-to-analog converters is carried out through an internal parallel interface highway 22 of information exchange through the interface input (I) of the device 6 for controlling digital-to-analog converters.

Keys 19 ₁ ,. . . , 19 _m from the first to the mth allow you to connect to the inputs of the reference voltage (OP) of each of the digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the mth either the first output of the driver 20 of the reference voltage, or its third output ( apply either a positive reference voltage or a negative reference voltage).

The data recording in digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the mth is performed by the microprocessor 3 via the internal serial interface interface 23 of the information exchange. Setting new values at the outputs of digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the mth and, therefore, at the outputs 26 ₁ , ..., 26 _{m of} analog signals from the first to the mth is performed upon receipt of a signal at control input (V) of digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the mth.

To ensure control over output using digital-to-analog converters 2 ₁ ,. .., 2 _m from the first to the m-th signals and to ensure the health monitoring of analog communication lines connecting the outputs of the digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the m-th with consumers of analog signals (in particular, to ensure control short circuit conditions in analog communication lines), the inputs of the third multiplexer 17 are connected to the corresponding outputs of the digital-to-analog converters 2 ₁ , ..., 2 _n from the first to the n-th, the inputs of the fourth multiplexer 18 are connected to the corresponding outputs of the digital-to-analog converters 2 _{n + 1} , ..., 2 _m from the (n + 1) -th to the m-th.

 Block 21 synchronization is used to generate a reference frequency signal from the supply voltage of the on-board network (400 Hz), used to power sensors using sine-cosine signals.

The reference voltage driver 20 is used to generate positive (+ U _OD ) and negative (-U _OP ) reference voltages defining a range of analog output signals generated by digital-to-analog converters 2 ₁ ,. . ., 2 _m from the first to the mth, as well as those used during operation of the multi-channel analog input-output adapter in test mode for calibrating the analog-to-digital converter 1.

 The microprocessor 3 is used to control and synchronize the implementation of digital-to-analog and analog-to-digital conversion, processing data obtained as a result of analog-to-digital conversion, and processing data for digital-to-analog conversion.

 Input-output 24 of the external interface system bus of the information exchange is used to connect a multi-channel adapter of analog input-output to the interface system bus of the information exchange of a computer system using this multi-channel adapter of analog input-output. The data exchange with the devices of the computing system is carried out using the controller 4 of the external interface system highway information exchange.

 Multichannel analog I / O adapter works as follows.

After power is turned on and microprocessor 3 performs self-testing procedures, microprocessor 3 starts receiving data from analog-to-digital converter 1 and outputting data to digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the mth.

 Reception of analog signals is as follows. The device 5 for controlling the analog-to-digital converter under the control of the microprocessor 3 provides the channel number for the first, second, third and fourth multiplexers 15, 16, 17 and 18 to its fifth output. The signals at the outputs of the device for controlling the analog-to-digital converter 5 are set by recording by the microprocessor 3 corresponding values in the corresponding bits of the output register of the device 5 control analog-to-digital Converter. Next, the device 5 controls the analog-to-digital Converter generates at its first output a strobe signal of the start of conversion (ST). The values of the analog signals supplied to the first, second, third and fourth inputs of the analog-to-digital converter 1 are stored in temporary storage devices of the analog-to-digital converter 1. Next, the analog-to-digital converter 1 performs the conversion for all four channels.

 The conversion results are recorded in the registers of the analog-to-digital converter 1. The corresponding state of the busy signal (BS) indicates the end of the conversion. After that, the conversion results are read from the registers of the analog-to-digital converter 1, for which the analog-to-digital converter control device 5 provides the corresponding signals to its second and third outputs, that is, the chip select signal (CS) and read signals (RD). The results of the conversions sequentially for all four channels on the internal parallel highway 22 information exchange are received in the microprocessor 3.

и функцию арктангенс

Так как синусно-косинусные сигналы являются сигналами переменного тока опорной частоты 400 Гц, то микропроцессор 3 синхронизирует начало аналого-цифрового преобразования (выдачу сигнала строба начала преобразования) с опорной частотой, поступающей на первый вход устройства 5 управления аналого-цифровым преобразователем.Data obtained as a result of analog-to-digital conversion is processed by microprocessor 3 as follows:
- for the input analog channel of absolute values, the conversion results without additional processing are placed in the memory cells of the corresponding channel of the microprocessor 3;
- for the input analog channel of the relative voltage value, the microprocessor 3 additionally calculates a value equal to the ratio of the result of the conversion of the voltage signal to the reference voltage;
- for the input analog sine-cosine channel, the microprocessor 3 calculates the ratio of the voltage conversion results in the sine channel to the voltage in the cosine channel

and arctangent function

Since the sine-cosine signals are AC signals of a reference frequency of 400 Hz, the microprocessor 3 synchronizes the beginning of the analog-to-digital conversion (output of the strobe signal of the beginning of the conversion) with the reference frequency supplied to the first input of the analog-to-digital converter control device 5.

 The microprocessor 3 when the multichannel analog I / O adapter is in test mode (when the first, second, third and fourth keys 11, 12, 13 and 14 of the inclusion of the test mode enable the positive and negative reference voltages from the driver 20 to the inputs of the analog-to-digital converter reference voltage, as well as zero potential) stores digital values corresponding to positive and negative reference voltages and zero potential. These values are used by microprocessor 3 when the multichannel analog I / O adapter is in operation (when the first, second, third and fourth keys 11, 12, 13 and 14 of the test mode enable provide analog signals from the outputs of the first to the inputs of the analog-to-digital converter 1 , second, third and fourth multiplexers 15, 16, 17 and 18) to adjust the values received from the analog-to-digital converter 1.

 The calculated values of the microprocessor 3 through the controller 4 of the external interface highway of information exchange outputs to the input-output 24 of the external interface highway of information exchange (to a computer system using this multichannel analog I / O adapter).

 The issuance of analog signals is as follows. The microprocessor 3 receives input for digital-to-analog converters and data on the operating modes of the multi-channel analog input-output adapter from the input-output 24 of the external interface bus of the information exchange (from a computer system using this multi-channel analog I / O adapter).

The electronic computer 3 processes this data (multiplication by scale factors, calculating the signal parameters when issuing signals in the form of the ratio of the voltages of two signals and issuing sine-cosine signals). The prepared data on the internal serial interface highway 23 information exchange are recorded in digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the mth. Then, when writing the corresponding data to the output register of the device for controlling digital-to-analog converters, to the control inputs (V) of the digital-to-analog converters 2 ₁ , ..., 2 _m , the signals from the first to the mth are transmitted, upon receipt of which the conversion is performed, and at the outputs of the digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the mth and, therefore, at the outputs 26 ₁ , ..., 26 _{m of the} analog signals from the first to the mth, new values of the analog signals are set.

When issuing sine-cosine signals using the keys 19 ₁ , ..., 19 _m from the first to the m-th positive and negative reference voltages (+ U _OP and -U _OP ) to the inputs of the reference voltage (OP) of digital-to-analog converters 2 ₁ , . . . , 2 _m from the first to the mth are fed synchronously with the frequency of the onboard network. In this case, at the outputs of the digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the mth, signals are generated in the form of a meander, the amplitude of which is proportional to the values recorded in the digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the m-th values .

The signals from the outputs of the digital-to-analog converters 2 ₁ , ..., 2 _n from the first to the n-th are fed to the corresponding inputs of the third multiplexer 17. The signals from the outputs of the digital-to-analog converters 2 _{n + 1} , ..., 2 _m s (n + 1) th to mth go to the corresponding inputs of the fourth multiplexer 18. An analog-to-digital converter 1 under the control of microprocessor 3 converts these signals into digital form. The microprocessor 3 compares the results of the conversions with the data that were transferred to the digital-to-analog converters 2 ₁ , ..., 2 _m from the first to the mth, and in case of a mismatch, the microprocessor 3 outputs to the input-output 24 through the controller 4 of the external interface data bus external interface trunk information exchange fault signals.

 Thus, the present invention provides the ability to receive analog signals of absolute voltage, relative voltage and sine-cosine signals, converting them into digital form with increased accuracy, as well as converting data in digital form to analog signals of absolute voltage, relative voltage and sine-cosine signals and the issuance of these analog signals while increasing fault tolerance and with minimal use of the resources of a computer system using this ogokanalny analog input-output adapter.

 The presented drawing and description of the invention allow, using the existing element base, to manufacture it industrially and use it in information collection and processing systems, as well as in control systems, which characterizes the invention as industrially applicable.

Sources of information
1. A.S. USSR 1532937, class G 06 F 13/00, 1990.

 2. A.S. USSR 1564606, class G 06 F 3/00, 1990.

Claims (1)

 A multichannel analog input-output adapter containing a digital-to-analog converter, an external interface interface controller, a first amplifier, further comprises an analog-to-digital converter, m-1 digital-to-analog converters, where m is an integer greater than or equal to four, a microprocessor, and an analog control device -digital converter, digital-to-analog converter control device, second amplifier, third amplifier, fourth amplifier, first switching key new mode, the second test mode enable switch, the third test mode enable switch, the fourth test mode enable switch, the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, m keys, the voltage driver, synchronization unit, an internal parallel interface for information exchange, an internal serial interface line of information exchange, while the interface inputs and outputs of the microprocessor, the control device analog-to-digital the converter, the control devices of the digital-to-analog converters, the interface output of the analog-to-digital converter are connected to each other and to the first input-output of the controller of the external interface highway of information exchange using the internal parallel interface highway of the information exchange, the first output of the control device of the analog-to-digital converter is connected to the input of the strobe signal the beginning of the conversion of the analog-to-digital converter, the second output of the analog-qi control device the front-end converter is connected to the input of the analog-to-digital converter chip selection signal, the third output of the analog-to-digital converter control device is connected to the input of the analog-to-digital converter read signal, the second input of the analog-to-digital converter control device is connected to the output of the busy signal of the analog-to-digital converter, outputs the first, second, third and fourth keys to enable the test mode through the first, second, third and fourth amplifiers are connected respectively However, with the first, second, third, and fourth inputs of the analog-to-digital converter, the first inputs of the first, second, third, and fourth test mode enable keys are connected to the outputs of the first, second, third, and fourth multiplexers, the second input of the first test mode enable key is connected to the first output of the voltage reference driver, the second input of the third test mode enable switch is connected to the third output of the voltage reference driver, the second inputs of the second and fourth switches The test mode is connected to a point with zero potential, the control inputs of the first, second, third and fourth switches of the test mode are connected to the fourth output of the analog-to-digital converter control device, the control inputs of the first, second, third and fourth multiplexers are connected to the fifth output of the control device analog-to-digital Converter, the inputs of the first and second multiplexers are inputs of analog signals, the inputs of the third multiplexer are connected to the corresponding the outputs of the digital-to-analog converters from the first to the n-th, the inputs of the fourth multiplexer are connected to the corresponding outputs of the digital-to-analog converters from (n + 1) to the m-th, the first output of the voltage generator is connected to the first inputs of the keys from the first to the m-th, the third output of the voltage generator is connected to the second inputs of the keys from the first to the mth, the second output of the voltage generator is connected to a point with zero potential, the outputs of the keys from the first to the mth are connected to the inputs of the voltage the corresponding first to mth digital-to-analog converters, the outputs of which are the first to mth analog signals outputs, the first to mth control key inputs and the first to mth digital to analog converter inputs are connected to the corresponding outputs of the control device digital-to-analog converters, the first input of the analog-to-digital converter control device and the synchronization input of the digital-to-analog converter control device are connected to the output of the synchronization unit of the input, whose input is an AC voltage input, the interface inputs of the digital-to-analog converters from the first to the mth are connected using the internal serial interface interface of the information exchange to the output of the serial interface interface of the microprocessor information exchange, the second input-output of the controller of the external interface of the information exchange is the input- the output of an external interface system bus information exchange.