RU2106676C1 - Device for programmed logical control of electric drives, electronic gates and guarding equipment - Google Patents

Abstract

FIELD: automation and computer engineering. SUBSTANCE: device has input and output units, memory unit, synchronization unit, commutation-computing unit, program unit and pulse generator. In addition device has accelerating unit which has OR gate and NOT gate, two-input and four-input AND gates, test flip-flop, controlled memory registers, first and second electronic gates with corresponding connections. This results in possibility to take into account only variables of boolean function that are active in given time. EFFECT: increased speed of boolean function calculation, decreased number of connection lines between program unit and accelerating unit. 10 dwg

Description

 The invention relates to programmable and control computing devices and can be used independently in control systems for various production lines, computer complexes as devices for sending single-bit information and computing Boolean functions, freeing multi-bit microprocessors from these functions that perform these functions inefficiently.

 A device is known that contains an input unit connected via a common information bus to the output of the RAM block and to the input of the computational block, the output of which is connected via a memory trigger to the output block, the RAM block, and a controlled inverter, the output of which is connected to the control block, to the inputs of which additional command buses are received from the program unit, transmitting the number of an extraordinary beat (SU, copyright certificate N 1226508, class G 08 C 19/16, 1984).

 The disadvantage of this device is that for the transmission of an extra cycle, additional command buses are used, coming from the software unit to the control unit, which increases the number of communication wires, which means it reduces the reliability of the device and makes it cumbersome.

 The closest in technical essence, reliable and efficient organization of the process of controlling the operation of the entire device is a device containing input and output blocks, RAM and synchronization blocks, a switching and computing unit, a pulse generator and a program block, the pulse generator being connected to a synchronization block, which its outputs are connected to the inputs of the switching and computing unit, the RAM block, the output and program blocks, the outputs of the latter are connected by command and solid buses with all blocks except the synchronization block, and the output of the input block is connected to the input of the switching and computing unit, the outputs of which are connected respectively to the RAM block and the output block (RU, patent N 1801223, class G 05 B 19/08, 1993 )

 The disadvantages of this device include the obligation to calculate the entire Boolean function, for example, conjunction, even when it is determined that the first term in the conjunction is equal to "0" and, therefore, the whole conjunction is equal to "0". The entire clause is also calculated when it is already established that, for example, the first clause variable is equal to "1", which means that the whole clause is equal to "1".

 The technical result of the invention is aimed at accelerating the process of calculating Boolean functions when using the command and address buses already available in the prototype as information carriers about an extra-measure number. This result is achieved by the fact that in the known device for remote control of electric drive mechanisms and signaling, comprising input and output blocks, a random access memory block, a synchronization block, a switching and computing unit, a program unit and a pulse generator, the switching and computing unit being connected by inputs to the outputs of the input block, the block of RAM and the synchronization block, two control outputs connected to the inputs of the blocks of RAM and output, and information the output is connected to the corresponding inputs of the last blocks, the remaining two inputs of which and the input of the program block are connected to the outputs of the synchronization block, the input of which is connected to the output of the pulse generator, an acceleration block is also introduced, consisting of the elements OR and NOT, two = and four-input elements AND, control trigger, memory cells, first and second electronic keys, while the inputs of the OR element are connected to the control outputs of the switching and computing unit, the output of the OR element is connected to the inputs of the element NOT and a two-input element And, the second input of which is connected to the second output of the synchronization block, and the output is connected to the input of the zero setting of the control trigger, the setting in "1" of which is connected to the additional bus of the program unit, and the output of the control trigger and the input of the element are NOT connected to two inputs of the four-input element AND, the remaining inputs of which are connected to the first output of the synchronization unit and to the output of the EXCLUSIVE OR element of the switching and computing unit, and the output - with the control input of the first electro key, the outputs of which are connected to the installation inputs of the pulse counter of the program unit, and the inputs are connected to the outputs of the memory cells, the inputs of which are connected together with the inputs of the second electronic key to the command, address and additional buses of the program block, and the outputs of the second electronic key are connected to command inputs switching and computing unit.

 The proposed device is illustrated by the circuit depicted in figure 1.

 The device consists of an input unit 1 connected to the input of the switching and computing unit 2, connected to the main memory unit 3, with the output unit 4 and, through the synchronization unit 5, with a pulse generator 6, a program unit 7 and an acceleration unit 8 containing the OR element 9 connected through the element NOT 10 and the two-input element And 11 with the control trigger 12 and the four-input element And 13, the output of which is connected to the control input of the first electronic key 14, connected by the remaining inputs to the outputs of the memory cells 15, controlling second input of which is connected to the control input of the second electronic key 16.

The operation of the electronic key 14 of block 8 is that if there is a logical "1" at the output of AND 14, key 14 passes logic signals from the outputs of memory cells 15 to the inputs A ₁ ... A _{j of} block 7 of the program, and if there is a logical " 0 "- does not pass and outputs A ₁ ... A _j have logical" 0 ". The key 16 is that if there is a logical "0" on the C bus of block 7, the values of the command signals C1 ... C5 are sent to the inputs of block 2. When C _{j + 1} = 1, the values C ' ₁ ... C' ₅ always equal to "0". The arrows directed to the elements and blocks mark the inputs of all the elements of the blocks.

C ' ₁ . ..C ' ₅ - command signals equal to signals C1 ... C5 at C = 0, controlling the operation of block 2;
C ₆ ... C _j - address signals that determine the number of memory cells in blocks 3 and 4, or the number of the input in block 1. They also determine the number of an extra cycle at C = 1.

X ₁ . .. X _n - values of the input signals coming from the control object;
a ₁ ... a _j - signals that set the counting triggers of block 7 to the state corresponding to the extraordinary number of the next measure;
b ₁ - value of the output of the element EXCLUSIVE OR in block 2;
b ₂ and b ₃ - signals from block 2 to block 8.

The input unit of known construction is presented in figure 2, It consists of matching elements 20, through which the input signals X in the necessary form are supplied to the reading elements 21 of the type of AND elements, the outputs of which are connected to the OR element 22, the decoder 23 controls the elements 21 according to the signals C ₆ ... C _j .

The program unit 7 (Fig. 4) of known construction consists of a pulse counter 28, the counting input of which receives pulses from the synchronization block 5, and the signals a ₁ ... a _j from block 8, which at C _{j + 1} = 1 put counter 28 in an extraordinary state. When C _{j + 1} = 0, the counter 28 operates in the usual mode of the decoder 29, which distributes the pulses to the elements 30 of the permanent memory (for example, the ROM series 155PE3), onto which the program of operation of the entire device is recorded. Before starting work, the pulse counter is set to zero. A detailed diagram of the counter 28 is shown in FIG. 10, where the index 50 denotes the element NOT, and the index 51-counted triggers with installation inputs J and K.

The output unit 4 (Fig. 3) consists of AND elements 24, memory cells 25, where information from block 2 and the corresponding amplifiers 26, which transmit logical signals from memory cells to electric drives, is recorded by address signals C ₆ ... C _j and commands from block 2, coming to the decoder 27.

The RAM block 3, which is presented in FIG. 5, contains the elements And 31 access to the memory cells, as the latter, you can use standard RAM, or, as in our example, individual memory elements 32, read elements 33 (elements And), elements OR 34, the first and second decoders 35, through the corresponding element enters or reads information from the corresponding memory cell according to the instructions from block 2 and the address code C ₆ ... C _j .

Block 2 of a known structure (Fig.6) consists of a three-input decoder 36, its inputs connected to the outputs C ₁ , C ₂ , C _{3 of} block 8, and the first / top / and second outputs connected to the first inputs of the elements And 37 and 38, the second the inputs of the latter are connected to the input block and RAM blocks 1 and 3, and the outputs to the inputs of the OR element 39, the output of which is connected to the first input of the EXCLUSIVE OR 40 element, the second input of the latter is connected to the output C _{4 of} block 8, and the output is connected through the element And 41 with the control input of the memory cell 42, information input cat swarm connected to the output C ₅ acceleration unit 8, and an output - a unit data inputs 3 and unit 4. The third and fourth outputs of decoder 36 are connected to the control inputs of the blocks 3, 4 and 8.

 Block 5 synchronization of known design (Fig. 7) contains the first counting trigger 43 connected by a direct output to the element And 44, and an inverse output to the first inputs of the elements And 45 and 46, the second input of the latter is connected to the output of the element And 47, the inputs of which connected with the direct output of the second counting trigger 48 and the output of the inverter 49, the input of which together with the input of the trigger 43 are the inputs of block 5 and are connected to the pulse generator 6. The output of element And 44 of block 5 is connected to the counting input of the counter 28 of block 7 and the input of element And 13 of block 8, the output of element And 47 of block 5 is connected to the input of element And 41 of block 2 and the input of element And 11 of block 8, and the output of the element And 45 of block 5 is connected to the inputs of decoders 35 and 27 of blocks 3 and 4, respectively. The operation of block 5 is illustrated by diagrams in FIG. 8 and FIG. nine.

We describe the operation of the proposed device using the example of computing a logical function X ₁ • X ₂ • X ₃ (X ₄ + X ₅ • X ₆ + X ₇ ) = Φ containing a functionally complete set of logical functions. At the first clock cycle, with the command C _{j + 1} = 1, the clock number is written in the memory cells 15 of block 8, which writes the result of the calculation of the function Ф into block 3 and at the same time the trigger 12 of block 8 is transferred to a single state. On the second step with C ' ₄ = 1; C ' ₅ = 1 and at zero values C' ₁ , C ' ₂ and C' ₃ in the cell 42 of the memory block 2 is written "1". At the third step, the variable X ₁ under the action of the commands C ' ₁ , C' ₂ and C ' ₃ , as well as the address signals C ₆ ... C _j, comes from block 1 through the elements 37, 39, 40 and 41 to the control input of cell 42 memory. Given that at the third clock cycle C ' ₄ = 1 and C' ₅ = 0, it can be argued that if X ₁ = 1, then “1” will be stored in the memory cell 42 and the process of calculating the function Ф will continue, and if X ₁ = 0, it is obvious that the function Φ is equal to "0" and there is no sense in calculating it further. Therefore, under the action of the command b ₁ coming from the output of element 40 of block 2, a single signal at the output of trigger 12 of block 8 and the next counting pulse at the output of block 5, at the output of element 13 of block 8, "1" appears and the value of the measure number previously recorded in the cells 15 of block 8, through a key 14 it enters the installation inputs of the counter 28 of block 7 and signals C ₁ ... C _j are set at its outputs, which ensure that the result of computing the function Ф is written to the desired memory cell of block 3. Thus, to calculate the function Ф, it took three measures together about thirteen, as would be required in the prototype.

Suppose that the result of calculating the conjunction X ₁ , X ₂ , X ₃ is "1", then this result is written in block 3 at the address C ₆ ... C _j and at the same time with C ' ₄ = 1 and C' ₅ = 0 is logical "0" is written to the memory cell 42 of block 2, and the trigger 12 of block 8 returns to the zero state. At the seventh step, under the action of the command C _{j + 1} = 1, a measure number is written in the memory cell 15 of block 8, which is determined by the values of C ₁ ... C _j coming from block 7 and determining the operation of the entire device after calculating the entire function Ф, and at the same time trigger 13 of block 2 will take a single value. On the eighth cycle, with C _{j + 1} = 0 and C ' ₅ = 1, the first output of the decoder 36 of block 2 and the variable X ₄ , the address of which in block 1 is determined by the values of C, are activated by the commands C' ₁ , C ' ₂ and C' _{3 6} ... C _j , through the elements 37 and 39 of block 2, it enters the input of element 40, the second input of which receives the command C ' ₄ = 1 and, if the variable X ₄ = 0, there is no point in calculating the function Ф further, because . it is equal to "1" and at the output of element 40 of block 2, a single signal will appear, which will provide, together with the signal at the output of block 5, the presence of "1", at the output of element 13, and to the installation inputs of the clock counter of block 7 from the output of elements 14 of block 8 the measure number recorded earlier in cells 15 of block 8, which determines the operation of the entire device after calculating the function F. Thus, the function Ф was calculated in 8 cycles instead of thirteen. If the value of the function Ф has not yet been determined (X ₄ = 1), then the calculation of the function Ф continues.

From the foregoing, two conclusions can be drawn:
- the use of acceleration unit 8 of a new design and with new connections allows you to speed up the process of computing Boolean functions by analyzing only the active input signals X, i.e. on which the meaning of conjunction or disjunction in Boolean functions depends;
- the use of block 8 allows the use of command and address buses C ₁ . . . C _j as buses transmitting the numbers of extraordinary clock cycles, which previously, as shown above, were recorded in the memory cells 15 of the block 8 from the block 7 of the memory.

In this case, the commands C ' ₁ ... C' _{5 are} blocked by the signal C _{j + 1} = 1 and no operations are performed in block 2, which, unlike the analogue, can significantly reduce the number of communication lines in the device.

 The technical and economic effect of the application of the proposed device consists in the possibility to increase the speed of processing discrete information, which increases the accuracy of control by reducing the time between the change of the sensor signals (X) at the control object and the issuance of control signals to the electric drive of the control object. The number of communication lines in the device is also reduced, which means that its reliability and noise immunity are increased.

Claims (1)

 A device for software logical control of electric drives, electronic keys and signaling, containing input and output blocks, a random access memory block, a synchronization block, a switching and computing unit, a program unit and a pulse generator, a switching and computing unit is connected by corresponding inputs to the outputs of the input unit, unit RAM and synchronization block, and the corresponding outputs - with the corresponding inputs of the RAM block and the output block, other inputs of the last blocks are connected to the program unit and the synchronization unit associated with the pulse generator and the program unit, characterized in that an acceleration unit containing OR or NOT elements, two-input and four-input AND elements, a control trigger, controlled memory cells, the first and second are introduced into it electronic keys, moreover, the inputs of the OR element are connected to the operating block of the RAM and the output block by the outputs of the switching and computing unit, the output of the OR element is connected to the inputs of the elements NOT and two of one element AND, the second input of the latter is connected to the corresponding input of the switching and computing unit and connected to the corresponding output of the synchronization unit, and the output of the two-input element And is connected to the input of the control trigger in “0”, the input of which is connected to the “1” input to the additional bus program block, and the output of the control trigger is connected to the first input of the four-input element And, the second input of which is connected to the output of the element NOT, the third and fourth inputs of the four-input element And are connected to one to them from the outputs of the synchronization unit and with the single output of the switching and computing unit, the output of the four-input element And is connected to the control input of the first electronic key, the outputs of the latter are connected to the installation inputs of the software unit, and the other inputs of the first electronic key are connected to the outputs of the controlled memory cells of the acceleration unit, the inputs of the latter together with the inputs of the second electronic key are connected to the outputs of the software unit, the outputs of the second electronic key are connected to the control inputs of the switching continuously computing unit.

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