RU2097921C1 - Noise reduction device - Google Patents

Abstract

FIELD: radio engineering, in particular, receivers for wide-band signals operating in heavy background noise in spectrum of signal. SUBSTANCE: device has analog-to-digital converter 1, subtraction unit 2, inverter 3, first and second modulo two adders 4, 8, AND gate 5, NOR-extension inverter 6, Schmidt flip-flop 7, delay gate 9, pulse generator 10. Analog-to-digital converter performs precise sampling while units 3, 4, 5, 6 provide rough sampling of input process (additive mix of signal and heavy noise). Noise is reduced by means of subtraction of rough sample of input process (noise) from precise one (additive mix of signal and noise) in unit 2. Increased efficiency of reduction is achieved by means of selection of clock frequency and bit-length of analog-to-digital converter. These data determine precise and rough sampling of input process. EFFECT: increased efficiency of noise reduction. 2 dwg

Description

 The invention relates to the field of radio engineering, and in particular to the field of radio communication technology and can be used as part of radio receivers designed to receive broadband signals against the background of powerful interference concentrated in the signal spectrum.

 A device for suppressing interference is known (see, for example, Aut. St. USSR N 1338079, application N 4603676 from 09.11.88. Publ. 11. 1990). The device comprises a non-linear signal converter, a decoder, a counter, a RAM block, a control pulse generation block, first and second buffer registers, a block for estimating the second initial distribution moment of a random process, a quadrator, a divider, an estimator for the fourth initial distribution moment of a random process, analog-to-digital converter and generator.

 The operation of this device is based on the determination of the kurtosis excess parameter, according to which the characteristic of the nonlinear signal converter is adapted so that it is consistent with the noise distribution density with the calculated kurtosis.

 The disadvantage of this interference suppression device is the low efficiency of the suppression of powerful concentrated in the spectrum of the signal interference, especially if their structure is close to the structure of the received signal. In this case, in a nonlinear converter, suppression of a useful signal is possible along with interference.

 It is also known a device for compensating for interference (see, for example, ed. St. USSR N 1571774, application N 4315421 from 09.10.87. Publ. 09.1990), containing the first and second filters, the first and second delay elements, a subtractor, an interference detector detector, threshold element, pulse generator, adjustable amplifier, block for determining the amplitude of interference, peak detector with reset, memory element.

 The device is linearly compensated for impulse noise voltages, and the result is output to the output of the device. The disadvantage of this device for noise compensation is the ability to compensate only for impulse noise, in addition, the frequency band of the received signal is limited by the passband of the input bandpass filter, and the input signal level is not taken into account in the process of noise compensation, which can lead to false useful signal compensation.

 The closest analogue to the claimed device (prototype) in its technical essence is the well-known device for the compensation of impulse noise (see, for example, ed. St. USSR N 1619413, application N 4449356 from 06.23.88. Publ. 04.1991). The prototype device contains the first and second bandpass filters, a pulse generator, a subtractor, a delay element, an analog-discrete converter, a signal recovery unit.

 In this case, the input signal is simultaneously fed to the inputs of the first bandpass filter, the second bandpass filter and the pulse generator, the output of which is connected to the first input of an analog-discrete converter, the output of the first bandpass filter is connected to the first input of the subtracter, the output of the second bandpass filter is connected to the second input of the subtractor, the output of which is connected to the input of the delay element, the output of which is connected to the second input of the analog-discrete converter, the output of which is connected to the input of the recovery unit signal.

 The suppression of impulse noise is achieved by the fact that in the analog-discrete converter, samples are taken at times when the signal at the output of the subtracter is zero. The useful signal is restored in the signal recovery unit.

 The disadvantage of this device for noise compensation is the inability to compensate for interference concentrated only in the signal spectrum and limited by the passband of the input bandpass filter, in addition, the presence of an extraneous signal in the passband of the second filter will lead to false compensation of the useful signal.

 The aim of the present invention is to develop a noise compensation device that has high suppression of powerful concentrated in the spectrum of a wideband interference signal and provides the output ratio of the interference power and the useful broadband signal, close to unity with guaranteed conservation of the useful signal power.

 This goal is achieved by the fact that in the known device for the compensation of impulse noise, containing an analog-to-digital converter (ADC), a subtractor, a delay element, a pulse generator, the output of which is connected to the first input of the ADC, the following elements are additionally introduced: Schmitt trigger, the first and second circuits modulo two additions, an inverter with an extension of the output "OR NOT", an inverter and a logic circuit "AND". The ADC outputs are connected to the first corresponding inputs of the subtractor and some of them are additionally connected to the inputs of the inverter, the outputs of which are connected to the corresponding second inputs of the subtractor. One of the ADC outputs is also connected to the first input of the AND circuit. The output of the pulse generator is connected to the second input of the AND circuit, and to the first input of the delay element. The output of the logic circuit "AND" is connected to the input of the inverter with an extension of the output "OR-NOT", the output of which is connected to the second corresponding inputs of the subtractor. Additionally, the output of the logic circuit "And" is connected to the first input of the second adder modulo two. The Schmitt trigger output is connected to the second input of the latter, the input of which is input. The output of the second adder modulo two is connected to the second input of the delay element, the output of which is connected to the first input of the first adder modulo two. The second input of the last one of the outputs of the subtractor is connected. The output of the first adder modulo two and the corresponding outputs of the subtractor are connected to the output of the device.

 The principle of creating the proposed device is based on the use of an evaluation-non-parametric method of compensating powerful interference. The named method is based on a priori knowledge of only the limiting amplitude values of signal realizations, which is quite realistic for channels with constant parameters. The algorithm for quasicompensation of powerful interference concentrated in the spectrum of the signal is based on rough tracking of the interference level by instantaneous samples of the analog-to-digital converter and subtracting from the value of the exact reference level of the additive mixture of the signal and the interference, the value of a rough estimate of the interference level. The operation of the device can be compared with the operation of a limiter with a tracking threshold (“window”), when the threshold with a given error monitors the average level of the envelope of the noise.

 This construction of the device, in contrast to the prototype, where the compensation of impulse noise is achieved by comparing the values of the input process at the outputs of the bandpass filter of the useful signal and the filter, tuned in frequency, and taking samples in an analog-discrete converter at times when the result of the comparison is zero, has the following advantage. The possibility of compensated interference types increases, false compensation of the useful signal due to the absence of a second reception channel is eliminated, and the power of the useful signal is guaranteed to be kept, reducing the ratio of the interference power and the useful signal at its input, significantly exceeding unity, to a value close to unity (above) at the output with the accuracy provided by the parameters of the analog-to-digital converter.

 In FIG. 1 shows a general functional diagram of a noise compensation device; in FIG. 2 timing diagrams of the operation of the blocks of the interference compensation device.

 The interference compensation device shown in Fig. 1 contains an analog-to-digital converter 1, a subtractor 2, an inverter 3, a first adder modulo two 4, a logic circuit "AND" 5, an inverter with an extension of the output "OR-NOT" 6, a trigger Schmitt 7, the second adder modulo two 8, delay element 9, pulse generator 10. The outputs 1.1 1.N of the analog-to-digital converter 1 are connected to the corresponding inputs A.1 - A.N of the subtractor 2, in addition, the outputs 1. K + 1 1.N ADC 1 is additionally connected to the corresponding inputs 3.K + 1 3.N of inverter 3, outputs 3.K + 1 - 3.N of which key to input B. K + 1 V.N subtractor 2, and the output of ADC 1.K 1 is further coupled to an input of the logic circuit 5.1 "and" 5, to the input 5.2 is connected to the output 10.2 of the pulse generator; the output of the logic circuit “AND” 5 is connected to the input of the inverter with an extension by the output to “OR-NOT” 6, the outputs 6.1 6. To which are connected to the inputs of B. 1 of the subtractor 2; at the same time, the output of the logic circuit “AND” 5 is connected to the input 8.1 of the second adder modulo two 8, to the input 8.2 of which the output of the Schmitt trigger 7 is connected, the input of which is supplied with an input signal; the output of the second adder modulo two 8 is connected to the input 9.1 of the delay element 9, to the input 9.2 of which the output 10.3 of the pulse generator is connected; the output of the delay element is connected to the input 4.1 of the first adder modulo two 4, the input 4.2 of which is connected to the output S. To the subtractor 2; the output 10.1 of the pulse generator is connected to the input 1.2 of the ADC 1, the input 1.1 of which is fed an input signal; the output of the first adder modulo two 4 and the outputs S.1 S. K-1 subtractor 2 are the outputs of the device.

The noise compensation device operates as follows. An additive mixture of signal and interference arrives at the input of the device, which, taking into account the power of white Gaussian noise in the signal band, has the form:
X (t) = S (t) + n _n (t) + n _o (t);
From the outputs 1.1 1.N of the ADC, the values of the numerical codes corresponding to the level of the time-varying analog value of the input process X (t) are fed to the inputs of the A.1 A.N subtractor. Additionally, from the outputs 1.K + 1 1.N, the ADC signal is supplied to the inputs 3.K + 1 3.N of the inverter and from its outputs 3.K + 1 3.N to the inputs B. K + 1 B.N of the subtractor. In addition, the signal from the output 1.K ADC is fed to the input 5.1 of the logic circuit "And", the input of 5.2 of which receives the signal from the output of 10.2 of the pulse generator. The result of logical multiplication from the output of the logic circuit "And" is simultaneously transmitted to the input 8.1 of the second adder modulo two and to the input of the inverter with an extension of the output "OR-NOT", from the outputs 6.1 6. To which the signal is fed to the inputs B.1 B. K subtractor. The input signal simultaneously with the input to the input 1.1 of the ADC is fed to the input of the Schmitt trigger, which has a threshold that is determined by the level of the input signal against a white Gaussian noise, i.e. if the input signal is X (t) <S (t) + n _o (t), then the output is logical "1" and if X (t)> S (t) + n _o (t), the logic is "0". The signal from the Schmitt trigger output is fed to the input 8.2 of the second adder modulo two. At the output of which a logical signal “1” or “0” appears, depending on the value of the signals at its inputs 8.1 and 8.2 and is equivalent to the truth table of the adder modulo two. Moreover, if X (t)> S (t) + n _o (t), then at the output of the second adder modulo two the signal will correspond to the signal at output 1. To the ADC, if X (t) <S (t) + n _o (t), then this signal will be inverted relative to the signal at the output 1.K of the ADC. The signal from the output of the second adder modulo two is fed to the input 9.1 of the delay element, where its delay for a time t _{s is} provided. From the output of the delay element, the signal enters the input 4.1 of the first adder modulo two. The subtractor performs the operation of algebraic subtraction from the values of the signal at its inputs A.1 A.N, the values of the signal at its inputs B.1 B.N. In this case, the signal values at the inputs A.1 A. N of the subtractor are the values of the exact reference of the input process X (t) with a quantization step ε _t . The values of the signal at the inputs of B.1 B.N, due to transformations in the logic circuit “And” and the inverter with the expansion by the output “OR-NOT”, are the values of the rough reading of the input process X (t) with a quantization step of ε _g . The subtractor is a conventional adder, the subtraction mode in which is provided by the inverter and inverter with an extension of the output "OR-NOT" connected to its inputs B.1 - B.N. From the outputs of S. 1 S. K-1 of the subtractor, the result of the subtraction is fed to the output of the device. In addition, the signal from the output S. To the subtractor is fed to the input 4.2 of the first adder modulo two, the output of which appears a logical signal "1" or "0" depending on the values of the signals at its inputs 4.1, 4.2 and is equivalent to the truth table of the adder by module two. The joint work of the first and second adders modulo two, the delay element and the logic circuit “And” provides the separation of the difference sign of the exact and rough samples of the input process X (t) and the complement of the signal code at the output of the device corresponding to this difference sign. Moreover, we believe that if the output is 1.K ADC, the logic signal is "0", then the difference sign is positive and the code is not supplemented at the output of the device. If at the output 1.K of the ADC the logic is “1”, then the rough count of the input process is taken in excess and at the output of the first adder modulo two there is a corresponding addition of the signal code at the output of the device. Outputs 1 To the noise compensation device are connected to the corresponding inputs of the digital demodulator. From the outputs 10.1 and 10.3 of the pulse generator, the clock signals are fed to the input 1.2 of the ADC and to the input 9.2 of the delay element, respectively. The temporal relations of the signals from the outputs of the pulse generator and other elements of the device are shown in FIG. 2 where
_a sampling time t, the time during which the ADC comparators are comparing the analog input signal with a set of standard mode reference voltages;
t _x storage time, during which the value of the analog input signal is stored in the comparators;
t _n conversion time, which consists of the transition time of the comparators to the storage mode and the processing time of the information in the ADC encoder;
t _s the summation time in a multi-bit adder, defined as t _s = (m-1) t _per + t _p , here: m is the number of four bit sections with an internal accelerated transfer circuit;
t _lane delay formation of transfer in each section;
t _p delay in the establishment of signals in the bits of each section;
τ ₁ , τ ₂ , ... τ _{n the} duration and temporary position of the signals at the outputs and inputs of the respective blocks.

The parameters of an analog-to-digital converter with a uniform quantization step in terms of level in its entire dynamic range are characterized by the following values:
the dynamic range of the analog-to-digital converter (U _dd ) is not less than the level of the expected input process, i.e.

(A _c + A _n ) ≅ U _dd / 2;
the bit depth of the output binary word of the analog-to-digital converter (N) provides the difference of the drive in the absence of interference on the background of natural noise and natural quantization noise. The total number of quantum levels (N _k ),
N _k = 2 ^N ;
the quantum accuracy of the process X (t) is characterized by 1/2 quantization steps in terms of (ε _t ) ε _t = U _dd / N _k
the accuracy of the rough estimate of the interference is characterized by 1/2 of the rough quantization step in terms of level (ε _g )
ε _g = U _dd / 2 ^(NK) ;
a priori data on the maximum signal level are determined by the number of ADC bits in which the dynamic range of the signal with a margin of fluctuations in the transmission channel (σ $\genfrac{}{}{0ex}{}{\text{2}}{\text{c}}$ )
A _c + σ $\genfrac{}{}{0ex}{}{\text{2}}{\text{c}}$ ≅ ε _t 2 ^(NK) ;
sampling-storage frequency (F _BX , provides a sufficiently accurate sampling of the input process in time
F _BX > (6.10) f _max = L f _max ;
the clock frequency of the analog-to-digital converter (f _t ADC) allows for the time Δt1 / F _BX to code-convert the instantaneous readout into a binary N bit code.

Мощность шумов квантования для "тонкой" структуры аналого-цифрового преобразования (P $\genfrac{}{}{0ex}{}{\text{n}}{\text{кв}}$ ) определяется в самом неблагоприятном случае квадратом половины точного шага квантования
(ε_т/2) P $\genfrac{}{}{0ex}{}{\text{n}}{\text{кв}}$ = ε $\genfrac{}{}{0ex}{}{\text{2}}{\text{т}}$ /4;
Аналогично, для "грубой" структуры базиса аналого-цифрового преобразования P $\genfrac{}{}{0ex}{}{\text{u}}{\text{кв}}$ = ε $\genfrac{}{}{0ex}{}{\text{2}}{\text{г}}$ /4. Тогда соотношение h $\genfrac{}{}{0ex}{}{\text{2}}{\text{вых}}$ , с учетом P $\genfrac{}{}{0ex}{}{\text{n}}{\text{кв}}$ и P $\genfrac{}{}{0ex}{}{\text{u}}{\text{кв}}$ будет определяться выражением вида:

чем и обусловлена эффективность устройства компенсации помех. При этом интегральное отношение мощности помехи (P_п) к мощности сигнала на выходе компенсатора составляет порядка 3.5 дБ, а интегральная эффективность подавления, определяемая соотношением
G_укп= h $\genfrac{}{}{0ex}{}{\text{2}}{\text{вх}}$ /h $\genfrac{}{}{0ex}{}{\text{2}}{\text{вых}}$ ;
где h $\genfrac{}{}{0ex}{}{\text{2}}{\text{вх}}$ (P_п/P_с)_вх, h $\genfrac{}{}{0ex}{}{\text{2}}{\text{вых}}$ (P_п/P_с)_вых, для различных видов помех составляет в среднем 18.23 дБ.The technical advantages of the proposed interference compensation device are that at its output we obtain a signal with a ratio of the power of uncompensated interference to the signal power close to unity (above):

Quantization noise power for the “fine” structure of analog-to-digital conversion (P $\genfrac{}{}{0ex}{}{\text{n}}{\text{sq}}$ ) is determined in the worst case by the square of half the exact quantization step
(ε _t / 2) P $\genfrac{}{}{0ex}{}{\text{n}}{\text{sq}}$ = ε $\genfrac{}{}{0ex}{}{\text{2}}{\text{t}}$ /4;
Similarly, for the “rough” structure of the basis of the analog-to-digital conversion P $\genfrac{}{}{0ex}{}{\text{u}}{\text{sq}}$ = ε $\genfrac{}{}{0ex}{}{\text{2}}{\text{g}}$ /4. Then the relation h $\genfrac{}{}{0ex}{}{\text{2}}{\text{out}}$ , taking into account P $\genfrac{}{}{0ex}{}{\text{n}}{\text{sq}}$ and P $\genfrac{}{}{0ex}{}{\text{u}}{\text{sq}}$ will be determined by an expression of the form:

which determines the effectiveness of the interference compensation device. In this case, the integral ratio of the interference power (P _p ) to the signal power at the output of the compensator is of the order of 3.5 dB, and the integral suppression efficiency, determined by the ratio
G _ukp = h $\genfrac{}{}{0ex}{}{\text{2}}{\text{in}}$ / h $\genfrac{}{}{0ex}{}{\text{2}}{\text{out}}$ ;
where h $\genfrac{}{}{0ex}{}{\text{2}}{\text{in}}$ (P _p / P _s ) _in , h $\genfrac{}{}{0ex}{}{\text{2}}{\text{out}}$ (P _p / P _s ) _out , for various types of interference averages 18.23 dB.

Obviously, the greater the number of quantization levels N _k , the more accurately the signal is tracked for a given dynamic range at the input, the lower the level of quantization noise. In turn, the more the number of bits is allocated for the analysis of the dynamic range of the useful signal, the rougher the interference is tracked for given N and U _dd , and the greater the level of quantization noise. In this case, the optimal values of the number of bits of the converter (K) allocated for signal analysis should be selected within (0.5.0.6) of the number of bits of the binary code (N) at the output of the analog-to-digital converter.

Степень реального подавления помех будет определяться разрядностью аналого-цифрового преобразователя и числом разрядов отводимых для анализа сигнала.The potential efficiency from the use of the device, estimated by the allowable excess of the interference power over the input signal power, expressed in terms of the number of bits of the analog-to-digital converter allocated for signal analysis (K) and its bit depth (N), can be estimated by an expression of the form:

The degree of real interference suppression will be determined by the capacity of the analog-to-digital converter and the number of bits allocated for signal analysis.

 Elements of the proposed device are typical and can be technically implemented at the present time using the available element base. The specific values of the time parameters of the blocks, as well as the ADC and subtracter bits, the Schmitt trigger threshold, are selected based on the parameters of the signals at the input of the device, the requirements for the accuracy of their quantization and the necessary level of noise suppression. An analog-to-digital converter can be performed on the basis of serial integrated circuits, for example, described in the book under the editorship of A.J. K. Marcinkevičius, E.-A. K. Baghdanskis. High-speed integrated circuits DAC and ADC and measurement of their parameters. M. Radio and Communications, 1988 .-- 224 p. Subtractor (adder operating in the subtraction mode), Schmitt trigger, the first and second adders modulo two, the logic circuit “I”, the inverter, the delay element, the pulse generator and the inverter with the output expansion “OR-NOT” can be performed on the basis of serial integrated circuits, for example, described in the book Shilo V.P. Popular digital circuits: a Reference. M. Radio and Communications, 1987, 352 pp. and in the book under the editorship of M.I. Zhodzishsky. Digital Radio Receiving Systems: A Guide. M. Radio and Communications, 1990.208 p.

Claims (1)

 An interference compensation device comprising an analog-to-digital converter, a subtracter, a delay element and a pulse generator, the first output of which is connected to the first input of the analog-to-digital converter, characterized in that an inverter, a Schmitt trigger, the first and second adders modulo two are inserted into it, the AND element and the inverter with the expansion by the output OR - NOT, while the first and second groups of outputs of the analog-to-digital converter are connected to the corresponding groups of inputs of the subtractor, to the first additional group of inputs which the first group of outputs of the analog-to-digital converter is connected through an inverter, the first output of the second group of outputs of the analog-to-digital converter is connected to the first input of the And element, the output of which is connected to the first input of the second adder modulo two and to the input of the inverter with an extension of the output OR NOT, the outputs of which are connected to the corresponding inputs of the second additional group of inputs of the subtractor, one of the outputs of the subtractor is connected to the first input of the first adder, to the second input of which the trigger output is connected and Schmitt through a series-connected second adder modulo two and a delay element, the other input of which is connected to the second output of the pulse generator, the third output of which is connected to the second input of the element And, the input of the Schmitt trigger is connected to the input of the analog-to-digital converter and is the input of the device, the outputs which are the respective outputs of the subtractor and the output of the adder modulo two.

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