RU2064190C1 - Device for suppression of multiple-component interference - Google Patents

Abstract

FIELD: air-traffic control. SUBSTANCE: device has two suppression units, two multiplication units, two adders, unit for assessing noise characteristics, unit of weight coefficients, memory unit, multiplication unit, N-2 additional delay units, M-1 additional memory units, N-2 additional multiplication units, subtraction unit N-1 additional memory units, M-1 additional multiplication units, synchronization unit. This results in possibility to suppress three-component interference when radar is subjected to multiple component correlation interference. EFFECT: increased efficiency of radar signal processing. 7 cl, 16 dwg

Description

 The invention relates to radar can be used in air traffic control systems in civil aviation.

 A device for coherent adaptive processing of radar signals (1), containing two delay units, a subtraction unit, a weighting unit, a multiplication unit, a summing unit. However, this device does not provide high noise immunity against the background of multicomponent passive interference with unknown parameters. A significant disadvantage of the known device is the low noise immunity in the entire Doppler range due to the inconsistency of the amplitude-frequency characteristic (AFC) of the signal processing device with the energy spectrum of multicomponent interference due to the adaptation of the known processing device to the parameters of one frequency component of passive interference.

 Closest to this invention is a device for suppressing two-component passive interference (2) selected as a prototype.

 A disadvantage of the known device is the impossibility of a sufficiently complete and simultaneous consideration of the parameters of three, four or more components of multicomponent passive interference. This leads to the appearance of significant residual notches at the output of a known device with an increase in the number of components (due to the inability to simultaneously evaluate the parameters of more than two components). These factors lead to insufficient processing of radar signals against the background of multicomponent passive interference.

 The aim of the invention is to increase the processing efficiency of radar signals against the background of multicomponent correlated interference with a priori unknown parameters.

 In FIG. 1 is a structural electrical diagram of a multi-component interference suppression device; in FIG. 2 is a structural circuit diagram of a delay unit, an additional delay unit, an additional storage unit; in FIG. 3 is a structural electrical diagram of a multiplication unit, a multiplication unit, an additional multiplication unit, an additional multiplication unit; in FIG. 4 is a structural electrical diagram of a first summing unit, a second summing unit, a summing unit; in FIG. 5 is a structural electrical diagram of an interference parameter estimator; in FIG. 6 is a structural electrical diagram of a weighting unit; in FIG. 7 is a structural electrical diagram of a memory unit, an additional memory unit; in FIG. 8 is a structural electrical diagram of a sync generator; in FIG. 9 is a structural electrical diagram of a subtraction unit; in FIG. 10 is a structural block diagram of a correlation coefficient estimator; in FIG. 11 is a structural electrical diagram of a normalization unit; in FIG. 12 is a block diagram of a complex conjugate multiplication block; in FIG. 13 is a block diagram of a power estimation unit; in FIG. 14 is a structural circuit diagram of a line of read-only memory; in FIG. 15 shows the dependences of the noise reduction coefficients on the relative power of the third interference component for the proposed device and for the prototype; in FIG. 16 shows the dependences of the noise reduction coefficients on the relative speed of the third interference component for the proposed device and for the prototype.

A multi-component interference suppression device operates as follows. A pack of coherent radio pulses arriving at the input of the receiving device of the radar station, passing the cascades of amplification and demodulated in the phase detectors of each of the two quadrature channels, is fed through analog-to-digital converters in the form of digital samples X _n to the inputs of the inventive device, which is a pair of inputs of the first block 1 delays. The signal X passes through two delay blocks 1 and (N-2) additional delay blocks 10 (Fig. 1), which form a delay line.

Each of the delay units 1 and the additional delay units 10 (Fig. 2) includes two parallel-connected random access memory (RAM) 16. Each RAM 16 is designed to store digital samples of the distance rings of one quadrature channel during the repetition period of the probe pulses T. Organization of RAM 16 corresponds to the FILO principle (the first to enter - the last to exit). The RAM capacity is determined by the number of rings of the range of the radar station and the resolution of each reference h
V = lh
The signals from the input of the delay line are fed to the first inputs of the second summing unit 4 (Fig. 1).

 The second summing unit 4 (FIG. 4) includes two multi-input adders 18. The first adder 18 sums the signals from the first quadrature (N + 1) input pairs of the second summing unit 4. The second adder 18 sums the signals from the second quadrature (N + 1) pairs of inputs of the second summing unit 4.

 The signals from the outputs of each block 1 delay (Fig. 1) come through the corresponding block 2 multiplication on the second block 4 of the summation.

The multiplication block 2 (Fig. 3) includes four multipliers 17, an adder 18 and a subtractor 19. The multiplication block 2 implements the multiplication of the first (A ₁ + B ₁ ) and second (A ₂ + B ₂ ) complex numbers:
(A ₁ + JB ₁ ) (A ₂ + JB ₂ ) A ₁ A ₂ - B ₁ B ₂ + J (A ₂ B ₁ + A ₁ B ₂ )
Moreover, the first complex number (A ₁ + B ₁ ) represents the first And ₁ and the second In ₁ quadrature signal X _n . The second complex number (A ₂ + JB ₂ ) represents the first A ₂ and second B ₂ quadratures of the corresponding weight coefficient supplied to the second inputs of the multiplication block 2. In this case, the signals A ₁ , A _{2 of the} first quadrature inputs of the multiplication block 2 are supplied to the inputs of the first multiplier 17, forming the product A ₁ A ₂ . The signals B ₁ , B _{2 of the} second quadrature inputs of the multiplication block 2 are fed to the inputs of the second multiplier 17, forming the product of B ₁ B ₂ . The signals A _{2 of the} first quadrature of the second quadrature input of the multiplication block 2 and B _{1 of the} second quadrature of the first quadrature input of the multiplication block 2 are fed to the inputs of the third multiplier 17, forming the product of A ₂ B ₁ . The signals A _{1 of the} first quadrature of the first quadrature input of the multiplication block 2 and B _{2 of the} second quadrature of the second quadrature input of the multiplication block 2 are fed to the inputs of the fourth multiplier 17, forming the product A ₁ B ₂ . The output signals (A ₁ A ₂ ) of the first multiplier 17 and (B ₁ B ₂ ) of the second multiplier 17 are fed to the inputs of the subtractor 19, which forms the difference (A ₁ A ₂ B ₁ B ₂ ). The output signals (A ₂ B ₁ ) of the third multiplier 17 and (A ₁ B ₂ ) of the fourth multiplier 17 are fed to the inputs of a two-input adder 18, forming the sum (A ₂ B ₁ + A ₁ B ₂ ). The output signal of the subtractor 19 is the first quadrature output quadrature signal of the block 2 multiplication. The output signal of the adder 18 is the second quadrature output quadrature signal of the block 2 multiplication.

 The signals from the outputs of each additional delay unit 10 (Fig. 1) are supplied through the corresponding additional multiplication unit 12 to the corresponding additional inputs of the second summing unit 4, the pair of outputs of which are outputs of the multi-component interference suppression device.

 The additional block 12 multiplication is similar in structure and operating principle to the block 2 multiplication (Fig. 3).

 Waist way, on a line of 2 blocks 1 delay and (N-2) additional blocks 10 delay (Fig. 1), 2 blocks 2 multiplication and (N-2) additional blocks 12 multiplication, the second block 4 summation is implemented N-order non-recursive notch filter (1) This filter whitens correlated noise.

 The complex coefficients of the weight vector of the column column W of the non-recursive whitening filter are supplied from the outputs of the block 6 of the weight coefficients to the second pairs of inputs of the blocks 2 multiplication and additional blocks 12 multiplication.

 Block 6 weighting coefficients (Fig. 6) contains (2N + 1) logical elements AND 22. The first input of the first logical element 22 And receives clock pulses from input "a" of block 6 weighting factors. The second input of the first logical element And 22 receives signals of zeroing from the input "b" block 6 weighting factors. The first inputs of the subsequent 2Nh logic gates And 22 receive signals from the output of the first logical gate And 22. The second input of each of the 2Nh logical gates And 22 receives the corresponding bit of the corresponding quadrature of the corresponding quadrature input of the block 6 weighting factors. The signals from the output of each of the 2Nh logical elements AND 22 are supplied to the corresponding bit of the corresponding quadrature of the corresponding quadrature output of the block 6 weight coefficients. In fact, the N inputs of the block 6 of the weighting coefficients are switched with its N outputs at the time of the simultaneous arrival of the clock pulse and the zeroing signal.

The normalized power P at the output of a non-recursive notch filter (Fig. 1) can be estimated by the formula (4):
PW ^{T *} RW / W ^{T *} W, where:
R complex correlation matrix of the input process;
T sign of transportation;
* sign of complex pairing.

где X_n n-й входной отсчет,
S_n n-й ненормированный коэффициент АКП.To maximize the interference suppression coefficient K, defined as K I / P, the matrix R is estimated and, based on this estimate, a vector W is formed, which is the first column vector of the inverse correlation matrix G of the input process. The procedure for generating the inverse matrix is fraught with great computational difficulties. The use of a recursive whitening filter, which uses the first column vector of the matrix R as the vector V of weighting coefficients, that is, the normalized autocorrelation sequence (ACP) of the input process [4], however, allows for a significant simplification of the problem of adaptive interference cancellation [4] However, the transparency zones for the recursive whitening filter signal are small orders are greatly narrowed [4], which reduces the efficiency of using recursive notch filters on short packs under conditions typical of radiolocation kopolosnyh correlated noise. A limited-order non-recursive filter (N <10) is more effective in suppressing such interference, since It has wide transparency areas for the signal and narrow areas of rejection. Avoid the computational complexity of the formation of the weight vector W of a non-recursive notch filter allows the approach implemented in the inventive device. At the first stage, in block 5 of the estimation of interference parameters (Fig. 5), the weight vector V of the recursive whitening filter of the Mth order is formed, i.e. calculation of the M coefficients of the normalized ACP of the input process. For this, in blocks 20 of the assessment of the correlation coefficients, M non-normalized values of the ACC coefficients are determined by the algorithm:

where X _{n is the} n-th input sample,
S _n n-th non-normalized coefficient of automatic transmission.

В результате на выходах блока 5 оценки параметров помех формируются комплексные коэффициенты весового вектора V.Then, in the normalization block 21, by the formula (1), the input process power S ₀ is estimated and M normalizing factors are generated, each of which from the corresponding output of the normalization block 21 is fed to the normalizing input of the corresponding correlation coefficient estimation block 20. The coefficients R _j normalized AKP are calculated by the algorithm:

As a result, at the outputs of block 5 for evaluating the interference parameters, complex coefficients of the weight vector V are formed.

 The signals from the i-th pair of inputs of block 5 for estimating the interference parameters are supplied to the (2i 1) -th pair of inputs of each block 20 for estimating the correlation coefficient. The signals from the i-th pair of inputs of block 5 for estimating the interference parameters, starting from the (j + 1) -th pair, are fed to the 2 (i j) -th pair of inputs of the j-th block 20 of estimating the correlation coefficient. The signals from the corresponding output of the normalization block 21 are fed to the normalizing input of the corresponding correlation coefficient estimation block 20. The signals from the inputs of block 5 estimates the interference parameters are fed to the inputs of block 21 normalization. The output signals of the blocks 20 of the assessment of the correlation coefficient are the coefficients of the normalized AKP input process.

The correlation coefficient estimator 20 (Fig. 10) includes (N j + 1) complex conjugate multiplication blocks 29, the summation unit 30 and two divisors 31. Moreover, the i-th complex conjugate multiplier 29 of the i-th correlation coefficient estimator 20 forms an unnormalized estimate of the instantaneous value of the i-th correlation coefficient U _{i, j} according to the algorithm:
u _{i, j} = X _(ij) X $\genfrac{}{}{0ex}{}{\text{*}}{\text{i}}$
Block 29 complex conjugate multiplication (Fig. 12) consists of four multipliers 17, adder 18 and subtractors 19. Block 29 complex conjugate multiplication implements the multiplication of the first (A ₁ + jB ₁ ) and second complex conjugate (A ₂ jB ₂ ) complex numbers:
(A ₁ + JB ₁ ) (A ₂ JB ₂ ) A ₁ A ₂ + B ₁ B ₂ + J (A ₂ B ₁ A ₁ B ₂ )
In this case, the signals A ₁ , A _{2 of the} first quadrature inputs of the complex complex conjugate multiplication unit 29 are supplied to the inputs of the first multiplier 17, forming the product A ₁ A ₂ . The signals В ₁ , В _{2 of the} second quadrature inputs of the complex complex conjugate multiplication block 29 are supplied to the inputs of the second multiplier 17, which forms the product В ₁ В ₂ . Signals A _{2 of the} first quadrature of the second quadrature input of complex complex conjugate block 29 and B _{1 of the} second quadrature of the first quadrature input of complex complex conjugate block 29 _{of the} second quadrature of the first quadrature input of complex complex conjugate block 29 are fed to the inputs of the third multiplier 17 forming the product A ₂ B ₁ . Signals A _{1 of the} first quadrature of the first quadrature input of complex complex conjugate block 29 and B _{2 of the} second quadrature of the second quadrature input of complex complex conjugate block 29 are input to the fourth multiplier 17, forming the product A ₁ B ₂ . The output signals (A ₁ A ₂ ) of the first multiplier 17 and (B ₁ B ₂ ) of the second multiplier 17 are fed to the inputs of a two-input adder 18, forming the sum (A ₁ A ₂ + B ₁ B ₂ ). The output signals (A ₂ B ₁ ) of the third multiplier 17 and (A ₁ B ₂ ) of the fourth multiplier 17 are fed to the inputs of the subtractor 18, which forms the difference (A ₂ B ₁ A ₁ B ₂ ). The output signal of the adder 18 is the first quadrature of the output quadrature signal of the complex conjugate multiplication unit 29. The output signal of the subtractor 19 is the second quadrature of the output quadrature signal of the complex conjugate multiplication unit 29.

Таким образом, блоки 29 комплeксно сопряженного умножения и блок 30 суммирования, реализующие алгоритмы (3, 4), осуществляют оценку S_j согласно ( 1 ).Block 30 summation is similar in structure and operation to the second block 4 summation (Fig. 4). Block 30 summing the j-th block 20 of the assessment of the correlation coefficient (Fig. 10) generates the j-th non-normalized correlation coefficient according to the algorithm:

Thus, the complex conjugate multiplication blocks 29 and the summing block 30 implementing the algorithms (3, 4) evaluate S _j according to (1).

 The formation of the jth coefficient of the normalized ACP according to (1) is carried out by a pair of dividers 31. The first quadrature of the output quadrature signal of the summing unit 30 is supplied to the first input of the first divider 31. At the first input of the second divider 31, a second quadrature of the output quadrature signal of the summing unit 30 is received. The second inputs of the first and second dividers 31 from the normalizing input of the correlation coefficient estimator 20 are supplied with a normalizing coefficient.

 The formation of the normalizing coefficient occurs in block 21 normalization (Fig. 11).

The normalization block 21 includes (N + 1) power estimation blocks 32, an adder 18, a read-only memory (ROM) line 33 of M multipliers 17. The signals from each of the (N + 1) quadrature inputs of the normalization block 21 are fed to the corresponding evaluation block 32 power. Each block 32 power assessment evaluates the instantaneous power value of the input process N _i according to the algorithm
H _i = A $\genfrac{}{}{0ex}{}{\text{2}}{\text{i}}$ + B $\genfrac{}{}{0ex}{}{\text{2}}{\text{i}}$ (5)
The power estimation block 32 (Fig. 13) consists of two multipliers 17 and a two-input adder 18. The first and second inputs of the first multiplier 17 receive signals from the first quadrature of the quadrature input of the power estimation block 32. From the output of the first multiplier 17, the value of A _{i is} supplied to the first input of the adder 18. The signals of the second quadrature quadrature input of the power estimator 32 are fed to the inputs of the second multiplier 17, the output of which is supplied to the second input of the adder 18. Instantaneous power is generated at the output of the adder 18 input process H _i according to algorithm (5). The signals from the outputs (N + 1) of the power estimation blocks 32 (Fig. 11) are fed to the inputs of the multi-input adder 18 that implements the algorithm (1) for estimating the abnormal power of the input process. From the output of the adder 18, the quantity S _{0 is} supplied to the first inputs of each of the M multipliers 17, which generate the M normalizing coefficients S ₀ (N + 1) / (N j + 1) For this, the quantity ( N + 1) / (N - j + 1) from the corresponding output of the ROM line 33.

Thus, at the output of each multiplier 17, an output normalization signal S ₀ (N + 1) / (N j +1) of the normalization unit 21 is generated.

 Line 33 ROM (Fig. 14) includes M cells 34 ROM, and in the j-th cell 34 ROM stores the factor (N + 1) / (N j +1), arriving at the time of arrival of the synchronizing pulse at the input "a" line 33 ROM.

 At the second stage, the complex coefficients of the weight vector arrive at the recursive whitening filter of the Mth order (Fig. 1). This filter is implemented on the line of memory blocks, consisting of a memory block 7 and (M 1) additional memory blocks 11, a multiplication block 8, (M 1) additional multiplication blocks 15, a subtraction block 13, a first summing block 3, onto the first pair of inputs of which through the multiplication unit, signals are received from the outputs of the memory unit 7, for each subsequent pair of inputs of the first summing unit 3, signals from the outputs of the corresponding additional memory unit 11 are received through the corresponding additional multiplication unit 15. Moreover, the first block 3 summation is similar in structure and operation to the second block 4 summation (Fig. 4).

 The first coefficient of the vector V (Fig. 1) is supplied to the second inputs of the multiplication block 8, each of the following (M-1) vector coefficients is supplied to the second inputs of the corresponding additional multiplication block 15, the signals from the outputs of the summing block 3 are fed through the subtraction block 13 to the inputs memory block lines. The output signals of the subtraction unit 13 are the output signals of this recursive whitewash filter.

 The memory unit 7 (Fig. 7) includes two RAM 23 with a reset and an element And 22. Moreover, each RAM 23 with a reset is designed to store one quadrature of the signals of the recursive whitening filter. At the time of the simultaneous arrival of the clock from the input “a” of the memory unit 7 and the reset signal from the input “b”, the RAM cells 23 are reset (zero) with a reset.

 The subtraction unit 13 (Fig. 9) consists of two subtractors 19, two zero cells 26 of the ROM, the first cell 27 of the ROM, the logical element And 22, the circuit 28 of unequality. Prior to the input of the zeroing signal from input "b", the subtraction unit 13 acts as a subtractor at the output of the recursive filter. For this, a pair of subtractors 19, each of which subtracts the corresponding quadrature component, receives zero signals from the outputs of the zero cells of the ROM 26, which ensures the inversion of the signs of the signals of each quadrature. At the time of the zeroing signal arriving at the first quadrature component of the quadrature output of the subtraction unit 13, a unit is called up from the first cell of the ROM 27. The unequal circuit 28 excludes the possibility of simultaneously calling zero and one from the zero 26 and the first 27 cells of the ROM.

 In subsequent (N + 1) periods of t clock pulses, an initialized recursive filter excited by a single pulse action generates at its output a response corresponding to the first (N + 1) samples of the pulse characteristic of the whitening non-recursive filter.

 The zeroing pulse comes from the output "b" of the clock 9. The clock 9 (Fig. 8) includes a clock generator 24, a frequency divider 25. Moreover, the clock generator 24 generates at its output a sequence of clock pulses with a period t. From the output of the clock generator 24, this sequence goes to the output "a" of the clock 9 and to the input of the frequency divider 25. A frequency divider 25 selects each (N + 1) th clock pulse and generates a sequence of zeroing signals with a period of Nt at the output of "b" of the clock generator 9.

 Thus, based on the assessment of the normalized AKP, an M-order whitening recursive filter is formed (Fig. 1), and then its first N + 1 impulse response coefficients are used as the weight coefficients of a non-recursive notch filter that processes the input sequence. The impulse response of the recursive filter is calculated by supplying a single impulse to the input of the recursive filter and then storing (N + 1) the first impulses of its response in additional storage units 14. Additional storage units 14 (Fig. 2) are similar in structure and operation to delay units 1 .

 From the outputs of the additional storage units 14 through the block 6 weighting coefficients, the coefficients of the impulse response are supplied as weighting factors to the non-recursive processing filter (Fig. 1). Block 6 weights provides the simultaneous supply of weights of the non-recursive filter at the time of arrival of the reset pulse. With its receipt, the inventive device starts the next clock cycle of duration Nt, that is, it produces on the account of the next set of N weight coefficients of a non-recursive filter based on the newly formed automatic transmission, which contains information about the changing noise environment. The zeroing pulse resets the RAM 23 with the reset of the memory block 7 and additional blocks 11 of the memory of the recursive filter and supplies a single pulse to its input, which provides the next clock cycle for the pulse characteristics of the recursive filter.

The advantages in the effectiveness of the proposed multi-component interference suppression device compared to the prototype are illustrated by the dependences of the interference suppression coefficient K on the relative power of the third interference component P ₃ (Fig. 15) and on the relative speed of the third interference component Φ ₃ (Fig. 16). These dependences are based on the calculation of the suppression of three-component passive interference with the effective spectral width of each component, the relative speed of the first component Φ ₁ = 0, the second component Φ ₂ = 0.4, the relative power of the first component P ₁ 1, the second component P ₂ 1, number conditioning the input correlation matrix of the process was taken to be 10 ^-6 M 5, N 6, wherein for the first function (FIG. 15) the value adopted by the third component of the relative velocity equal to Φ ₃ = 1, and for a second function (FIG. 16) regarding the value tion of the third component of power assumed to be P ₁ March.

The gain in efficiency lies in the fact that with a changing relative power of the third component P _3, the interference suppression coefficient for the proposed device K _{2 is} higher than the interference suppression coefficient for the prototype K ₁ . For example, with the relative power of the third component P ₃ 0.5 K ₁ 1.48 dB, and K ₂ 6.66 dB, which provides a gain in the noise reduction coefficient from the optimal speed (Φ ₃ = 0.8) K ₁ 0.79 dB, and K ₂ 4.11 dB, which provides a gain in the suppression coefficient ΔK = 3.32 dB (Fig. 16). With an increase in the relative power of the third component of the interference and with its approach to the optimal speed, the gains K, with all other conditions unchanged, will increase. YYY2 YYY4 YYY6 YYY8 YYY10 YYY12 YYY14

Claims (7)

 1. A multi-component interference suppression device, comprising two series-connected delay units, characterized in that two additional multiplication units, a first summing unit, a second summing unit, an interference parameter estimating unit, a weighting coefficient unit, a memory unit, a multiplication unit, a clock generator are introduced, moreover the pair of inputs of the first delay unit is the inputs of the multi-component interference suppression device and is connected to the first pair of inputs of the interference parameter estimation unit, the second pair of inputs of the couple evaluation unit meters of interference is connected to a pair of outputs of the first delay unit and to a pair of first inputs of the first multiplication unit, the third pair of inputs of the unit for evaluating interference parameters is connected to a pair of outputs of the second delay unit and to the first pair of inputs of the second multiplication unit, the second pair of inputs of the first multiplication unit is connected to the first a pair of outputs of the block of weights, the second pair of inputs of the second block of multiplication is connected to a second pair of outputs of the block of weights, a pair of outputs in-phase and quadrature components of the signal the second summing unit is the outputs of the multi-component interference suppression device, N-2 additional delay units connected in series, M-1 additional memory units connected in series, N-2 additional multiplication units, subtraction unit, N-1 additional memory units connected in series, M-1 additional blocks of multiplication, and a pair of inputs of the first additional delay unit is connected to a pair of outputs of the second delay unit, a pair of outputs of each additional delay unit connected to the first pair of inputs of the corresponding additional unit of multiplication and with the corresponding additional pair of inputs of the unit for estimating interference parameters, the pair of inputs of the multi-component interference suppression device is connected to the first pair of N + 1 pairs of inputs of the in-phase and quadrature components of the signal of the second summing unit, the pair of outputs of the first block of the multiplier is connected with the second pair of inputs of the in-phase and quadrature components of the signal of the second summing unit, the pair of outputs of the second multiplying unit is connected the third pair of inputs of the in-phase and quadrature components of the signal of the second summing block, the pair of outputs of each additional block of multiplication is connected to the corresponding pair of inputs of the common-mode and quadrature components of the signal of the second summing block, starting from the fourth pair of inputs, the second pair of inputs of each additional block of multiplication is connected to the corresponding pair of outputs block weighting factors, starting from the third pair of outputs, the first pair of outputs of the block estimates the interference parameters connected to the first by the array of inputs of the multiplication block, each of the subsequent M-1 pairs of outputs of the interference parameter estimation block is connected to the first pair of inputs of the corresponding additional multiplication block, the pair of outputs of the memory block is connected to the second pair of inputs of the multiplication block and to the pair of inputs of the first additional memory block, the pair of block outputs multiplication is connected to the first pair of M pairs of inputs of the in-phase and quadrature components of the signal of the first summing unit, each of the subsequent M-1 pairs of inputs of the common-mode and quadrature components of the signal o the summation block is connected to a pair of outputs of the corresponding additional multiplication block, the pair of outputs of each additional memory block is connected to a second pair of inputs of the corresponding additional multiplication block, the pair of outputs in-phase and quadrature components of the signal of the first summation block is connected through the subtraction block to the pair of inputs of the memory block, the inputs of the first additional storage unit and the first pair of inputs of the weighting unit, each of the subsequent N- 1 pairs of inputs of the weighting unit of coefficients is connected to a pair of outputs of the corresponding additional storage unit, the sync input of each of the listed blocks is connected to the first output of the clock generator, the input of zeroing the block of weight coefficients, the memory block, each of the additional memory blocks, the subtraction block is connected to the second output of the clock generator.  2. The device according to claim 1, characterized in that the first summing unit contains two adders, each of the M inputs of the first adder being connected to the in-phase component of the corresponding pair of M pairs of in-phase and quadrature component inputs of the signal of the first summing unit, each of the M inputs of the second the adder is connected to the quadrature component of the signal of the first summing unit, the output of the first adder is the in-phase component of the pair of outputs of the in-phase and quadrature components of the signal of the first summing unit, the output d of the second adder is the quadrature component of the pair, the output-phase and quadrature components of the first signal summation unit, the clock of the first summation unit coupled to the clock first and second adders.  3. The device according to claim 1, characterized in that the second summing unit contains two (N + 1) input adders, the inputs of the first adder being connected to the common-mode components of the corresponding pairs of (N + 1) pairs of common-mode and quadrature input components of the second unit summation, the inputs of the second adder are connected to the quadrature components of the corresponding pairs of (N + 1) pairs of inputs of the in-phase and quadrature components of the signal of the second summing unit, the output of the first adder is the in-phase component of the pair of outputs hydrochloric and quadrature components of the second signal summation unit, the output of the second adder is the quadrature component of the pair of inphase and quadrature components of the second summing unit output signal, the clock of the second summing unit connected to the clock the first and second adders.  4. The device according to claim 1, characterized in that the block for estimating interference parameters contains M blocks for estimating the correlation coefficient, a normalization block, and the i-th of N + 1 pairs of inputs of the block for estimating interference parameters is connected to the (2i-1) -th pair the inputs of each block for estimating the correlation coefficient, the first of (N + 1) pairs of inputs of the block for estimating interference parameters, starting from the (j + 1) -th pair, is connected to the 2 (j 1) -th pair of inputs of the j-th normalization by the normalizing input of the corresponding correlation coefficient estimation unit, each of N + 1 pairs of inputs of the normalization unit is connected to the corresponding The pair of inputs of the block for estimating the noise parameters, the pairs of outputs of the blocks for estimating the correlation coefficient are the outputs of the block for estimating the noise parameters, the clock input of the block for estimating the noise parameters is connected to the synchro inputs of all the blocks of the parameter for estimating noise parameters.  5. The device according to claim 1, characterized in that the weighting unit contains (2Nh + 1) AND elements, the first input of the first element And connected to the sync input of the weighting unit, the second input of the first element And connected to the zeroing input of the weighting unit, the first inputs of the subsequent 2Nh elements And are connected to the output of the first element And, the second input of each of the 2Nh elements And is connected to the corresponding bit of the corresponding quadrature of the corresponding pair of N pairs of inputs of the block of weight coefficients, the output of each of 2Nh e ments and connected to a respective discharge a corresponding squaring respective pair of N pairs of outputs block weighting coefficients.  6. The device according to claim 1, characterized in that the memory unit contains two random access memory devices with a reset, AND element, with each quadrature of the pair of inputs of the memory block connected to the input of the corresponding random access memory device with a reset, the output of the first random access memory with a reset is the first quadrature of the pair of outputs of the memory block, the output of the second random access memory with a reset is the second quadrature of the pair of outputs of the memory block, the first input of the And element, the sync inputs op iterative memory devices with a reset are connected to the sync input of the memory block, the zeroing input of the memory block is connected to the second input of the And element, the output of the And element is connected to the reset inputs of the random access memory with a reset.  7. The device according to claim 1, characterized in that the clock generator contains a clock generator, the output of which is the synchronization output of the clock generator, a frequency divider, the output of which is the output of zeroing the clock, the input of the frequency divider connected to the output of the clock generator.

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