RU2045095C1 - Process of optimum formation of visible image - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: process consists in continuous reconstruction of pixel array forming preassigned sequence of frames with the aid of isotropic processors which number n is chosen in agreement with expression

, where k if number of frames per second, p is number of pixels in frame; t₀ is time of reconstruction (processing) of one pixel by one processor; C₀ is cost of components of circuit used collectively; C₁ is cost of one processor and equipment used by this processor. Description gives example of realization of process by device built on principle of parallel input of information while processing pixels which includes external storage, control unit, input commutator, channel commutators with keys, two buffer storages, isotropic processors, screen storage. EFFECT: increased speed of response, minimized cost of equipment expenditures for its realization. 2 cl, 1 dwg

Description

 The invention relates to computer technology and is intended for digital optimal synthesis and reproduction of images, sound and other perceptions in real time with the ability to record to a medium (video tape, disk) or output to the screen.

 From a technical solution [1], a method for parallel processing of video information is known in which an odd number of pixels is selected in a frame: the number of horizontal pixels (2k + 1) and vertical pixels (2L + 1), resulting in a grid of rectangular pixels; A pixel located in the center of this lattice (pattern) is subjected to calculation. To perform the calculations, (2L + 1) (2k + 1) computing units (processors) are required.

 The disadvantage of this method is not optimal in terms of minimizing hardware costs for its implementation, since the number of processors is uniquely determined by the area of the processed picture, in the center of which the desired point is located, but the dimensions of the picture itself are not optimized, but are chosen arbitrarily.

 From the technical solution [2], which is the closest analogue, there is a known method for constructing visual images (geometric shapes) on a computer screen, including continuous restoration of an array of pixels and the formation of a given sequence of frames using homogeneous processors.

The disadvantage of this method is the following:
1. The method can create on the screen only images of geometric figures constructed by segments of straight lines, but is not able to create images containing natural components (photos, videos, etc.).

 2. The method does not guarantee the use of all the resources of the circuit when constructing the image: parallelization of computations is achieved in it by dividing the screen into squares, each of which is serviced by its own processor, and if a corresponding element of the geometric figure is missing in a certain square, then the processor responsible for this square is idle.

 3. The method does not guarantee minimization of costs for its hardware implementation, because the number of screen divisions into squares is not determined by anything.

 The aim of the invention is to increase the speed of image construction, minimizing the cost of hardware costs during its implementation and expanding its capabilities.

≅ n ≅

, где n число процессоров,
k число кадров в 1 с;
р число пикселей в кадре,
t₀ время восстановления (обработки) одного пиксела одним процессором,
С₀ стоимость коллективно используемых компонентов схемы;
С₁ стоимость одного процессора и используемого только им оборудования.This is achieved by the fact that in the method of constructing a visual image, which consists in the continuous restoration of an array of pixels forming a given sequence of frames using homogeneous processors, the number of processors is selected based on the condition:
kpt

≅ n ≅

where n is the number of processors
k number of frames in 1 s;
p is the number of pixels in the frame,
t ₀ recovery time (processing) of one pixel by one processor,
With _{0, the} cost of collectively used circuit components;
With _{1, the} cost of one processor and equipment used only by it.

 The choice of the upper and lower bounds determining the choice of the optimal number of processors is based on the following premises.

 The end result of the implementation of the method, as mentioned above, is the minimization of the cost of the circuit that implements the method, while guaranteeing the achievement of the image quality specified by the parameters k and p and achieving the minimum cost per unit of the circuit time while guaranteeing the preservation of image quality.

 In both cases, the optimization tool is the number of processors n.

, (1) где а и b коэффициенты, определяемые как:

(a + b/n) t₀, откуда а t₀.The processing time of one frame is inversely proportional to the number of processors, but cannot be less than the time to calculate the parameter of one pixel by one processor. Then the equality is true:
a +

, (1) where a and b are coefficients, defined as:

(a + b / n) t ₀ , whence a t ₀ .

For n 1, 1 / k pt ₀ , whence
b + t ₀ pt ₀ or
b (p 1) t ₀ , where t _{0 is} the processing time of one pixel.

, откуда следует
n kpt₀

(2)
Так как правая часть равенства (2) содержит произведение kp, определяющее качество изображения, уменьшение величины n по отношению к условию, задаваемому (2), приведет к нарушению качества изображения, что не допустимо. Таким образом, допустимым является такое число процессоров n, для которого справедливо:
n≥ kpt_o

(3)
Как отмечалось выше, время формирования одного кадра определяется выражением t

. Если положить, что стоимость единицы времени прибора линейно зависит от числа используемых процеcсоров n и определяется зависимостью вида С₀+ С₁n₁, то стоимость Q формирования одного кадра устройством, содержащим n однородных процессоров, равна:
Q qt₀(C₀ + C₁n)(1 + p/n), (4) где q коэффициент пропорциональности.Given that p> 1 and taking a t ₀ (1) can be written in the form
t ₀ +

from where
n kpt ₀

(2)
Since the right-hand side of equality (2) contains the product kp, which determines the image quality, a decrease in n with respect to the condition specified by (2) will lead to a violation of image quality, which is not permissible. Thus, the number of processors n that is valid is valid for which:
n≥ kpt _o

(3)
As noted above, the formation time of one frame is determined by the expression t

. If we assume that the unit cost per unit of time linearly depends on the number of processors used n and is determined by the dependence of the form C ₀ + C ₁ n ₁ , then the cost Q of forming one frame by a device containing n homogeneous processors is:
Q qt ₀ (C ₀ + C ₁ n) (1 + p / n), (4) where q is the coefficient of proportionality.

0, откуда следует
n

(5)
Так как при любых значениях n вторая производная

> 0 0, значение n, определяемое (4), соответствует минимальному значению Q.Equating the derivative dQ / dn to zero, we obtain an extremum point that corresponds to the condition:
C ₁ -

0, whence
n

(5)
Since for any values of n the second derivative

> 0 0, the value of n determined by (4) corresponds to the minimum value of Q.

(6)
Сочетание (3) и (6) приводит к уcтановлению значений нижней и верхней границ выбора оптимального числа n.Since an increase in the number of processors then leads to an increase in Q, the inequality holds:
n≅

(6)
The combination of (3) and (6) leads to the establishment of the values of the lower and upper boundaries for choosing the optimal number n.

 If, as a result of the implementation of the inequalities, the number n is not integer, but fractional, then it is rounded to the nearest larger integer.

Пример реализации изобретения показан на чертеже.In addition, an integer n can be obtained by forming the number of processors step by step in accordance with the following condition:
n n1 + n2 (7) where n1 entier (N)
n2 signum (N)
N kpt

An example implementation of the invention is shown in the drawing.

 A device that implements the method includes an input switch 1; channel switches 2, 3, 4, managing keys 2.1-2.n, 3.1-3, respectively. n, 4.1-4.n; external memory 5, control system 6, buffer memory N1: blocks 7.1.11-7.n.21; processors 8.1-8.n; buffer memory N2; blocks 9.1.12-9.n. 22; screen memory 10 and communications shown in this figure.

 The devices included in the structure perform standard functions and are implemented using a standard elemental base, for example, blocks 1, 2, 3, 4, 6 can be performed on the basis of similar function blocks from autosw. [1] ie The proposed method does not require new means for its implementation.

 A step-by-step algorithm for the operation of this device is as follows.

 Step 1. Parameter j (frame number) is assigned a value equal to one.

 Step 2. If j 2entier (j / 2), i.e. if j is even, then go to step 4; if j is odd then go to step 3.

 Step 3. Assign parameter d equal to zero, and go to step 5.

 Step 4.d 1.

Step 5. The control system installs all the switches as follows:
5.1. Switch (1) allows reading information from external memory and writing it to buffer memory N1, and in those blocks that have numbers i (2-d) 1, where i 1,2.n. Writing to blocks with numbers i (d + 1) 1, i1, 2, n is prohibited.

 5.2. Switch 2 using keys 2i allows reading information from blocks of buffer memory N1 with numbers i (d + 1) 1, i 1,2,3, n, and information from i (d + 1) of the 1st block goes to i- processor and, at the same time, prohibits reading from blocks with numbers i (2-d) 1, i 1,2, n.

 5.3. Switch 3 using the keys 3.i allows information to be written to blocks of buffer memory N2 with numbers i (2-d) 2, i 1,2, n coming from the i-th processor, and at the same time it prohibits writing to blocks of buffer memory N2 with the numbers i (d + 1) 2, i 1,2, n.

 5.4. Switch 4 using keys 4.i allows reading information from blocks of buffer memory N2 with numbers i (d + 1) 2, i 1,2, n and sending it to the corresponding memory cells on the screen and, at the same time, prohibits reading from blocks of buffer memory N2 with numbers i (2-d) 2.

Step 6. On the open switches 1-4 channels:
a) information on the j-th frame is read by the control system block from the external memory block and distributed among the blocks of buffer memory N1 with numbers i (2-d) 1, i 1,2, n.

b) the information contained in the buffer memory unit N1 with the number i (d + 1) 1, i 1,2, n, enters the i-th processor (i 1,2, n) and, after processing, is written to the buffer memory unit N2 number i (2-d) 2;
c) the information contained in block i (d + 1) 2, i 1,2, n is copied to the corresponding memory cells 10 of the screen, thereby forming information for displaying the (j-1) th frame.

 Step 7. The value of j increases by one.

 Step 8. If j exceeds the maximum allowable value, go to step 9, otherwise, to step 2.

 Step 9. The end of the algorithm.

 Thus, the indicated technical result is achieved in the invention by distributing the calculations by dispersing the processors on the screen so that each processes its own group of pixels, and choosing their optimal number.

Claims (2)

1. METHOD FOR OPTIMUM FORMATION OF A VISUAL IMAGE by continuously restoring an array of pixels forming a given sequence of frames using homogeneous processors, characterized in that the number of homogeneous processors is selected from the condition

where n is the number of homogeneous processors;
k frames per second;
p is the number of pixels in the frame;
t ₀ recovery time of one pixel by one processor;
C _{o the} cost of sharing components;
C _{i is the} cost of one processor and the equipment it uses. 2. The method according to p. 1, characterized in that the determination of the number of homogeneous processors is carried out in accordance with the condition
n = n ₁ + n ₂ ,
where n ₁ = entier (N),
n ₂ = signum (N),

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