RU2020616C1 - Analog storage - Google Patents

Abstract

FIELD: automatics; test equipment. SUBSTANCE: third switch is introduced into analog storage. Attenuator has voltage follower, restricting element made on the base of resistor and voltage divider. Attenuator may also be made of two voltage dividers. EFFECT: improved precision of the device. 3 cl, 3 dwg

Description

 The invention relates to automation and control equipment, is intended for the operation of sampling and storing analog information with increased accuracy and can be used as a functional element of microelectronics in data acquisition and distribution systems of microprocessor devices.

 A device for sampling and storing analog information containing two operational amplifiers, three switches and two capacitors with identical parameters, as well as three resistors and two diodes [1].

 This device is characterized by increased accuracy of information storage achieved by performing two identical discharge capacitor discharge circuits connected to the inputs of the operational amplifier, however, it does not provide the required higher accuracy of storing analog information due to the insufficiently large discharge time constants of the capacitors.

 Of the known devices, the closest in technical essence is a device for storing analog information containing the first and second capacitors, first and second switches, an operational amplifier, as well as a resistor and attenuator, consisting of two series-connected resistors, while the output of the first switch through the resistor is connected with one of the terminals of the first capacitor and a non-inverting input of the operational amplifier, the output of which, which is the output of the device, is connected to one of the terminals of the WTO of the capacitor and the free output of one of the attenuator resistors, the connection point of the attenuator resistors through the second switch is connected to the inverting input of the operational amplifier and the second output of the second capacitor, the second output of the first capacitor and the free output of the second attenuator resistor are connected to the common bus, the control inputs of the first and second switches connected to the control input of the device, and the information input of the first switch is connected to the information input of the device [2].

 This device also has a high accuracy of storing analog information, however, it is not possible to obtain a higher accuracy of information storage in this device due to the unequal discharge time constants of storage capacitors, which are realized even with identical parameters of capacitors and switches.

 The aim of the invention is to improve the accuracy of information storage by ensuring the same and sufficiently large constant discharge time of storage capacitors.

 The goal is achieved in that in a device for storing analog information containing the first and second capacitors, first and second switches, an operational amplifier, as well as a resistor and attenuator, while the output of the first switch through a resistor is connected to one of the terminals of the first capacitor and a non-inverting input of the operating amplifier, the output of which, which is the output of the device, is connected to one of the terminals of the second capacitor and the input of the attenuator, the first output of the attenuator through the second switch is connected to by the operational input of the operational amplifier and the second output of the second capacitor, the second output of the first capacitor is connected to a common bus, and the control inputs of the first and second switches are connected to the control input of the device, a third switch is introduced, the information and control inputs of which are connected respectively to the information and control inputs of the device, and the output of the third switch is connected to the information input of the first switch and the second output of the attenuator.

 The device is also characterized in that the attenuator is made in the form of three resistors and a voltage follower, while the first and second resistors are connected in series and connected between the input and the common attenuator bus, the connection point of the first and second resistors is connected to the first output of the attenuator and through the voltage follower connected to one of the terminals of the third resistor, the second terminal of which is connected to the second output of the attenuator.

 The device also differs in that the attenuator is made in the form of three resistors, the first and second resistors are connected in series and connected between the input and the common bus of the attenuator, the connection point of the first and second resistors is connected to the first output of the attenuator and connected to second output attenuator.

 In FIG. 1 is a structural schematic diagram of a device for storing analog information; figure 2, 3 - implementation options of the attenuator.

 A device for storing analog information (Fig. 1) contains the first and second storage capacitors 1 and 2, the first and second switches 3 and 4, an operational amplifier 5, a load resistor 6, an attenuator 7, and a third switch 8.

 The output of the first key 3 through a resistor 6 is connected to one of the terminals of the first capacitor 1 and a non-inverting input of the operational amplifier 5, the output of which, which is the output 9 of the device, is connected to one of the terminals of the second capacitor 2 and the input 10 of the attenuator 7. The first input 11 of the attenuator 7 through the second key 4 is connected to the inverting input of the operational amplifier 5 and the second output of the second capacitor 2. The second output of the first capacitor 1 is connected to the zero potential bus 12, and the control inputs of the first and second keys 3 and 4 with are united to a control input 13 of the device. The information and control inputs of the third key 8 are connected respectively to the information and control inputs 14 and 13 of the device. The output of the third key 8 is connected to the information input of the first key 3 and the second output 15 of the attenuator 7.

 The attenuator 7 (figure 1) contains the first, second and third resistors 16-18, as well as a voltage follower 19. In this case, the first and second resistors 16 and 17 are connected in series, form a voltage divider, and are connected between the input 10 and the bus 12. The connection point of the first and second resistors 16 and 17 is connected to the first output 11 of the attenuator 7 and is connected to one of the voltage repeater 19 the conclusions of the third resistor 18, the second terminal of which is connected to the second output 15 of the attenuator.

 The attenuator 7 (Fig. 2) is made in the form of a connected first, second, fourth and fifth resistors 16, 17, 20 and 21, forming two voltage dividers.

 The attenuator 7 (Fig. 3) is made in the form of the first, second and third resistors 16-18. The first and second resistors 16 and 17 are connected in series, form a divider and are connected between the input 10 and the common bus 12 of the attenuator 7. The connection point of the first and second resistors 16 and 17 is connected to the first output 11 of the attenuator 7 and connected to the second through the third resistor 18 output 15 attenuator.

 A device for storing analog information works as follows.

Initially, the first and second capacitors 1 and 2, characterized by the nominal values of the capacitance C ₁ and C ₂ , as well as the first, second and third switches 3, 4 and 8, having in the on state low resistances r on ₃ , r on ₄ and r _On and off, large resistance R _{off 3} , R _{off 4} and R _{off 8} , in a first approximation, are considered identical:
C ₁ = C ₂ = C, (1)
r on ₃ = r on ₄ = r on ₈ = r _on , (2)
R _{Off3 vykl.4} = R = R = R _{vykl.8 off.} (3)
The first and second resistors 16 and 17 of the attenuator 7 are also considered identical and their resistance R ₁₆ = R ₁₇ = 2R, and the transfer coefficient of the voltage follower 19 is close to unity. In this case, the first and second capacitors 1 and 2 are assumed to be discharged.

 Under the influence of the signal of the source of control voltage connected between the control input 13 and the bus 12 of the device, the first, second and third switches 3, 4 and 8 are turned on. In this case, using the second key 4, the first and second resistors 16 and 17 of the attenuator 7 are connected to the inverting input of the operational amplifier 5, which form a negative feedback circuit.

R₁₇ = R; R₆ - сопротивление резистора 6.Under the action of the voltage of the signal source connected between the information input 14 and the bus 12 of the device, through the included third and first keys 8 and 3 and resistor 6, the first capacitor 1 is charged with a time constant
τ ₃₁ = [(R _i + r on ₈ ) || R ₁₈ + r on ₁ + R ₆ ] C ₁ ≈
(4)
≈ (R _i + R ₆ + 2 r _on ) C,
where R _i is the internal resistance of the signal source; R ₁₈ is the resistance of the third resistor 18 of the attenuator 7, selected from the condition R ₁₈ >> (R _i + r _on ), actually R ₁₈ = R

R ₁₇ = R; R ₆ is the resistance of the resistor 6.

= 2, которое с помощью первого и второго резисторов 16 и 17 ослабляется (в два раза) и в виде напряжения обратной связи поступает на первый выход 11 аттенюатора 7 и через включенный второй ключ 4 воздействует на инвертирующий вход операционного усилителя 5. Ослабленные напряжения беспрепятственно передается также на выход повторителя 19 напряжения. При данной ситуации разность напряжений, действующая между выводами третьего резистора 18 аттенюатора 7, оказывается незначительной по величине. В связи с этим влияние сопротивления третьего резистора 18 на процесс заряда первого конденсатора 1 заметно не сказывается.The voltage obtained at the first capacitor 1 is transmitted to the output of the operational amplifier 5 with a scale factor determined by the negative feedback circuit (in the first approximation, K ₁ = 1 +

= 2, which with the help of the first and second resistors 16 and 17 is attenuated (twice) and in the form of feedback voltage is supplied to the first output 11 of the attenuator 7 and through the included second key 4 acts on the inverting input of the operational amplifier 5. The attenuated voltage is freely transmitted also to the output of the voltage follower 19. In this situation, the voltage difference between the terminals of the third resistor 18 of the attenuator 7 is small in magnitude. In this regard, the influence of the resistance of the third resistor 18 on the charge process of the first capacitor 1 is not noticeably affected.

Under the influence of the voltage difference formed between the output and the inverting input of the operational amplifier 5, the second capacitor 2 is charged with a time constant
τ ₃₂ = (R ₁₆ || R ₁₇ + r on ₂ ) С ₂ = (R + r _on ) С (5)
In order to ensure equal charge time constants (4), (5) with identical parameters (1), (2), the nominal value of the resistor 6 is determined from the condition
R ₆ = R - R _i - r _on (6)
The resulting negative feedback voltage is continuously compared with the voltage accumulated by the first capacitor 1, forming a voltage increment ΔU between the inputs of the operational amplifier 5. Due to the fact that the voltage at the inverting input of the operational amplifier 5 is less than the voltage acting at the non-inverting input by ΔU, the second capacitor 2 in steady state is charged to a voltage exceeding the voltage value of the first capacitor 1 by the value of this increment.

 At the end of the voltage at the control input 13, the first, second and third keys 3, 4 and 8 go into the off state and the device as a whole is transferred to the storage mode of the accumulated analog information.

=

C₁≈

C, (7)

=

R

R₁₇+

C₂≈

C, (8) где К - коэффициент, характеризующий отношение напряжений, действующих между информационным входом и выходом первого и второго ключей 3 и 4 (этот коэффициент при оговоренных выше условиях весьма близок к единице).When the third switch 8 is turned off, the voltage from the output of the repeater 19 through the third resistor 18 is freely transferred to the second output 15 of the attenuator 7 and then to the information input of the first switch 3 and the voltage difference between its information input and output becomes the same (close to zero) as the voltage difference between the information input and the output of the second switch 4. In this regard, the first and second capacitors 1 and 2 begin to gradually discharge with sufficiently large and with identical parameters (1), (3) approximately equal time constants:

=

C ₁ ≈

C, (7)

=

R

R ₁₇ +

C ₂ ≈

C, (8) where K is the coefficient characterizing the ratio of the voltages acting between the information input and the output of the first and second switches 3 and 4 (this coefficient under the conditions mentioned above is very close to unity).

 As a result of this, the voltage difference ΔU acting between the inputs of the operational amplifier 5 changes insignificantly in time, maintaining with a fairly high accuracy the constancy of the stored output voltage of the device.

 When resuming signals at the control and information inputs 13 and 14 of the device (Fig. 1), the first and second capacitors 1 and 2 are recharged with time constants (4) and (5). Moreover, if the level of the information signal does not exceed the level of the stored voltage, then the first and second capacitors 1 and 2 are discharged, and in the reverse situation of these signals they are recharged to the level of the analyzed signal.

 The proposed device (figure 1) works similarly if the attenuator 7 is implemented according to the schemes presented in figure 2,3. The only difference is that the required voltage at the second output 15 of the attenuator 7 (Fig. 2, a) and the resistance equivalent to the resistance of the third resistor 18 (Fig. 1) are created using a divider consisting of the fourth and fifth resistors 20 and 21 , similarly to the divider made on the first and second resistors 16 and 17, with the same denominations. The effect achieved in this case will turn out to be the same if the coefficient K included in expressions (7), (8) is identical for both divisors. However, the apparent simplicity of such an implementation of the attenuator 7 (figure 2), for example, for integral performance is quite complicated due to the difficulties of performing two exact dividers with identical parameters.

 In the case of the implementation of the attenuator 7 according to the scheme shown in figure 3, the third resistor 18 is connected to the first output 11, which acts on the desired voltage value. In this case, the charging conditions of the first and second capacitors 1 and 2 are somewhat worse (Fig. 1), since there is a relationship between the charging circuits. However, when high accuracy of signal processing is not required, this embodiment of the attenuator 7 (Fig. 3) can be widely used in practice.

 The proposed device in comparison with the known technical solutions, including the prototype device, which is currently the best designed sample and which in this regard is taken as the base object, has an increased accuracy of storing analog information. A significant increase in the accuracy of information storage is achieved by providing identical and sufficiently large discharge time constants of storage capacitors by creating a potential difference between the information input and output of the first and second keys 3 and 4, which is close to zero. This allows you to increase their equivalent resistance in the off state really tens or hundreds of times.

 The gain in the accuracy of storing analog information is determined theoretically.

Ue

-

U_вых(t)-(U+ΔU)

K_o, (9) где U и U + ΔU - напряжения, действующие на первом и втором конденсаторах 1 и 2 в момент времени, когда устройство переходит в режим хранения информации; Δt - текущее время, отсчитываемое с момента перехода устройства в режим хранения информации; К_о - коэффициент передачи операционного усилителя 5.The change in the output voltage of the device in the information storage mode in time t is mathematically described as follows:
U _{o (t)} =

Ue

-

U _{o (t)} - (U + ΔU)

K _o , (9) where U and U + ΔU are the voltages acting on the first and second capacitors 1 and 2 at the time when the device goes into information storage mode; Δt is the current time counted from the moment the device enters the information storage mode; To _about - the transfer coefficient of the operational amplifier 5.

U

e

+

1+

. (10)
В начальный момент времени, когда Δt= = 0,
U_вых(o)= U

=

. (11)
Полагая, что по свойствам операционного усилителя 5 ΔU =

, выражение (11) позволяет найти:
U_вых(0) = 2U (12)
и

=

. (13)
С учетом соотношений (12) и (13) уравнение (10) приобретает вид:
U_вых(t)= U

(14)
Отсюда находим погрешность хранения информации в предлагаемом устройстве
δU_вых(t)=

-1 =

(15)
Так как

≪ 1, то соотношение для погрешности хранения информации (15) принимает удобный для практического использования вид:
δU_вых(t)=

. (16)
При условии равенства постоянных времени разряда (7), (8) выражение (16) упрощается:
δU

- 1. (17)
Выражение (16) может характеризовать и погрешность хранения информации в устройстве-прототипе, если в нем постоянные времени разряда

(7) и

(8) заменить на соответствующие постоянные времени разряда

и τ^p2^*. В устройстве-прототипе только второй ключ 4 находится под разностью потенциалов, близкой к нулю, поэтому постоянная времени разряда первого конденсатора

= (R₆ + R_выкл.1 + R_i), C₁ ≈ R_выкл C, (18)
а постоянная времени разряда второго конденсатора

соответствует постоянной времени разряда (8) предлагаемого устройства (

=

) . В связи с этим погрешность хранения информации в устройстве-прототипе
δU $\genfrac{}{}{0ex}{}{\text{*}}{\text{в}}$ _ых(t)=

. (19)
Выигрыш в точности хранения информации, который обеспечивает предлагаемое устройство по отношению к устройству-прототипу, определим на основании сравнения соотношений (17) и (19):
B =

0

_ 1

. (20)
Пусть Δt = 10 с, С = 10^-6 Ф⁽¹⁾; r_вкл = 10³ Ом (2); R_выкл = 10⁸ Ом (3); К = 0,99; К_о = 10⁵, R =5 ˙10³ Ом; R_i = 100 Ом, тогда R₆ = 3,9 кОм (6); τ₃₁= τ₃₂= 6 ˙10^-3 с (4), (5),

100 с (18);

=

10⁴ с (7), (8); δU

= 0,1% (17); δU_вых(t) ^*= 4,808% (19); В = 48,08 (20).The relation (9) is presented in another form:
U _{o (t)} =

U

e

+

1+

. (10)
At the initial moment of time, when Δt = = 0,
U _{o (o)} = U

=

. (eleven)
Assuming that according to the properties of the operational amplifier 5 ΔU =

, expression (11) allows you to find:
U _{o (0)} = 2U (12)
and

=

. (thirteen)
Given relations (12) and (13), equation (10) takes the form:
U _{o (t)} = U

(14)
From here we find the error of information storage in the proposed device
δU o _(t) =

-1 =

(fifteen)
As

≪ 1, then the ratio for the error of information storage (15) takes the form convenient for practical use:
δU o _(t) =

. (sixteen)
Provided that the discharge time constants are equal (7), (8), expression (16) is simplified:
δU

- 1. (17)
Expression (16) can also characterize the error in storing information in the prototype device, if it contains discharge time constants

(7) and

(8) replace with appropriate discharge time constants

and τ ^p 2 ^* . In the prototype device, only the second key 4 is under a potential difference close to zero, therefore, the discharge time constant of the first capacitor

= (R ₆ + R _{off 1} + R _i ), C ₁ ≈ R _off C, (18)
and the discharge time constant of the second capacitor

corresponds to the discharge time constant (8) of the proposed device (

=

) In this regard, the error in the storage of information in the device prototype
δU $\genfrac{}{}{0ex}{}{\text{*}}{\text{at}}$ _{s (t)} =

. (nineteen)
The gain in the accuracy of information storage, which provides the proposed device in relation to the prototype device, we define based on a comparison of relations (17) and (19):
B =

0

_ 1

. (twenty)
Let Δt = 10 s, C = 10 ^-6 F ⁽¹⁾ ; r _on = 10 ³ Ohms (2); R _off = 10 ⁸ Ohms (3); K = 0.99; To _about = 10 ⁵ , R = 5 ˙ 10 ³ Ohms; R _i = 100 Ohms, then R ₆ = 3.9 kOhm (6); τ ₃₁ = τ ₃₂ = 6 ˙ 10 ^-3 s (4), (5),

100 s (18);

=

10 ⁴ s (7), (8); δU

= 0.1% (17); δU o _(t) ^* = 4.808% (19); B = 48.08 (20).

 Thus, the proposed device is efficient and can be used as a functional element of microelectronics in the processing of both low-frequency and high-frequency information in high-precision measuring and other systems.

Claims (3)

 1. ANALOGUE MEMORY DEVICE containing the first and second storage capacitors, two keys, an operational amplifier, as well as a load resistor and an attenuator, the output of the first key through a load resistor connected to the first output of the first storage capacitor and a non-inverting input of the operational amplifier, the output of which is connected with the first output of the second storage capacitor and the input of the attenuator, the first output of which is connected to the information input of the second key, the output of which is connected to by the input of the operational amplifier and the second output of the second storage capacitor, the second output of the first storage capacitor is connected to the zero potential bus, and the control inputs of the first and second keys are the input of the device selection, characterized in that, in order to increase the accuracy of the device, the third key is inserted into it , the information input of which is the information input of the device, the control input is connected to the control input of the first key, and the output of the third key is connected to the information the input of the first key and the second output of the attenuator.  2. The device according to claim 1, characterized in that the attenuator consists of a repeater on the second operational amplifier, a limiting element on the resistor and voltage divider, the first input of which is the input of the attenuator, the second input is connected to the zero potential bus, and the output is connected to a non-inverting input the second operational amplifier and is the first output of the attenuator, the inverting input of the second operational amplifier is connected to its output and the first output of the limiting element on the resistor, the second output of which is the second output of the attenuator.  3. The device according to claim 1, characterized in that the attenuator consists of the first and second voltage dividers, the first inputs of which are combined and are the input of the attenuator, the second inputs are connected to the zero potential bus, and the outputs are the first and second outputs of the attenuator, respectively.

Images